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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_wishbone.vhd] - Blame information for rev 23

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - External Bus Interface (WISHBONE) >>                                             #
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-- # ********************************************************************************************* #
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-- # The interface is either unregistered (INTERFACE_REG_STAGES = 0), only outgoing signals are    #
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-- # registered (INTERFACE_REG_STAGES = 1) or incoming and outgoing signals are registered         #
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-- # (INTERFACE_REG_STAGES = 2).                                                                   #
7 23 zero_gravi
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
8 2 zero_gravi
-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- #
9 23 zero_gravi
-- # loader or the internal instruction or data memories (if implemented), are delegated via this  #
10 2 zero_gravi
-- # Wishbone gateway to the external bus interface.                                               #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
42
 
43
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
46
 
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library neorv32;
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use neorv32.neorv32_package.all;
49
 
50
entity neorv32_wishbone is
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  generic (
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    INTERFACE_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
53 23 zero_gravi
    -- Internal instruction memory --
54 2 zero_gravi
    MEM_INT_IMEM_USE     : boolean := true;   -- implement processor-internal instruction memory
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    MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
56 23 zero_gravi
    -- Internal data memory --
57 2 zero_gravi
    MEM_INT_DMEM_USE     : boolean := true;   -- implement processor-internal data memory
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    MEM_INT_DMEM_SIZE    : natural := 4*1024  -- size of processor-internal data memory in bytes
59
  );
60
  port (
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    -- global control --
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    clk_i    : in  std_ulogic; -- global clock line
63
    rstn_i   : in  std_ulogic; -- global reset line, low-active
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    -- host access --
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    addr_i   : in  std_ulogic_vector(31 downto 0); -- address
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    rden_i   : in  std_ulogic; -- read enable
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    wren_i   : in  std_ulogic; -- write enable
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    ben_i    : in  std_ulogic_vector(03 downto 0); -- byte write enable
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    data_i   : in  std_ulogic_vector(31 downto 0); -- data in
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    data_o   : out std_ulogic_vector(31 downto 0); -- data out
71 11 zero_gravi
    cancel_i : in  std_ulogic; -- cancel current bus transaction
72 2 zero_gravi
    ack_o    : out std_ulogic; -- transfer acknowledge
73
    err_o    : out std_ulogic; -- transfer error
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    -- wishbone interface --
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    wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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    wb_dat_i : in  std_ulogic_vector(31 downto 0); -- read data
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    wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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    wb_we_o  : out std_ulogic; -- read/write
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    wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
80
    wb_stb_o : out std_ulogic; -- strobe
81
    wb_cyc_o : out std_ulogic; -- valid cycle
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    wb_ack_i : in  std_ulogic; -- transfer acknowledge
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    wb_err_i : in  std_ulogic  -- transfer error
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  );
85
end neorv32_wishbone;
86
 
87
architecture neorv32_wishbone_rtl of neorv32_wishbone is
88
 
89
  -- access control --
90
  signal int_imem_acc, int_imem_acc_real : std_ulogic;
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  signal int_dmem_acc, int_dmem_acc_real : std_ulogic;
92 23 zero_gravi
  signal int_boot_acc                    : std_ulogic;
93 2 zero_gravi
  signal wb_access                       : std_ulogic;
94 23 zero_gravi
  signal wb_access_ff, wb_access_ff_ff   : std_ulogic;
95
  signal rb_en                           : std_ulogic;
96 2 zero_gravi
 
97
  -- bus arbiter --
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  signal wb_stb_ff0 : std_ulogic;
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  signal wb_stb_ff1 : std_ulogic;
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  signal wb_cyc_ff  : std_ulogic;
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  signal wb_ack_ff  : std_ulogic;
102
  signal wb_err_ff  : std_ulogic;
103
 
104 23 zero_gravi
  -- data read-back --
105
  signal wb_rdata : std_ulogic_vector(31 downto 0);
106
 
107 2 zero_gravi
begin
108
 
109
  -- Sanity Check ---------------------------------------------------------------------------
110
  -- -------------------------------------------------------------------------------------------
111 23 zero_gravi
  assert (INTERFACE_REG_STAGES <= 2) report "NEORV32 CONFIG ERROR! Number of external memory interface buffer stages must be 0, 1 or 2." severity error;
112
  assert (INTERFACE_REG_STAGES /= 0) report "NEORV32 CONFIG WARNING! External memory interface without register stages is still experimental for peripherals with more than 1 cycle latency." severity warning;
113 2 zero_gravi
 
114
 
115
  -- Access Control -------------------------------------------------------------------------
116
  -- -------------------------------------------------------------------------------------------
117
  -- access to internal IMEM or DMEM? --
118 23 zero_gravi
  int_imem_acc <= '1' when (addr_i >= imem_base_c) and (addr_i < std_ulogic_vector(unsigned(imem_base_c) + MEM_INT_IMEM_SIZE)) else '0';
119
  int_dmem_acc <= '1' when (addr_i >= dmem_base_c) and (addr_i < std_ulogic_vector(unsigned(dmem_base_c) + MEM_INT_DMEM_SIZE)) else '0';
120 2 zero_gravi
  int_imem_acc_real <= int_imem_acc when (MEM_INT_IMEM_USE = true) else '0';
121
  int_dmem_acc_real <= int_dmem_acc when (MEM_INT_DMEM_USE = true) else '0';
122 23 zero_gravi
  int_boot_acc <= '1' when (addr_i >= boot_rom_base_c) else '0'; -- this also covers access to the IO space
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--int_io_acc   <= '1' when (addr_i >= io_base_c) else '0';
124 2 zero_gravi
 
125
  -- actual external bus access? --
126 23 zero_gravi
  wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc) and (wren_i or rden_i);
127 2 zero_gravi
 
128
 
129
  -- Bus Arbiter -----------------------------------------------------------------------------
130
  -- -------------------------------------------------------------------------------------------
131
  bus_arbiter: process(rstn_i, clk_i)
132
  begin
133
    if (rstn_i = '0') then
134 23 zero_gravi
      wb_cyc_ff       <= '0';
135
      wb_stb_ff1      <= '0';
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      wb_stb_ff0      <= '0';
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      wb_ack_ff       <= '0';
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      wb_err_ff       <= '0';
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      wb_access_ff    <= '0';
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      wb_access_ff_ff <= '0';
141 2 zero_gravi
    elsif rising_edge(clk_i) then
142
      -- bus cycle --
143
      if (INTERFACE_REG_STAGES = 0) then
144
        wb_cyc_ff <= '0'; -- unused
145 11 zero_gravi
      else
146 23 zero_gravi
        wb_cyc_ff <= (wb_cyc_ff or wb_access) and (not wb_ack_i) and (not wb_err_i) and (not cancel_i);
147 2 zero_gravi
      end if;
148
      -- bus strobe --
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      wb_stb_ff1 <= wb_stb_ff0;
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      wb_stb_ff0 <= wb_access;
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      -- bus ack --
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      wb_ack_ff <= wb_ack_i;
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      -- bus err --
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      wb_err_ff <= wb_err_i;
155 23 zero_gravi
      -- access still active? --
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      wb_access_ff_ff <= wb_access_ff;
157
      if (wb_access = '1') then
158
        wb_access_ff <= '1';
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      elsif ((wb_ack_i or wb_err_i or cancel_i) = '1') then
160
        wb_access_ff <= '0';
161
      end if;
162 2 zero_gravi
    end if;
163
  end process bus_arbiter;
164
 
165
  -- bus cycle --
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  wb_cyc_o <= wb_access when (INTERFACE_REG_STAGES = 0) else wb_cyc_ff;
167
 
168
  -- bus_strobe: rising edge detector --
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  wb_stb_o <= (wb_access and (not wb_stb_ff0)) when (INTERFACE_REG_STAGES = 0) else (wb_stb_ff0 and (not wb_stb_ff1));
170
 
171
  -- cpu ack --
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  ack_o <= wb_ack_ff when (INTERFACE_REG_STAGES = 2) else wb_ack_i;
173
 
174
  -- cpu err --
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  err_o <= wb_err_ff when (INTERFACE_REG_STAGES = 2) else wb_err_i;
176
 
177 23 zero_gravi
  -- cpu read-data --
178
  rb_en  <= wb_access_ff_ff when (INTERFACE_REG_STAGES = 2) else wb_access_ff;
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  data_o <= wb_rdata when (rb_en = '1') else (others => '0');
180 2 zero_gravi
 
181 23 zero_gravi
 
182 2 zero_gravi
  -- Bus Buffer -----------------------------------------------------------------------------
183
  -- -------------------------------------------------------------------------------------------
184
  interface_reg_level_zero:
185
  if (INTERFACE_REG_STAGES = 0) generate -- 0 register levels: direct connection
186 23 zero_gravi
    wb_rdata <= wb_dat_i;
187 2 zero_gravi
    wb_adr_o <= addr_i;
188
    wb_dat_o <= data_i;
189
    wb_sel_o <= ben_i;
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    wb_we_o  <= wren_i;
191
  end generate;
192
 
193
  interface_reg_level_one:
194
  if (INTERFACE_REG_STAGES = 1) generate -- 1 register levels: buffer outgoing signals
195
    buffer_stages_one: process(clk_i)
196
    begin
197
      if rising_edge(clk_i) then
198 11 zero_gravi
        if (wb_cyc_ff = '0') then
199
          wb_adr_o <= addr_i;
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          wb_dat_o <= data_i;
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          wb_sel_o <= ben_i;
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          wb_we_o  <= wren_i;
203
        end if;
204 2 zero_gravi
      end if;
205
    end process buffer_stages_one;
206 23 zero_gravi
    wb_rdata <= wb_dat_i;
207 2 zero_gravi
  end generate;
208
 
209
  interface_reg_level_two:
210
  if (INTERFACE_REG_STAGES = 2) generate -- 2 register levels: buffer incoming and outgoing signals
211
    buffer_stages_two: process(clk_i)
212
    begin
213
      if rising_edge(clk_i) then
214 11 zero_gravi
        if (wb_cyc_ff = '0') then
215
          wb_adr_o <= addr_i;
216
          wb_dat_o <= data_i;
217
          wb_sel_o <= ben_i;
218
          wb_we_o  <= wren_i;
219
        end if;
220 23 zero_gravi
        if (wb_ack_i = '1') then
221
          wb_rdata <= wb_dat_i;
222
        end if;
223 2 zero_gravi
      end if;
224
    end process buffer_stages_two;
225
  end generate;
226
 
227
 
228
end neorv32_wishbone_rtl;

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