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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_wishbone.vhd] - Blame information for rev 37

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1 2 zero_gravi
-- #################################################################################################
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-- # << NEORV32 - External Bus Interface (WISHBONE) >>                                             #
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-- # ********************************************************************************************* #
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-- # The interface provides registers for all outgoing signals. If the host cancels a running      #
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-- # transfer, the Wishbone arbiter still waits some time for the bus system to ACK to transfer.   #
6 23 zero_gravi
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
7 2 zero_gravi
-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- #
8 23 zero_gravi
-- # loader or the internal instruction or data memories (if implemented), are delegated via this  #
9 2 zero_gravi
-- # Wishbone gateway to the external bus interface.                                               #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false)    #
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-- # and also pipelined transactions (WB_PIPELINED_MODE = true).                                   #
13 2 zero_gravi
-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
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45
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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52
entity neorv32_wishbone is
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  generic (
54 35 zero_gravi
    WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
55 23 zero_gravi
    -- Internal instruction memory --
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    MEM_INT_IMEM_USE  : boolean := true;   -- implement processor-internal instruction memory
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    MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
58 23 zero_gravi
    -- Internal data memory --
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    MEM_INT_DMEM_USE  : boolean := true;   -- implement processor-internal data memory
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    MEM_INT_DMEM_SIZE : natural := 4*1024  -- size of processor-internal data memory in bytes
61 2 zero_gravi
  );
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  port (
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    -- global control --
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    clk_i    : in  std_ulogic; -- global clock line
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    rstn_i   : in  std_ulogic; -- global reset line, low-active
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    -- host access --
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    src_i    : in  std_ulogic; -- access type (0: data, 1:instruction)
68 2 zero_gravi
    addr_i   : in  std_ulogic_vector(31 downto 0); -- address
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    rden_i   : in  std_ulogic; -- read enable
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    wren_i   : in  std_ulogic; -- write enable
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    ben_i    : in  std_ulogic_vector(03 downto 0); -- byte write enable
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    data_i   : in  std_ulogic_vector(31 downto 0); -- data in
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    data_o   : out std_ulogic_vector(31 downto 0); -- data out
74 11 zero_gravi
    cancel_i : in  std_ulogic; -- cancel current bus transaction
75 2 zero_gravi
    ack_o    : out std_ulogic; -- transfer acknowledge
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    err_o    : out std_ulogic; -- transfer error
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    priv_i   : in  std_ulogic_vector(1 downto 0); -- current CPU privilege level
78 2 zero_gravi
    -- wishbone interface --
79 36 zero_gravi
    wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag
80 2 zero_gravi
    wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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    wb_dat_i : in  std_ulogic_vector(31 downto 0); -- read data
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    wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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    wb_we_o  : out std_ulogic; -- read/write
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    wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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    wb_stb_o : out std_ulogic; -- strobe
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    wb_cyc_o : out std_ulogic; -- valid cycle
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    wb_ack_i : in  std_ulogic; -- transfer acknowledge
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    wb_err_i : in  std_ulogic  -- transfer error
89
  );
90
end neorv32_wishbone;
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92
architecture neorv32_wishbone_rtl of neorv32_wishbone is
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94 35 zero_gravi
  -- constants --
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  constant wb_timeout_c : natural := bus_timeout_c/2;
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97 2 zero_gravi
  -- access control --
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  signal int_imem_acc, int_imem_acc_real : std_ulogic;
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  signal int_dmem_acc, int_dmem_acc_real : std_ulogic;
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  signal int_boot_acc                    : std_ulogic;
101 2 zero_gravi
  signal wb_access                       : std_ulogic;
102
 
103 35 zero_gravi
  -- bus arbiter
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  type ctrl_state_t is (IDLE, BUSY, CANCELED);
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  type ctrl_t is record
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    state      : ctrl_state_t;
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    state_prev : ctrl_state_t;
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    we         : std_ulogic;
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    rd_req     : std_ulogic;
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    wr_req     : std_ulogic;
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    adr        : std_ulogic_vector(31 downto 0);
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    wdat       : std_ulogic_vector(31 downto 0);
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    rdat       : std_ulogic_vector(31 downto 0);
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    sel        : std_ulogic_vector(3 downto 0);
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    ack        : std_ulogic;
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    err        : std_ulogic;
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    timeout    : std_ulogic_vector(index_size_f(wb_timeout_c)-1 downto 0);
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    src        : std_ulogic;
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    priv       : std_ulogic_vector(1 downto 0);
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  end record;
121 36 zero_gravi
  signal ctrl    : ctrl_t;
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  signal stb_int : std_ulogic;
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  signal cyc_int : std_ulogic;
124 2 zero_gravi
 
125
begin
126
 
127 35 zero_gravi
  -- Sanity Checks --------------------------------------------------------------------------
128 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
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  assert not (bus_timeout_c <= 15) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (bus_timeout_c) should be >16 for interfacing external modules." severity error;
130 2 zero_gravi
 
131
 
132
  -- Access Control -------------------------------------------------------------------------
133
  -- -------------------------------------------------------------------------------------------
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  -- access to internal IMEM or DMEM? --
135 31 zero_gravi
  int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) else '0';
136
  int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) else '0';
137 2 zero_gravi
  int_imem_acc_real <= int_imem_acc when (MEM_INT_IMEM_USE = true) else '0';
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  int_dmem_acc_real <= int_dmem_acc when (MEM_INT_DMEM_USE = true) else '0';
139 31 zero_gravi
 
140
  -- access to internal BOOTROM or IO devices? --
141 23 zero_gravi
  int_boot_acc <= '1' when (addr_i >= boot_rom_base_c) else '0'; -- this also covers access to the IO space
142 31 zero_gravi
--int_boot_acc <= '1' when (addr_i(31 downto index_size_f(2*boot_rom_max_size_c)) = boot_rom_base_c(31 downto index_size_f(2*boot_rom_max_size_c))) else '0'; -- this also covers access to the IO space
143 23 zero_gravi
--int_io_acc   <= '1' when (addr_i >= io_base_c) else '0';
144 2 zero_gravi
 
145
  -- actual external bus access? --
146 35 zero_gravi
  wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc);
147 2 zero_gravi
 
148
  -- Bus Arbiter -----------------------------------------------------------------------------
149
  -- -------------------------------------------------------------------------------------------
150
  bus_arbiter: process(rstn_i, clk_i)
151
  begin
152
    if (rstn_i = '0') then
153 35 zero_gravi
      ctrl.state      <= IDLE;
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      ctrl.state_prev <= IDLE;
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      ctrl.we         <= '0';
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      ctrl.rd_req     <= '0';
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      ctrl.wr_req     <= '0';
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      ctrl.adr        <= (others => '0');
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      ctrl.wdat       <= (others => '0');
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      ctrl.rdat       <= (others => '0');
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      ctrl.sel        <= (others => '0');
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      ctrl.timeout    <= (others => '0');
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      ctrl.ack        <= '0';
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      ctrl.err        <= '0';
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      ctrl.src        <= '0';
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      ctrl.priv       <= "00";
167 2 zero_gravi
    elsif rising_edge(clk_i) then
168 35 zero_gravi
      -- defaults --
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      ctrl.state_prev <= ctrl.state;
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      ctrl.rdat       <= (others => '0');
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      ctrl.ack        <= '0';
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      ctrl.err        <= '0';
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      ctrl.timeout    <= std_ulogic_vector(to_unsigned(wb_timeout_c, index_size_f(wb_timeout_c)));
174 2 zero_gravi
 
175 35 zero_gravi
      -- state machine --
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      case ctrl.state is
177 2 zero_gravi
 
178 35 zero_gravi
        when IDLE => -- waiting for host request
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        -- ------------------------------------------------------------
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          ctrl.rd_req <= '0';
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          ctrl.wr_req <= '0';
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          -- buffer all outgoing signals --
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          ctrl.we   <= wren_i;
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          ctrl.adr  <= addr_i;
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          ctrl.wdat <= data_i;
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          ctrl.sel  <= ben_i;
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          ctrl.src  <= src_i;
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          ctrl.priv <= priv_i;
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          -- valid read/write access --
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          if ((wb_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
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            ctrl.state <= BUSY;
192
          end if;
193 2 zero_gravi
 
194 35 zero_gravi
        when BUSY => -- transfer in progress
195
        -- ------------------------------------------------------------
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          ctrl.rdat <= wb_dat_i;
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          if (cancel_i = '1') then -- transfer canceled by host
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            ctrl.state <= CANCELED;
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          elsif (wb_err_i = '1') then -- abnormal bus termination
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            ctrl.err   <= '1';
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            ctrl.state <= CANCELED;
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          elsif (wb_ack_i = '1') then -- normal bus termination
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            ctrl.ack   <= '1';
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            ctrl.state <= IDLE;
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          end if;
206 2 zero_gravi
 
207 35 zero_gravi
        when CANCELED => -- 
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        -- ------------------------------------------------------------
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          ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
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          ctrl.rd_req <= ctrl.rd_req or rden_i; -- buffer new request
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          -- wait for bus.peripheral to ACK transfer (as "aborted" but still somehow "completed")
212
          -- or wait for a timeout and force termination
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          ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
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          if (wb_ack_i = '1') or (or_all_f(ctrl.timeout) = '0') then
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            ctrl.state <= IDLE;
216
          end if;
217 2 zero_gravi
 
218 35 zero_gravi
        when others => -- undefined
219
        -- ------------------------------------------------------------
220
          ctrl.state <= IDLE;
221 2 zero_gravi
 
222 35 zero_gravi
      end case;
223
    end if;
224
  end process bus_arbiter;
225 23 zero_gravi
 
226 35 zero_gravi
  -- host access --
227
  data_o   <= ctrl.rdat;
228
  ack_o    <= ctrl.ack;
229
  err_o    <= ctrl.err;
230 2 zero_gravi
 
231 35 zero_gravi
  -- wishbone interface --
232 36 zero_gravi
  wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
233
  wb_tag_o(1) <= '0'; -- 0=secure, 1=non-secure
234
  wb_tag_o(2) <= ctrl.src; -- 0=data access, 1=instruction access
235
 
236 35 zero_gravi
  wb_adr_o <= ctrl.adr;
237
  wb_dat_o <= ctrl.wdat;
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  wb_we_o  <= ctrl.we;
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  wb_sel_o <= ctrl.sel;
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  wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
241
  wb_cyc_o <= cyc_int;
242 2 zero_gravi
 
243 35 zero_gravi
  stb_int  <= '1' when ((ctrl.state = BUSY) and (ctrl.state_prev = IDLE)) else '0';
244
  cyc_int  <= '0' when (ctrl.state = IDLE) else '1';
245 2 zero_gravi
 
246 35 zero_gravi
 
247 2 zero_gravi
end neorv32_wishbone_rtl;

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