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2 |
zero_gravi |
-- #################################################################################################
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2 |
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # ********************************************************************************************* #
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35 |
zero_gravi |
-- # The interface provides registers for all outgoing signals. If the host cancels a running #
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-- # transfer, the Wishbone arbiter still waits some time for the bus system to ACK to transfer. #
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zero_gravi |
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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7 |
2 |
zero_gravi |
-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- #
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8 |
23 |
zero_gravi |
-- # loader or the internal instruction or data memories (if implemented), are delegated via this #
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9 |
2 |
zero_gravi |
-- # Wishbone gateway to the external bus interface. #
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10 |
35 |
zero_gravi |
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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11 |
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-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) #
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12 |
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-- # and also pipelined transactions (WB_PIPELINED_MODE = true). #
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13 |
2 |
zero_gravi |
-- # ********************************************************************************************* #
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14 |
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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34 |
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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35 |
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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36 |
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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37 |
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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39 |
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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43 |
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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48 |
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49 |
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library neorv32;
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50 |
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use neorv32.neorv32_package.all;
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51 |
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52 |
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entity neorv32_wishbone is
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53 |
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generic (
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54 |
35 |
zero_gravi |
WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
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55 |
23 |
zero_gravi |
-- Internal instruction memory --
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56 |
35 |
zero_gravi |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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57 |
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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58 |
23 |
zero_gravi |
-- Internal data memory --
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59 |
35 |
zero_gravi |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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60 |
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MEM_INT_DMEM_SIZE : natural := 4*1024 -- size of processor-internal data memory in bytes
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61 |
2 |
zero_gravi |
);
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62 |
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port (
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63 |
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-- global control --
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64 |
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clk_i : in std_ulogic; -- global clock line
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65 |
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rstn_i : in std_ulogic; -- global reset line, low-active
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66 |
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-- host access --
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67 |
36 |
zero_gravi |
src_i : in std_ulogic; -- access type (0: data, 1:instruction)
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68 |
2 |
zero_gravi |
addr_i : in std_ulogic_vector(31 downto 0); -- address
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69 |
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rden_i : in std_ulogic; -- read enable
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70 |
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wren_i : in std_ulogic; -- write enable
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71 |
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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72 |
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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73 |
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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74 |
11 |
zero_gravi |
cancel_i : in std_ulogic; -- cancel current bus transaction
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75 |
2 |
zero_gravi |
ack_o : out std_ulogic; -- transfer acknowledge
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76 |
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err_o : out std_ulogic; -- transfer error
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77 |
36 |
zero_gravi |
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
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78 |
2 |
zero_gravi |
-- wishbone interface --
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79 |
36 |
zero_gravi |
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag
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80 |
2 |
zero_gravi |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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81 |
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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82 |
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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83 |
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wb_we_o : out std_ulogic; -- read/write
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84 |
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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85 |
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wb_stb_o : out std_ulogic; -- strobe
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86 |
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wb_cyc_o : out std_ulogic; -- valid cycle
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87 |
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wb_ack_i : in std_ulogic; -- transfer acknowledge
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88 |
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wb_err_i : in std_ulogic -- transfer error
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89 |
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);
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90 |
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end neorv32_wishbone;
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91 |
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|
92 |
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architecture neorv32_wishbone_rtl of neorv32_wishbone is
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93 |
|
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|
94 |
35 |
zero_gravi |
-- constants --
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95 |
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|
constant wb_timeout_c : natural := bus_timeout_c/2;
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96 |
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|
|
97 |
2 |
zero_gravi |
-- access control --
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98 |
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signal int_imem_acc, int_imem_acc_real : std_ulogic;
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99 |
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signal int_dmem_acc, int_dmem_acc_real : std_ulogic;
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100 |
23 |
zero_gravi |
signal int_boot_acc : std_ulogic;
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101 |
2 |
zero_gravi |
signal wb_access : std_ulogic;
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102 |
|
|
|
103 |
35 |
zero_gravi |
-- bus arbiter
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104 |
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type ctrl_state_t is (IDLE, BUSY, CANCELED);
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105 |
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type ctrl_t is record
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106 |
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state : ctrl_state_t;
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107 |
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state_prev : ctrl_state_t;
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108 |
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we : std_ulogic;
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109 |
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rd_req : std_ulogic;
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110 |
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wr_req : std_ulogic;
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111 |
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adr : std_ulogic_vector(31 downto 0);
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112 |
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wdat : std_ulogic_vector(31 downto 0);
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113 |
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rdat : std_ulogic_vector(31 downto 0);
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114 |
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sel : std_ulogic_vector(3 downto 0);
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115 |
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ack : std_ulogic;
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116 |
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err : std_ulogic;
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117 |
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timeout : std_ulogic_vector(index_size_f(wb_timeout_c)-1 downto 0);
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118 |
36 |
zero_gravi |
src : std_ulogic;
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119 |
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priv : std_ulogic_vector(1 downto 0);
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120 |
35 |
zero_gravi |
end record;
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121 |
36 |
zero_gravi |
signal ctrl : ctrl_t;
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122 |
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signal stb_int : std_ulogic;
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123 |
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signal cyc_int : std_ulogic;
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124 |
2 |
zero_gravi |
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125 |
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begin
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126 |
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127 |
35 |
zero_gravi |
-- Sanity Checks --------------------------------------------------------------------------
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128 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
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129 |
35 |
zero_gravi |
assert not (bus_timeout_c <= 15) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (bus_timeout_c) should be >16 for interfacing external modules." severity error;
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130 |
2 |
zero_gravi |
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131 |
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132 |
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-- Access Control -------------------------------------------------------------------------
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133 |
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-- -------------------------------------------------------------------------------------------
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134 |
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-- access to internal IMEM or DMEM? --
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135 |
31 |
zero_gravi |
int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) else '0';
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136 |
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int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) else '0';
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137 |
2 |
zero_gravi |
int_imem_acc_real <= int_imem_acc when (MEM_INT_IMEM_USE = true) else '0';
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138 |
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int_dmem_acc_real <= int_dmem_acc when (MEM_INT_DMEM_USE = true) else '0';
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139 |
31 |
zero_gravi |
|
140 |
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-- access to internal BOOTROM or IO devices? --
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141 |
23 |
zero_gravi |
int_boot_acc <= '1' when (addr_i >= boot_rom_base_c) else '0'; -- this also covers access to the IO space
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142 |
31 |
zero_gravi |
--int_boot_acc <= '1' when (addr_i(31 downto index_size_f(2*boot_rom_max_size_c)) = boot_rom_base_c(31 downto index_size_f(2*boot_rom_max_size_c))) else '0'; -- this also covers access to the IO space
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143 |
23 |
zero_gravi |
--int_io_acc <= '1' when (addr_i >= io_base_c) else '0';
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144 |
2 |
zero_gravi |
|
145 |
|
|
-- actual external bus access? --
|
146 |
35 |
zero_gravi |
wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc);
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147 |
2 |
zero_gravi |
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148 |
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|
-- Bus Arbiter -----------------------------------------------------------------------------
|
149 |
|
|
-- -------------------------------------------------------------------------------------------
|
150 |
|
|
bus_arbiter: process(rstn_i, clk_i)
|
151 |
|
|
begin
|
152 |
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|
if (rstn_i = '0') then
|
153 |
35 |
zero_gravi |
ctrl.state <= IDLE;
|
154 |
|
|
ctrl.state_prev <= IDLE;
|
155 |
|
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ctrl.we <= '0';
|
156 |
|
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ctrl.rd_req <= '0';
|
157 |
|
|
ctrl.wr_req <= '0';
|
158 |
|
|
ctrl.adr <= (others => '0');
|
159 |
|
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ctrl.wdat <= (others => '0');
|
160 |
|
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ctrl.rdat <= (others => '0');
|
161 |
|
|
ctrl.sel <= (others => '0');
|
162 |
|
|
ctrl.timeout <= (others => '0');
|
163 |
|
|
ctrl.ack <= '0';
|
164 |
|
|
ctrl.err <= '0';
|
165 |
36 |
zero_gravi |
ctrl.src <= '0';
|
166 |
|
|
ctrl.priv <= "00";
|
167 |
2 |
zero_gravi |
elsif rising_edge(clk_i) then
|
168 |
35 |
zero_gravi |
-- defaults --
|
169 |
|
|
ctrl.state_prev <= ctrl.state;
|
170 |
|
|
ctrl.rdat <= (others => '0');
|
171 |
|
|
ctrl.ack <= '0';
|
172 |
|
|
ctrl.err <= '0';
|
173 |
|
|
ctrl.timeout <= std_ulogic_vector(to_unsigned(wb_timeout_c, index_size_f(wb_timeout_c)));
|
174 |
2 |
zero_gravi |
|
175 |
35 |
zero_gravi |
-- state machine --
|
176 |
|
|
case ctrl.state is
|
177 |
2 |
zero_gravi |
|
178 |
35 |
zero_gravi |
when IDLE => -- waiting for host request
|
179 |
|
|
-- ------------------------------------------------------------
|
180 |
|
|
ctrl.rd_req <= '0';
|
181 |
|
|
ctrl.wr_req <= '0';
|
182 |
|
|
-- buffer all outgoing signals --
|
183 |
|
|
ctrl.we <= wren_i;
|
184 |
|
|
ctrl.adr <= addr_i;
|
185 |
|
|
ctrl.wdat <= data_i;
|
186 |
|
|
ctrl.sel <= ben_i;
|
187 |
36 |
zero_gravi |
ctrl.src <= src_i;
|
188 |
|
|
ctrl.priv <= priv_i;
|
189 |
35 |
zero_gravi |
-- valid read/write access --
|
190 |
|
|
if ((wb_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
|
191 |
|
|
ctrl.state <= BUSY;
|
192 |
|
|
end if;
|
193 |
2 |
zero_gravi |
|
194 |
35 |
zero_gravi |
when BUSY => -- transfer in progress
|
195 |
|
|
-- ------------------------------------------------------------
|
196 |
|
|
ctrl.rdat <= wb_dat_i;
|
197 |
|
|
if (cancel_i = '1') then -- transfer canceled by host
|
198 |
|
|
ctrl.state <= CANCELED;
|
199 |
|
|
elsif (wb_err_i = '1') then -- abnormal bus termination
|
200 |
|
|
ctrl.err <= '1';
|
201 |
|
|
ctrl.state <= CANCELED;
|
202 |
|
|
elsif (wb_ack_i = '1') then -- normal bus termination
|
203 |
|
|
ctrl.ack <= '1';
|
204 |
|
|
ctrl.state <= IDLE;
|
205 |
|
|
end if;
|
206 |
2 |
zero_gravi |
|
207 |
35 |
zero_gravi |
when CANCELED => --
|
208 |
|
|
-- ------------------------------------------------------------
|
209 |
|
|
ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
|
210 |
|
|
ctrl.rd_req <= ctrl.rd_req or rden_i; -- buffer new request
|
211 |
|
|
-- wait for bus.peripheral to ACK transfer (as "aborted" but still somehow "completed")
|
212 |
|
|
-- or wait for a timeout and force termination
|
213 |
|
|
ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
|
214 |
|
|
if (wb_ack_i = '1') or (or_all_f(ctrl.timeout) = '0') then
|
215 |
|
|
ctrl.state <= IDLE;
|
216 |
|
|
end if;
|
217 |
2 |
zero_gravi |
|
218 |
35 |
zero_gravi |
when others => -- undefined
|
219 |
|
|
-- ------------------------------------------------------------
|
220 |
|
|
ctrl.state <= IDLE;
|
221 |
2 |
zero_gravi |
|
222 |
35 |
zero_gravi |
end case;
|
223 |
|
|
end if;
|
224 |
|
|
end process bus_arbiter;
|
225 |
23 |
zero_gravi |
|
226 |
35 |
zero_gravi |
-- host access --
|
227 |
|
|
data_o <= ctrl.rdat;
|
228 |
|
|
ack_o <= ctrl.ack;
|
229 |
|
|
err_o <= ctrl.err;
|
230 |
2 |
zero_gravi |
|
231 |
35 |
zero_gravi |
-- wishbone interface --
|
232 |
36 |
zero_gravi |
wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
|
233 |
|
|
wb_tag_o(1) <= '0'; -- 0=secure, 1=non-secure
|
234 |
|
|
wb_tag_o(2) <= ctrl.src; -- 0=data access, 1=instruction access
|
235 |
|
|
|
236 |
35 |
zero_gravi |
wb_adr_o <= ctrl.adr;
|
237 |
|
|
wb_dat_o <= ctrl.wdat;
|
238 |
|
|
wb_we_o <= ctrl.we;
|
239 |
|
|
wb_sel_o <= ctrl.sel;
|
240 |
|
|
wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
|
241 |
|
|
wb_cyc_o <= cyc_int;
|
242 |
2 |
zero_gravi |
|
243 |
35 |
zero_gravi |
stb_int <= '1' when ((ctrl.state = BUSY) and (ctrl.state_prev = IDLE)) else '0';
|
244 |
|
|
cyc_int <= '0' when (ctrl.state = IDLE) else '1';
|
245 |
2 |
zero_gravi |
|
246 |
35 |
zero_gravi |
|
247 |
2 |
zero_gravi |
end neorv32_wishbone_rtl;
|