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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_xirq.vhd] - Blame information for rev 66

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-- #################################################################################################
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-- # << NEORV32 - External Interrupt Controller (XIRQ) >>                                          #
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-- # ********************************************************************************************* #
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-- # Simple interrupt controller for platform (processor-external) interrupts. Up to 32 channels   #
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-- # are supported that get (optionally) prioritized into a single CPU interrupt.                  #
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-- #                                                                                               #
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-- # The actual trigger configuration has to be done BEFORE synthesis using the XIRQ_TRIGGER_TYPE  #
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-- # and XIRQ_TRIGGER_POLARITY generics. These allow to configure channel-independent low-level,   #
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-- # high-level, falling-edge and rising-edge triggers.                                            #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_xirq is
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  generic (
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    XIRQ_NUM_CH           : natural; -- number of external IRQ channels (0..32)
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    XIRQ_TRIGGER_TYPE     : std_ulogic_vector(31 downto 0); -- trigger type: 0=level, 1=edge
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    XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0)  -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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  );
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  port (
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    -- host access --
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    clk_i     : in  std_ulogic; -- global clock line
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    addr_i    : in  std_ulogic_vector(31 downto 0); -- address
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    rden_i    : in  std_ulogic; -- read enable
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    wren_i    : in  std_ulogic; -- write enable
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    data_i    : in  std_ulogic_vector(31 downto 0); -- data in
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    data_o    : out std_ulogic_vector(31 downto 0); -- data out
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    ack_o     : out std_ulogic; -- transfer acknowledge
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    -- external interrupt lines --
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    xirq_i    : in  std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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    -- CPU interrupt --
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    cpu_irq_o : out std_ulogic
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  );
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end neorv32_xirq;
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architecture neorv32_xirq_rtl of neorv32_xirq is
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  -- IO space: module base address --
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  constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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  constant lo_abb_c : natural := index_size_f(xirq_size_c); -- low address boundary bit
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  -- access control --
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  signal acc_en : std_ulogic; -- module access enable
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  signal addr   : std_ulogic_vector(31 downto 0); -- access address
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  signal wren   : std_ulogic; -- word write enable
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  signal rden   : std_ulogic; -- read enable
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  -- control registers --
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  signal irq_enable  : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: interrupt enable
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  signal clr_pending : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: clear pending IRQs
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  signal irq_src     : std_ulogic_vector(4 downto 0); -- r/w: source IRQ, ACK on any write
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  -- interrupt trigger --
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  signal irq_sync  : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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  signal irq_sync2 : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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  signal irq_trig  : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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  -- interrupt buffer --
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  signal irq_buf  : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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  signal irq_fire : std_ulogic;
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  -- interrupt source --
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  signal irq_src_nxt : std_ulogic_vector(4 downto 0);
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  -- arbiter --
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  signal irq_run : std_ulogic;
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begin
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  -- Sanity Checks --------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  assert not ((XIRQ_NUM_CH < 0) or (XIRQ_NUM_CH > 32)) report "NEORV32 PROCESSOR CONFIG ERROR: Number of XIRQ inputs <XIRQ_NUM_CH> has to be 0..32." severity error;
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  -- Access Control -------------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = xirq_base_c(hi_abb_c downto lo_abb_c)) else '0';
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  addr   <= xirq_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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  wren   <= acc_en and wren_i;
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  rden   <= acc_en and rden_i;
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  -- Read/Write Access ----------------------------------------------------------------------
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  -- -------------------------------------------------------------------------------------------
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  rw_access: process(clk_i)
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  begin
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    if rising_edge(clk_i) then
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      -- bus handshake --
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      ack_o <= rden or wren;
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      -- write access --
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      clr_pending <= (others => '1');
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      if (wren = '1') then
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        -- channel-enable --
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        if (addr = xirq_enable_addr_c) then
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          irq_enable <= data_i(XIRQ_NUM_CH-1 downto 0);
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        end if;
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        -- clear pending IRQs --
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        if (addr = xirq_pending_addr_c) then
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          clr_pending <= data_i(XIRQ_NUM_CH-1 downto 0); -- set zero to clear pending IRQ
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        end if;
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      end if;
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      -- read access --
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      data_o <= (others => '0');
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      if (rden = '1') then
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        case addr is
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          when xirq_enable_addr_c  => data_o(XIRQ_NUM_CH-1 downto 0) <= irq_enable; -- channel-enable
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          when xirq_pending_addr_c => data_o(XIRQ_NUM_CH-1 downto 0) <= irq_buf; -- pending IRQs
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          when xirq_source_addr_c  => data_o(4 downto 0) <= irq_src; -- source IRQ
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          when others => NULL;
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        end case;
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      end if;
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    end if;
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  end process rw_access;
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  -- IRQ Trigger --------------------------------------------------------------
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  -- -----------------------------------------------------------------------------
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  irq_trigger: process(clk_i)
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  begin
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    if rising_edge(clk_i) then
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      irq_sync  <= xirq_i;
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      irq_sync2 <= irq_sync;
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    end if;
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  end process irq_trigger;
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  irq_trigger_comb: process(irq_sync, irq_sync2)
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    variable sel_v : std_ulogic_vector(1 downto 0);
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  begin
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    for i in 0 to XIRQ_NUM_CH-1 loop
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      sel_v := XIRQ_TRIGGER_TYPE(i) & XIRQ_TRIGGER_POLARITY(i);
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      case sel_v is
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        when "00"   => irq_trig(i) <= not irq_sync(i); -- low-level
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        when "01"   => irq_trig(i) <= irq_sync(i); -- high-level
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        when "10"   => irq_trig(i) <= (not irq_sync(i)) and irq_sync2(i); -- falling-edge
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        when "11"   => irq_trig(i) <= irq_sync(i) and (not irq_sync2(i)); -- rising-edge
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        when others => irq_trig(i) <= '0';
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      end case;
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    end loop;
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  end process irq_trigger_comb;
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  -- IRQ Buffer ---------------------------------------------------------------
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  -- -----------------------------------------------------------------------------
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  irq_buffer: process(clk_i)
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  begin
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    if rising_edge(clk_i) then
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      irq_buf <= (irq_buf or (irq_trig and irq_enable)) and clr_pending;
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    end if;
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  end process irq_buffer;
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  -- anyone firing? --
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  irq_fire <= or_reduce_f(irq_buf);
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  -- IRQ Priority Encoder -----------------------------------------------------
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  -- -----------------------------------------------------------------------------
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  irq_priority: process(irq_buf)
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  begin
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    irq_src_nxt <= (others => '0');
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    if (XIRQ_NUM_CH > 1) then
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      for i in 0 to XIRQ_NUM_CH-1 loop
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        if (irq_buf(i) = '1') then
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          irq_src_nxt(index_size_f(XIRQ_NUM_CH)-1 downto 0) <= std_ulogic_vector(to_unsigned(i, index_size_f(XIRQ_NUM_CH)));
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          exit;
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        end if;
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      end loop;
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    end if;
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  end process irq_priority;
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  -- IRQ Arbiter --------------------------------------------------------------
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  -- -----------------------------------------------------------------------------
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  irq_arbiter: process(clk_i)
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  begin
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    if rising_edge(clk_i) then
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      if (irq_run = '0') then -- no active IRQ
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        if (irq_fire = '1') then
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          irq_run <= '1';
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          irq_src <= irq_src_nxt;
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        end if;
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      else -- active IRQ, wait for CPU to acknowledge
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        if (wren = '1') and (addr = xirq_source_addr_c) then -- write _any_ value to acknowledge
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          irq_run <= '0';
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        end if;
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      end if;
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    end if;
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  end process irq_arbiter;
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  -- interrupt request --
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  cpu_irq_o <= irq_run;
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end neorv32_xirq_rtl;

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