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[/] [neorv32/] [trunk/] [rtl/] [processor_templates/] [neorv32_ProcessorTop_MinimalBoot.vhd] - Blame information for rev 64

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1 63 zero_gravi
-- #################################################################################################
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-- # << NEORV32 - Minimal setup with the bootloader enabled >>                                     #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
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-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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entity neorv32_ProcessorTop_MinimalBoot is
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  generic (
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    CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
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    INT_BOOTLOADER_EN            : boolean := true;   -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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    HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
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47
    -- RISC-V CPU Extensions --
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    CPU_EXTENSION_RISCV_A        : boolean := true;   -- implement atomic extension?
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    CPU_EXTENSION_RISCV_C        : boolean := true;   -- implement compressed extension?
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    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
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    CPU_EXTENSION_RISCV_M        : boolean := true;   -- implement mul/div extension?
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    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
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    CPU_EXTENSION_RISCV_Zfinx    : boolean := false;  -- implement 32-bit floating-point extension (using INT regs!)
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    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
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    CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
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57
    -- Extension Options --
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    FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
59
    FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
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    CPU_CNT_WIDTH                : natural := 34;     -- total width of CPU cycle and instret counters (0..64)
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    -- Physical Memory Protection (PMP) --
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    PMP_NUM_REGIONS              : natural := 0;       -- number of regions (0..64)
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    PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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    -- Hardware Performance Monitors (HPM) --
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    HPM_NUM_CNTS                 : natural := 0;       -- number of implemented HPM counters (0..29)
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    HPM_CNT_WIDTH                : natural := 40;      -- total size of HPM counters (0..64)
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    -- Internal Instruction memory --
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    MEM_INT_IMEM_EN              : boolean := true;    -- implement processor-internal instruction memory
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    MEM_INT_IMEM_SIZE            : natural := 64*1024; -- size of processor-internal instruction memory in bytes
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    -- Internal Data memory --
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    MEM_INT_DMEM_EN              : boolean := true;    -- implement processor-internal data memory
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    MEM_INT_DMEM_SIZE            : natural := 64*1024; -- size of processor-internal data memory in bytes
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    -- Internal Cache memory --
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    ICACHE_EN                    : boolean := false;  -- implement instruction cache
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    ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
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    ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
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    ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
83
 
84
    -- Processor peripherals --
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    IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
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    IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
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    IO_UART0_EN                  : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
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    IO_PWM_NUM_CH                : natural := 3;      -- number of PWM channels to implement (0..60); 0 = disabled
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    IO_WDT_EN                    : boolean := true    -- implement watch dog timer (WDT)?
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  );
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  port (
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    clk_i      : in  std_logic;
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    rstn_i     : in  std_logic;
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95
    -- GPIO (available if IO_GPIO_EN = true) --
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    gpio_o     : out std_ulogic_vector(3 downto 0);
97
 
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    -- primary UART0 (available if IO_UART0_EN = true) --
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    uart_txd_o : out std_ulogic; -- UART0 send data
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    uart_rxd_i : in  std_ulogic := '0'; -- UART0 receive data
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    uart_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
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    uart_cts_i : in  std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
103
 
104
    -- PWM (available if IO_PWM_NUM_CH > 0) --
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    pwm_o      : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0)
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  );
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end entity;
108
 
109
architecture neorv32_ProcessorTop_MinimalBoot_rtl of neorv32_ProcessorTop_MinimalBoot is
110
 
111
  -- internal IO connection --
112
  signal con_gpio_o : std_ulogic_vector(63 downto 0);
113
 
114
begin
115
 
116
  -- IO Connection --------------------------------------------------------------------------
117
  -- -------------------------------------------------------------------------------------------
118
 
119
  -- GPIO --
120
  gpio_o <= con_gpio_o(3 downto 0);
121
 
122
  -- The core of the problem ----------------------------------------------------------------
123
  -- -------------------------------------------------------------------------------------------
124
  neorv32_inst: entity neorv32.neorv32_top
125
  generic map (
126
    -- General --
127
    CLOCK_FREQUENCY              => CLOCK_FREQUENCY,  -- clock frequency of clk_i in Hz
128
    INT_BOOTLOADER_EN            => INT_BOOTLOADER_EN,-- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
129
    HW_THREAD_ID                 => HW_THREAD_ID,     -- hardware thread id (32-bit)
130
 
131
    -- On-Chip Debugger (OCD) --
132
    ON_CHIP_DEBUGGER_EN          => false,  -- implement on-chip debugger?
133
 
134
    -- RISC-V CPU Extensions --
135
    CPU_EXTENSION_RISCV_A        => CPU_EXTENSION_RISCV_A,         -- implement atomic extension?
136
    CPU_EXTENSION_RISCV_C        => CPU_EXTENSION_RISCV_C,         -- implement compressed extension?
137
    CPU_EXTENSION_RISCV_E        => CPU_EXTENSION_RISCV_E,         -- implement embedded RF extension?
138
    CPU_EXTENSION_RISCV_M        => CPU_EXTENSION_RISCV_M,         -- implement mul/div extension?
139
    CPU_EXTENSION_RISCV_U        => CPU_EXTENSION_RISCV_U,         -- implement user mode extension?
140
    CPU_EXTENSION_RISCV_Zfinx    => CPU_EXTENSION_RISCV_Zfinx,     -- implement 32-bit floating-point extension (using INT regs!)
141
    CPU_EXTENSION_RISCV_Zicsr    => CPU_EXTENSION_RISCV_Zicsr,     -- implement CSR system?
142
    CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei,  -- implement instruction stream sync.?
143
 
144
    -- Extension Options --
145
    FAST_MUL_EN                  => FAST_MUL_EN,    -- use DSPs for M extension's multiplier
146
    FAST_SHIFT_EN                => FAST_SHIFT_EN,  -- use barrel shifter for shift operations
147
    CPU_CNT_WIDTH                => CPU_CNT_WIDTH,  -- total width of CPU cycle and instret counters (0..64)
148
 
149
    -- Physical Memory Protection (PMP) --
150
    PMP_NUM_REGIONS              => PMP_NUM_REGIONS,       -- number of regions (0..64)
151
    PMP_MIN_GRANULARITY          => PMP_MIN_GRANULARITY,   -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
152
 
153
    -- Hardware Performance Monitors (HPM) --
154
    HPM_NUM_CNTS                 => HPM_NUM_CNTS,          -- number of implemented HPM counters (0..29)
155
    HPM_CNT_WIDTH                => HPM_CNT_WIDTH,         -- total size of HPM counters (1..64)
156
 
157
    -- Internal Instruction memory --
158
    MEM_INT_IMEM_EN              => MEM_INT_IMEM_EN,       -- implement processor-internal instruction memory
159
    MEM_INT_IMEM_SIZE            => MEM_INT_IMEM_SIZE,     -- size of processor-internal instruction memory in bytes
160
 
161
    -- Internal Data memory --
162
    MEM_INT_DMEM_EN              => MEM_INT_DMEM_EN,       -- implement processor-internal data memory
163
    MEM_INT_DMEM_SIZE            => MEM_INT_DMEM_SIZE,     -- size of processor-internal data memory in bytes
164
 
165
    -- Internal Cache memory --
166
    ICACHE_EN                    => ICACHE_EN,             -- implement instruction cache
167
    ICACHE_NUM_BLOCKS            => ICACHE_NUM_BLOCKS,     -- i-cache: number of blocks (min 1), has to be a power of 2
168
    ICACHE_BLOCK_SIZE            => ICACHE_BLOCK_SIZE,     -- i-cache: block size in bytes (min 4), has to be a power of 2
169
    ICACHE_ASSOCIATIVITY         => ICACHE_ASSOCIATIVITY,  -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
170
 
171
    -- External memory interface --
172
    MEM_EXT_EN                   => false,       -- implement external memory bus interface?
173
    MEM_EXT_TIMEOUT              => 0,           -- cycles after a pending bus access auto-terminates (0 = disabled)
174
 
175
    -- Processor peripherals --
176
    IO_GPIO_EN                   => IO_GPIO_EN,    -- implement general purpose input/output port unit (GPIO)?
177
    IO_MTIME_EN                  => IO_MTIME_EN,   -- implement machine system timer (MTIME)?
178
    IO_UART0_EN                  => IO_UART0_EN,   -- implement primary universal asynchronous receiver/transmitter (UART0)?
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    IO_UART1_EN                  => false,         -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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    IO_SPI_EN                    => false,         -- implement serial peripheral interface (SPI)?
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    IO_TWI_EN                    => false,         -- implement two-wire interface (TWI)?
182
    IO_PWM_NUM_CH                => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled
183
    IO_WDT_EN                    => IO_WDT_EN,     -- implement watch dog timer (WDT)?
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    IO_TRNG_EN                   => false,         -- implement true random number generator (TRNG)?
185
    IO_CFS_EN                    => false,         -- implement custom functions subsystem (CFS)?
186
    IO_CFS_CONFIG                => x"00000000",   -- custom CFS configuration generic
187
    IO_CFS_IN_SIZE               => 32,            -- size of CFS input conduit in bits
188
    IO_CFS_OUT_SIZE              => 32,            -- size of CFS output conduit in bits
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    IO_NEOLED_EN                 => false          -- implement NeoPixel-compatible smart LED interface (NEOLED)?
190
  )
191
  port map (
192
    -- Global control --
193
    clk_i       => clk_i,                        -- global clock, rising edge
194
    rstn_i      => rstn_i,                       -- global reset, low-active, async
195
 
196
    -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
197
    jtag_trst_i => '0',                          -- low-active TAP reset (optional)
198
    jtag_tck_i  => '0',                          -- serial clock
199
    jtag_tdi_i  => '0',                          -- serial data input
200
    jtag_tdo_o  => open,                         -- serial data output
201
    jtag_tms_i  => '0',                          -- mode select
202
 
203
    -- Wishbone bus interface (available if MEM_EXT_EN = true) --
204
    wb_tag_o    => open,                         -- request tag
205
    wb_adr_o    => open,                         -- address
206
    wb_dat_i    => (others => '0'),              -- read data
207
    wb_dat_o    => open,                         -- write data
208
    wb_we_o     => open,                         -- read/write
209
    wb_sel_o    => open,                         -- byte enable
210
    wb_stb_o    => open,                         -- strobe
211
    wb_cyc_o    => open,                         -- valid cycle
212
    wb_lock_o   => open,                         -- exclusive access request
213
    wb_ack_i    => '0',                          -- transfer acknowledge
214
    wb_err_i    => '0',                          -- transfer error
215
 
216
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
217
    fence_o     => open,                         -- indicates an executed FENCE operation
218
    fencei_o    => open,                         -- indicates an executed FENCEI operation
219
 
220
    -- GPIO (available if IO_GPIO_EN = true) --
221
    gpio_o      => con_gpio_o,                   -- parallel output
222
    gpio_i      => (others => '0'),              -- parallel input
223
 
224
    -- primary UART0 (available if IO_UART0_EN = true) --
225
    uart0_txd_o => uart_txd_o,                   -- UART0 send data
226
    uart0_rxd_i => uart_rxd_i,                   -- UART0 receive data
227
    uart0_rts_o => uart_rts_o,                   -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
228
    uart0_cts_i => uart_cts_i,                   -- hw flow control: UART0.TX allowed to transmit, low-active, optional
229
 
230
    -- secondary UART1 (available if IO_UART1_EN = true) --
231
    uart1_txd_o => open,                         -- UART1 send data
232
    uart1_rxd_i => '0',                          -- UART1 receive data
233
    uart1_rts_o => open,                         -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
234
    uart1_cts_i => '0',                          -- hw flow control: UART1.TX allowed to transmit, low-active, optional
235
 
236
    -- SPI (available if IO_SPI_EN = true) --
237
    spi_sck_o   => open,                         -- SPI serial clock
238
    spi_sdo_o   => open,                         -- controller data out, peripheral data in
239
    spi_sdi_i   => '0',                          -- controller data in, peripheral data out
240
    spi_csn_o   => open,                         -- SPI CS
241
 
242
    -- TWI (available if IO_TWI_EN = true) --
243
    twi_sda_io  => open,                         -- twi serial data line
244
    twi_scl_io  => open,                         -- twi serial clock line
245
 
246
    -- PWM (available if IO_PWM_NUM_CH > 0) --
247
    pwm_o       => pwm_o,                        -- pwm channels
248
 
249
    -- Custom Functions Subsystem IO --
250
    cfs_in_i    => (others => '0'),              -- custom CFS inputs conduit
251
    cfs_out_o   => open,                         -- custom CFS outputs conduit
252
 
253
    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
254
    neoled_o    => open,                         -- async serial data line
255
 
256
    -- System time --
257
    mtime_i     => (others => '0'),              -- current system time from ext. MTIME (if IO_MTIME_EN = false)
258
    mtime_o     => open,                         -- current system time from int. MTIME (if IO_MTIME_EN = true)
259
 
260
    -- Interrupts --
261
    mtime_irq_i => '0',                          -- machine timer interrupt, available if IO_MTIME_EN = false
262
    msw_irq_i   => '0',                          -- machine software interrupt
263
    mext_irq_i  => '0'                           -- machine external interrupt
264
  );
265
 
266
end architecture;

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