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[/] [neorv32/] [trunk/] [rtl/] [system_integration/] [neorv32_SystemTop_AvalonMM.vhd] - Blame information for rev 72

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1 64 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Processor Top Entity with AvalonMM Compatible Master Interface >>                #
3
-- # ********************************************************************************************* #
4
-- # (c) "AvalonMM", "NIOS-2", "Qsys", "MegaWizard"  and "Platform Designer"                       # 
5
-- # are trademarks of Intel                                                                       #
6
-- # ********************************************************************************************* #
7
-- # BSD 3-Clause License                                                                          #
8
-- #                                                                                               #
9 70 zero_gravi
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
10 64 zero_gravi
-- #                                                                                               #
11
-- # Redistribution and use in source and binary forms, with or without modification, are          #
12
-- # permitted provided that the following conditions are met:                                     #
13
-- #                                                                                               #
14
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
15
-- #    conditions and the following disclaimer.                                                   #
16
-- #                                                                                               #
17
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
18
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
19
-- #    provided with the distribution.                                                            #
20
-- #                                                                                               #
21
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
22
-- #    endorse or promote products derived from this software without specific prior written      #
23
-- #    permission.                                                                                #
24
-- #                                                                                               #
25
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
26
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
27
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
28
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
29
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
30
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
31
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
32
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
33
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
34
-- # ********************************************************************************************* #
35
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
36
-- #################################################################################################
37
 
38
library ieee;
39
use ieee.std_logic_1164.all;
40
use ieee.numeric_std.all;
41
 
42
library neorv32;
43
use neorv32.neorv32_package.all;
44
 
45
entity neorv32_top_avalonmm is
46
  generic (
47
    -- General --
48
    CLOCK_FREQUENCY              : natural;           -- clock frequency of clk_i in Hz
49
    HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
50
    INT_BOOTLOADER_EN            : boolean := false;  -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
51
 
52
    -- On-Chip Debugger (OCD) --
53
    ON_CHIP_DEBUGGER_EN          : boolean := false;  -- implement on-chip debugger
54
 
55
    -- RISC-V CPU Extensions --
56
    CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
57 66 zero_gravi
    CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit-manipulation extension?
58 64 zero_gravi
    CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
59
    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
60
    CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement mul/div extension?
61
    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
62
    CPU_EXTENSION_RISCV_Zfinx    : boolean := false;  -- implement 32-bit floating-point extension (using INT regs!)
63
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
64 66 zero_gravi
    CPU_EXTENSION_RISCV_Zicntr   : boolean := true;   -- implement base counters?
65
    CPU_EXTENSION_RISCV_Zihpm    : boolean := false;  -- implement hardware performance monitors?
66 64 zero_gravi
    CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
67
    CPU_EXTENSION_RISCV_Zmmul    : boolean := false;  -- implement multiply-only M sub-extension?
68 72 zero_gravi
    CPU_EXTENSION_RISCV_Zxcfu    : boolean := false;  -- implement custom (instr.) functions unit?
69 64 zero_gravi
 
70
    -- Extension Options --
71
    FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
72
    FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
73
    CPU_CNT_WIDTH                : natural := 64;     -- total width of CPU cycle and instret counters (0..64)
74
    CPU_IPB_ENTRIES              : natural := 2;      -- entries is instruction prefetch buffer, has to be a power of 2
75
 
76
    -- Physical Memory Protection (PMP) --
77
    PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
78
    PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
79
 
80
    -- Hardware Performance Monitors (HPM) --
81
    HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
82
    HPM_CNT_WIDTH                : natural := 40;     -- total size of HPM counters (0..64)
83
 
84
    -- Internal Instruction memory (IMEM) --
85
    MEM_INT_IMEM_EN              : boolean := false;  -- implement processor-internal instruction memory
86
    MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
87
 
88
    -- Internal Data memory (DMEM) --
89
    MEM_INT_DMEM_EN              : boolean := false;  -- implement processor-internal data memory
90
    MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
91
 
92
    -- Internal Cache memory (iCACHE) --
93
    ICACHE_EN                    : boolean := false;  -- implement instruction cache
94
    ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
95
    ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
96
    ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
97
 
98
    -- Stream link interface (SLINK) --
99
    SLINK_NUM_TX                 : natural := 0;      -- number of TX links (0..8)
100
    SLINK_NUM_RX                 : natural := 0;      -- number of TX links (0..8)
101
    SLINK_TX_FIFO                : natural := 1;      -- TX fifo depth, has to be a power of two
102
    SLINK_RX_FIFO                : natural := 1;      -- RX fifo depth, has to be a power of two
103
 
104
    -- External Interrupts Controller (XIRQ) --
105
    XIRQ_NUM_CH                  : natural := 0;      -- number of external IRQ channels (0..32)
106
    XIRQ_TRIGGER_TYPE            : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
107
    XIRQ_TRIGGER_POLARITY        : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
108
 
109
    -- Processor peripherals --
110
    IO_GPIO_EN                   : boolean := false;  -- implement general purpose input/output port unit (GPIO)?
111
    IO_MTIME_EN                  : boolean := false;  -- implement machine system timer (MTIME)?
112
    IO_UART0_EN                  : boolean := false;  -- implement primary universal asynchronous receiver/transmitter (UART0)?
113 65 zero_gravi
    IO_UART0_RX_FIFO             : natural := 1;      -- RX fifo depth, has to be a power of two, min 1
114
    IO_UART0_TX_FIFO             : natural := 1;      -- TX fifo depth, has to be a power of two, min 1
115 64 zero_gravi
    IO_UART1_EN                  : boolean := false;  -- implement secondary universal asynchronous receiver/transmitter (UART1)?
116 65 zero_gravi
    IO_UART1_RX_FIFO             : natural := 1;      -- RX fifo depth, has to be a power of two, min 1
117
    IO_UART1_TX_FIFO             : natural := 1;      -- TX fifo depth, has to be a power of two, min 1
118 64 zero_gravi
    IO_SPI_EN                    : boolean := false;  -- implement serial peripheral interface (SPI)?
119
    IO_TWI_EN                    : boolean := false;  -- implement two-wire interface (TWI)?
120
    IO_PWM_NUM_CH                : natural := 0;      -- number of PWM channels to implement (0..60); 0 = disabled
121
    IO_WDT_EN                    : boolean := false;  -- implement watch dog timer (WDT)?
122
    IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
123
    IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
124
    IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
125
    IO_CFS_IN_SIZE               : positive := 32;    -- size of CFS input conduit in bits
126
    IO_CFS_OUT_SIZE              : positive := 32;    -- size of CFS output conduit in bits
127
    IO_NEOLED_EN                 : boolean := false;  -- implement NeoPixel-compatible smart LED interface (NEOLED)?
128 67 zero_gravi
    IO_NEOLED_TX_FIFO            : natural := 1;      -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
129 70 zero_gravi
    IO_GPTMR_EN                  : boolean := false;  -- implement general purpose timer (GPTMR)?
130
    IO_XIP_EN                    : boolean := false   -- implement execute in place module (XIP)?
131 64 zero_gravi
  );
132
  port (
133
    -- Global control --
134
    clk_i          : in  std_ulogic; -- global clock, rising edge
135
    rstn_i         : in  std_ulogic; -- global reset, low-active, async
136
 
137
    -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
138
    jtag_trst_i    : in  std_ulogic := 'U'; -- low-active TAP reset (optional)
139
    jtag_tck_i     : in  std_ulogic := 'U'; -- serial clock
140
    jtag_tdi_i     : in  std_ulogic := 'U'; -- serial data input
141
    jtag_tdo_o     : out std_ulogic;        -- serial data output
142
    jtag_tms_i     : in  std_ulogic := 'U'; -- mode select
143
 
144
    -- AvalonMM interface
145
    read_o         : out std_logic;
146
    write_o        : out std_logic;
147 70 zero_gravi
    waitrequest_i  : in  std_logic := '0';
148 64 zero_gravi
    byteenable_o   : out std_logic_vector(3 downto 0);
149
    address_o      : out std_logic_vector(31 downto 0);
150
    writedata_o    : out std_logic_vector(31 downto 0);
151 70 zero_gravi
    readdata_i     : in  std_logic_vector(31 downto 0) := (others => '0');
152 64 zero_gravi
 
153
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
154
    fence_o        : out std_ulogic; -- indicates an executed FENCE operation
155
    fencei_o       : out std_ulogic; -- indicates an executed FENCEI operation
156
 
157 70 zero_gravi
    -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
158
    xip_csn_o      : out std_ulogic; -- chip-select, low-active
159
    xip_clk_o      : out std_ulogic; -- serial clock
160
    xip_sdi_i      : in  std_ulogic := 'L'; -- device data input
161
    xip_sdo_o      : out std_ulogic; -- controller data output
162
 
163 64 zero_gravi
    -- TX stream interfaces (available if SLINK_NUM_TX > 0) --
164
    slink_tx_dat_o : out sdata_8x32_t; -- output data
165
    slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
166
    slink_tx_rdy_i : in  std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send
167
 
168
    -- RX stream interfaces (available if SLINK_NUM_RX > 0) --
169
    slink_rx_dat_i : in  sdata_8x32_t := (others => (others => 'U')); -- input data
170
    slink_rx_val_i : in  std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input
171
    slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
172
 
173
    -- GPIO (available if IO_GPIO_EN = true) --
174
    gpio_o         : out std_ulogic_vector(63 downto 0); -- parallel output
175
    gpio_i         : in  std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input
176
 
177
    -- primary UART0 (available if IO_UART0_EN = true) --
178
    uart0_txd_o    : out std_ulogic; -- UART0 send data
179
    uart0_rxd_i    : in  std_ulogic := 'U'; -- UART0 receive data
180
    uart0_rts_o    : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
181
    uart0_cts_i    : in  std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
182
 
183
    -- secondary UART1 (available if IO_UART1_EN = true) --
184
    uart1_txd_o    : out std_ulogic; -- UART1 send data
185
    uart1_rxd_i    : in  std_ulogic := 'U'; -- UART1 receive data
186
    uart1_rts_o    : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
187
    uart1_cts_i    : in  std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
188
 
189
    -- SPI (available if IO_SPI_EN = true) --
190
    spi_sck_o      : out std_ulogic; -- SPI serial clock
191
    spi_sdo_o      : out std_ulogic; -- controller data out, peripheral data in
192
    spi_sdi_i      : in  std_ulogic := 'U'; -- controller data in, peripheral data out
193
    spi_csn_o      : out std_ulogic_vector(07 downto 0); -- chip-select
194
 
195
    -- TWI (available if IO_TWI_EN = true) --
196
    twi_sda_io     : inout std_logic := 'U'; -- twi serial data line
197
    twi_scl_io     : inout std_logic := 'U'; -- twi serial clock line
198
 
199
    -- PWM (available if IO_PWM_NUM_CH > 0) --
200 70 zero_gravi
    pwm_o          : out std_ulogic_vector(59 downto 0); -- pwm channels
201 64 zero_gravi
 
202
    -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
203
    cfs_in_i       : in  std_ulogic_vector(IO_CFS_IN_SIZE-1  downto 0) := (others => 'U'); -- custom CFS inputs conduit
204
    cfs_out_o      : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
205
 
206
    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
207
    neoled_o       : out std_ulogic; -- async serial data line
208
 
209
    -- System time --
210
    mtime_i        : in  std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
211
    mtime_o        : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
212
 
213
    -- External platform interrupts (available if XIRQ_NUM_CH > 0) --
214 70 zero_gravi
    xirq_i         : in  std_ulogic_vector(31 downto 0) := (others => 'L'); -- IRQ channels
215 64 zero_gravi
 
216
    -- CPU interrupts --
217
    mtime_irq_i    : in  std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
218
    msw_irq_i      : in  std_ulogic := 'L'; -- machine software interrupt
219
    mext_irq_i     : in  std_ulogic := 'L'  -- machine external interrupt
220
  );
221
end neorv32_top_avalonmm;
222
 
223
architecture neorv32_top_avalonmm_rtl of neorv32_top_avalonmm is
224
 
225 65 zero_gravi
  -- Wishbone bus interface (available if MEM_EXT_EN = true) --
226
  signal wb_tag_o  : std_ulogic_vector(02 downto 0); -- request tag
227
  signal wb_adr_o  : std_ulogic_vector(31 downto 0); -- address
228
  signal wb_dat_i  : std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data
229
  signal wb_dat_o  : std_ulogic_vector(31 downto 0); -- write data
230
  signal wb_we_o   : std_ulogic; -- read/write
231
  signal wb_sel_o  : std_ulogic_vector(03 downto 0); -- byte enable
232
  signal wb_stb_o  : std_ulogic; -- strobe
233
  signal wb_cyc_o  : std_ulogic; -- valid cycle
234
  signal wb_lock_o : std_ulogic; -- exclusive access request
235
  signal wb_ack_i  : std_ulogic := 'L'; -- transfer acknowledge
236
  signal wb_err_i  : std_ulogic := 'L'; -- transfer error
237 64 zero_gravi
 
238
begin
239
 
240
  neorv32_top_map : neorv32_top
241
  generic map (
242
    -- General --
243
    CLOCK_FREQUENCY => CLOCK_FREQUENCY,
244
    HW_THREAD_ID => HW_THREAD_ID,
245
    INT_BOOTLOADER_EN => INT_BOOTLOADER_EN,
246
 
247
    -- On-Chip Debugger (OCD) --
248
    ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN,
249
 
250
    -- RISC-V CPU Extensions --
251
    CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A,
252 66 zero_gravi
    CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B,
253 64 zero_gravi
    CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C,
254
    CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E,
255
    CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M,
256
    CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U,
257
    CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx,
258
    CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr,
259 66 zero_gravi
    CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr,
260
    CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm,
261 64 zero_gravi
    CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei,
262
    CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul,
263 72 zero_gravi
    CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu,
264 64 zero_gravi
 
265
    -- Extension Options --
266
    FAST_MUL_EN => FAST_MUL_EN,
267
    FAST_SHIFT_EN => FAST_SHIFT_EN,
268
    CPU_CNT_WIDTH => CPU_CNT_WIDTH,
269
    CPU_IPB_ENTRIES => CPU_IPB_ENTRIES,
270
 
271
    -- Physical Memory Protection (PMP) --
272
    PMP_NUM_REGIONS => PMP_NUM_REGIONS,
273
    PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY,
274
 
275
    -- Hardware Performance Monitors (HPM) --
276
    HPM_NUM_CNTS => HPM_NUM_CNTS,
277
    HPM_CNT_WIDTH => HPM_CNT_WIDTH,
278
 
279
    -- Internal Instruction memory (IMEM) --
280
    MEM_INT_IMEM_EN => MEM_INT_IMEM_EN,
281
    MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE,
282
 
283
    -- Internal Data memory (DMEM) --
284
    MEM_INT_DMEM_EN => MEM_INT_IMEM_EN,
285
    MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE,
286
 
287
    -- Internal Cache memory (iCACHE) --
288
    ICACHE_EN => ICACHE_EN,
289
    ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS,
290
    ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE,
291
    ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY,
292
 
293
    -- External memory interface (WISHBONE) --
294
    MEM_EXT_EN => true,
295
    MEM_EXT_TIMEOUT => 0,
296
    MEM_EXT_PIPE_MODE => false,
297
    MEM_EXT_BIG_ENDIAN => false,
298
    MEM_EXT_ASYNC_RX => false,
299
 
300
    -- Stream link interface (SLINK) --
301
    SLINK_NUM_TX => SLINK_NUM_TX,
302
    SLINK_NUM_RX => SLINK_NUM_RX,
303
    SLINK_TX_FIFO => SLINK_TX_FIFO,
304
    SLINK_RX_FIFO => SLINK_RX_FIFO,
305
 
306
    -- External Interrupts Controller (XIRQ) --
307
    XIRQ_NUM_CH => XIRQ_NUM_CH,
308
    XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE,
309
    XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY,
310
 
311
    -- Processor peripherals --
312
    IO_GPIO_EN => IO_GPIO_EN,
313
    IO_MTIME_EN => IO_MTIME_EN,
314
    IO_UART0_EN => IO_UART0_EN,
315 65 zero_gravi
    IO_UART0_RX_FIFO => IO_UART0_RX_FIFO,
316
    IO_UART0_TX_FIFO => IO_UART0_TX_FIFO,
317 64 zero_gravi
    IO_UART1_EN => IO_UART1_EN,
318 65 zero_gravi
    IO_UART1_RX_FIFO => IO_UART1_RX_FIFO,
319
    IO_UART1_TX_FIFO => IO_UART1_TX_FIFO,
320 64 zero_gravi
    IO_SPI_EN => IO_SPI_EN,
321
    IO_TWI_EN => IO_TWI_EN,
322
    IO_PWM_NUM_CH => IO_PWM_NUM_CH,
323
    IO_WDT_EN => IO_WDT_EN,
324
    IO_TRNG_EN => IO_TRNG_EN,
325
    IO_CFS_EN => IO_CFS_EN,
326
    IO_CFS_CONFIG => IO_CFS_CONFIG,
327
    IO_CFS_IN_SIZE => IO_CFS_IN_SIZE,
328
    IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE,
329
    IO_NEOLED_EN => IO_NEOLED_EN,
330 67 zero_gravi
    IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO,
331 70 zero_gravi
    IO_GPTMR_EN => IO_GPTMR_EN,
332
    IO_XIP_EN => IO_XIP_EN
333 67 zero_gravi
    )
334 64 zero_gravi
  port map (
335
    -- Global control --
336
    clk_i => clk_i,
337
    rstn_i => rstn_i,
338
 
339
    -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
340
    jtag_trst_i => jtag_trst_i,
341
    jtag_tck_i => jtag_tck_i,
342
    jtag_tdi_i => jtag_tdi_i,
343
    jtag_tdo_o => jtag_tdo_o,
344
    jtag_tms_i => jtag_tms_i,
345
 
346
    -- Wishbone bus interface (available if MEM_EXT_EN = true) --
347
    wb_tag_o => wb_tag_o,
348
    wb_adr_o => wb_adr_o,
349
    wb_dat_i => wb_dat_i,
350
    wb_dat_o => wb_dat_o,
351
    wb_we_o => wb_we_o,
352
    wb_sel_o => wb_sel_o,
353
    wb_stb_o => wb_stb_o,
354
    wb_cyc_o => wb_cyc_o,
355
    wb_lock_o => wb_lock_o,
356
    wb_ack_i => wb_ack_i,
357
    wb_err_i => wb_err_i,
358
 
359
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
360
    fence_o => fence_o,
361
    fencei_o => fencei_o,
362
 
363 70 zero_gravi
    -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
364
    xip_csn_o => xip_csn_o,
365
    xip_clk_o => xip_clk_o,
366
    xip_sdi_i => xip_sdi_i,
367
    xip_sdo_o => xip_sdo_o,
368
 
369 64 zero_gravi
    -- TX stream interfaces (available if SLINK_NUM_TX > 0) --
370
    slink_tx_dat_o => slink_tx_dat_o,
371
    slink_tx_val_o => slink_tx_val_o,
372
    slink_tx_rdy_i => slink_tx_rdy_i,
373
 
374
    -- RX stream interfaces (available if SLINK_NUM_RX > 0) --
375
    slink_rx_dat_i => slink_rx_dat_i,
376
    slink_rx_val_i => slink_rx_val_i,
377
    slink_rx_rdy_o => slink_rx_rdy_o,
378
 
379
    -- GPIO (available if IO_GPIO_EN = true) --
380
    gpio_o => gpio_o,
381
    gpio_i => gpio_i,
382
 
383
    -- primary UART0 (available if IO_UART0_EN = true) --
384
    uart0_txd_o => uart0_txd_o,
385
    uart0_rxd_i => uart0_rxd_i,
386
    uart0_rts_o => uart0_rts_o,
387
    uart0_cts_i => uart0_cts_i,
388
 
389
    -- secondary UART1 (available if IO_UART1_EN = true) --
390
    uart1_txd_o => uart1_txd_o,
391
    uart1_rxd_i => uart1_rxd_i,
392
    uart1_rts_o => uart1_rts_o,
393
    uart1_cts_i => uart1_cts_i,
394
 
395
    -- SPI (available if IO_SPI_EN = true) --
396
    spi_sck_o => spi_sck_o,
397
    spi_sdo_o => spi_sdo_o,
398
    spi_sdi_i => spi_sdi_i,
399
    spi_csn_o => spi_csn_o,
400
 
401
    -- TWI (available if IO_TWI_EN = true) --
402
    twi_sda_io => twi_sda_io,
403
    twi_scl_io => twi_scl_io,
404
 
405
    -- PWM (available if IO_PWM_NUM_CH > 0) --
406
    pwm_o => pwm_o,
407
 
408
    -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
409
    cfs_in_i => cfs_in_i,
410
    cfs_out_o => cfs_out_o,
411
 
412
    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
413
    neoled_o => neoled_o,
414
 
415
    -- System time --
416
    mtime_i => mtime_i,
417
    mtime_o => mtime_o,
418
 
419
    -- External platform interrupts (available if XIRQ_NUM_CH > 0) --
420
    xirq_i => xirq_i,
421
 
422
    -- CPU interrupts --
423
    mtime_irq_i => mtime_irq_i,
424
    msw_irq_i => msw_irq_i,
425 65 zero_gravi
    mext_irq_i => mext_irq_i
426
  );
427 64 zero_gravi
 
428 65 zero_gravi
  -- Wishbone to AvalonMM bridge
429 64 zero_gravi
  read_o <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0';
430
  write_o <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0';
431
  address_o <= std_logic_vector(wb_adr_o);
432
  writedata_o <= std_logic_vector(wb_dat_o);
433
  byteenable_o <= std_logic_vector(wb_sel_o);
434
 
435
  wb_dat_i <= std_ulogic_vector(readdata_i);
436
  wb_ack_i <= not(waitrequest_i);
437
  wb_err_i <= '0';
438
 
439
end neorv32_top_avalonmm_rtl;

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