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[/] [neorv32/] [trunk/] [rtl/] [system_integration/] [neorv32_SystemTop_axi4lite.vhd] - Blame information for rev 72

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1 63 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Processor Top Entity with AXI4-Lite Compatible Master Interface >>               #
3
-- # ********************************************************************************************* #
4
-- # (c) "AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.                         #
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-- # Note: External MTIME is not supported.                                                        #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
9 70 zero_gravi
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
10 63 zero_gravi
-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
15
-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
36
-- #################################################################################################
37
 
38
library ieee;
39
use ieee.std_logic_1164.all;
40
use ieee.numeric_std.all;
41
 
42
library neorv32;
43
use neorv32.neorv32_package.all;
44
 
45
entity neorv32_SystemTop_axi4lite is
46
  generic (
47
    -- ------------------------------------------------------------
48
    -- Configuration Generics --
49
    -- ------------------------------------------------------------
50
    -- General --
51
    CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
52
    INT_BOOTLOADER_EN            : boolean := true;   -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
53
    HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
54
    -- On-Chip Debugger (OCD) --
55
    ON_CHIP_DEBUGGER_EN          : boolean := false;  -- implement on-chip debugger
56
    -- RISC-V CPU Extensions --
57
    CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
58 66 zero_gravi
    CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit-manipulation extension?
59 63 zero_gravi
    CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
60
    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
61
    CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
62
    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
63
    CPU_EXTENSION_RISCV_Zfinx    : boolean := false;  -- implement 32-bit floating-point extension (using INT reg!)
64
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
65 66 zero_gravi
    CPU_EXTENSION_RISCV_Zicntr   : boolean := true;   -- implement base counters?
66
    CPU_EXTENSION_RISCV_Zihpm    : boolean := false;  -- implement hardware performance monitors?
67 63 zero_gravi
    CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
68 72 zero_gravi
    CPU_EXTENSION_RISCV_Zmmul    : boolean := false;  -- implement multiply-only M sub-extension?
69
    CPU_EXTENSION_RISCV_Zxcfu    : boolean := false;  -- implement custom (instr.) functions unit?
70 63 zero_gravi
    -- Extension Options --
71
    FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
72
    FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
73
    CPU_CNT_WIDTH                : natural := 64;     -- total width of CPU cycle and instret counters (0..64)
74
    -- Physical Memory Protection (PMP) --
75
    PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
76
    PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
77
    -- Hardware Performance Monitors (HPM) --
78
    HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
79
    HPM_CNT_WIDTH                : natural := 40;     -- total size of HPM counters (0..64)
80
    -- Internal Instruction memory --
81
    MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
82
    MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
83
    -- Internal Data memory --
84
    MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
85
    MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
86
    -- Internal Cache memory --
87
    ICACHE_EN                    : boolean := false;  -- implement instruction cache
88
    ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
89
    ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
90
    ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
91
    -- External Interrupts Controller (XIRQ) --
92
    XIRQ_NUM_CH                  : natural := 0;      -- number of external IRQ channels (0..32)
93
    XIRQ_TRIGGER_TYPE            : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge
94
    XIRQ_TRIGGER_POLARITY        : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
95
    -- Processor peripherals --
96
    IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
97
    IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
98
    IO_UART0_EN                  : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
99 65 zero_gravi
    IO_UART0_RX_FIFO             : natural := 1;      -- RX fifo depth, has to be a power of two, min 1
100
    IO_UART0_TX_FIFO             : natural := 1;      -- TX fifo depth, has to be a power of two, min 1
101 63 zero_gravi
    IO_UART1_EN                  : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
102 65 zero_gravi
    IO_UART1_RX_FIFO             : natural := 1;      -- RX fifo depth, has to be a power of two, min 1
103
    IO_UART1_TX_FIFO             : natural := 1;      -- TX fifo depth, has to be a power of two, min 1
104 63 zero_gravi
    IO_SPI_EN                    : boolean := true;   -- implement serial peripheral interface (SPI)?
105
    IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
106
    IO_PWM_NUM_CH                : natural := 4;      -- number of PWM channels to implement (0..60); 0 = disabled
107
    IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
108 69 zero_gravi
    IO_TRNG_EN                   : boolean := true;   -- implement true random number generator (TRNG)?
109 63 zero_gravi
    IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
110
    IO_CFS_CONFIG                : std_logic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
111
    IO_CFS_IN_SIZE               : positive := 32;    -- size of CFS input conduit in bits
112
    IO_CFS_OUT_SIZE              : positive := 32;    -- size of CFS output conduit in bits
113 65 zero_gravi
    IO_NEOLED_EN                 : boolean := true;   -- implement NeoPixel-compatible smart LED interface (NEOLED)?
114 67 zero_gravi
    IO_NEOLED_TX_FIFO            : natural := 1;      -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
115 70 zero_gravi
    IO_GPTMR_EN                  : boolean := false;  -- implement general purpose timer (GPTMR)?
116
    IO_XIP_EN                    : boolean := false   -- implement execute in place module (XIP)?
117 63 zero_gravi
  );
118
  port (
119
    -- ------------------------------------------------------------
120
    -- AXI4-Lite-Compatible Master Interface --
121
    -- ------------------------------------------------------------
122
    -- Clock and Reset --
123
    m_axi_aclk    : in  std_logic;
124
    m_axi_aresetn : in  std_logic;
125
    -- Write Address Channel --
126
    m_axi_awaddr  : out std_logic_vector(31 downto 0);
127
    m_axi_awprot  : out std_logic_vector(2 downto 0);
128
    m_axi_awvalid : out std_logic;
129
    m_axi_awready : in  std_logic;
130
    -- Write Data Channel --
131
    m_axi_wdata   : out std_logic_vector(31 downto 0);
132
    m_axi_wstrb   : out std_logic_vector(3 downto 0);
133
    m_axi_wvalid  : out std_logic;
134
    m_axi_wready  : in  std_logic;
135
    -- Read Address Channel --
136
    m_axi_araddr  : out std_logic_vector(31 downto 0);
137
    m_axi_arprot  : out std_logic_vector(2 downto 0);
138
    m_axi_arvalid : out std_logic;
139
    m_axi_arready : in  std_logic;
140
    -- Read Data Channel --
141
    m_axi_rdata   : in  std_logic_vector(31 downto 0);
142
    m_axi_rresp   : in  std_logic_vector(1 downto 0);
143
    m_axi_rvalid  : in  std_logic;
144
    m_axi_rready  : out std_logic;
145
    -- Write Response Channel --
146
    m_axi_bresp   : in  std_logic_vector(1 downto 0);
147
    m_axi_bvalid  : in  std_logic;
148
    m_axi_bready  : out std_logic;
149
    -- ------------------------------------------------------------
150
    -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
151
    -- ------------------------------------------------------------
152
    jtag_trst_i   : in  std_logic := '0'; -- low-active TAP reset (optional)
153
    jtag_tck_i    : in  std_logic := '0'; -- serial clock
154
    jtag_tdi_i    : in  std_logic := '0'; -- serial data input
155
    jtag_tdo_o    : out std_logic;        -- serial data output
156
    jtag_tms_i    : in  std_logic := '0'; -- mode select
157
    -- ------------------------------------------------------------
158
    -- Processor IO --
159
    -- ------------------------------------------------------------
160 70 zero_gravi
    -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
161
    xip_csn_o     : out std_logic; -- chip-select, low-active
162
    xip_clk_o     : out std_logic; -- serial clock
163
    xip_sdi_i     : in  std_logic := 'L'; -- device data input
164
    xip_sdo_o     : out std_logic; -- controller data output
165 63 zero_gravi
    -- GPIO (available if IO_GPIO_EN = true) --
166
    gpio_o        : out std_logic_vector(63 downto 0); -- parallel output
167
    gpio_i        : in  std_logic_vector(63 downto 0) := (others => '0'); -- parallel input
168
    -- primary UART0 (available if IO_UART0_EN = true) --
169
    uart0_txd_o   : out std_logic; -- UART0 send data
170
    uart0_rxd_i   : in  std_logic := '0'; -- UART0 receive data
171
    uart0_rts_o   : out std_logic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
172
    uart0_cts_i   : in  std_logic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
173
    -- secondary UART1 (available if IO_UART1_EN = true) --
174
    uart1_txd_o   : out std_logic; -- UART1 send data
175
    uart1_rxd_i   : in  std_logic := '0'; -- UART1 receive data
176
    uart1_rts_o   : out std_logic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
177
    uart1_cts_i   : in  std_logic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
178
    -- SPI (available if IO_SPI_EN = true) --
179
    spi_sck_o     : out std_logic; -- SPI serial clock
180
    spi_sdo_o     : out std_logic; -- controller data out, peripheral data in
181
    spi_sdi_i     : in  std_logic := '0'; -- controller data in, peripheral data out
182
    spi_csn_o     : out std_logic_vector(07 downto 0); -- SPI CS
183
    -- TWI (available if IO_TWI_EN = true) --
184
    twi_sda_io    : inout std_logic; -- twi serial data line
185
    twi_scl_io    : inout std_logic; -- twi serial clock line
186
    -- PWM (available if IO_PWM_NUM_CH > 0) --
187 70 zero_gravi
    pwm_o         : out std_logic_vector(59 downto 0);  -- pwm channels
188 63 zero_gravi
    -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
189
    cfs_in_i      : in  std_logic_vector(IO_CFS_IN_SIZE-1  downto 0); -- custom inputs
190
    cfs_out_o     : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs
191
    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
192
    neoled_o      : out std_logic; -- async serial data line
193
    -- External platform interrupts (available if XIRQ_NUM_CH > 0) --
194 70 zero_gravi
    xirq_i        : in  std_logic_vector(31 downto 0) := (others => '0'); -- IRQ channels
195 63 zero_gravi
    -- CPU Interrupts --
196
    msw_irq_i     : in  std_logic := '0'; -- machine software interrupt
197
    mext_irq_i    : in  std_logic := '0'  -- machine external interrupt
198
  );
199
end entity;
200
 
201
architecture neorv32_SystemTop_axi4lite_rtl of neorv32_SystemTop_axi4lite is
202
 
203
  -- type conversion --
204
  constant IO_CFS_CONFIG_INT         : std_ulogic_vector(31 downto 0) := std_ulogic_vector(IO_CFS_CONFIG);
205
  constant XIRQ_TRIGGER_TYPE_INT     : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_TYPE);
206
  constant XIRQ_TRIGGER_POLARITY_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_POLARITY);
207
  --
208
  signal clk_i_int       : std_ulogic;
209
  signal rstn_i_int      : std_ulogic;
210
  --
211
  signal jtag_trst_i_int :std_ulogic;
212
  signal jtag_tck_i_int  :std_ulogic;
213
  signal jtag_tdi_i_int  :std_ulogic;
214
  signal jtag_tdo_o_int  :std_ulogic;
215
  signal jtag_tms_i_int  :std_ulogic;
216
  --
217 70 zero_gravi
  signal xip_csn_o_int   : std_ulogic;
218
  signal xip_clk_o_int   : std_ulogic;
219
  signal xip_sdi_i_int   : std_ulogic;
220
  signal xip_sdo_o_int   : std_ulogic;
221
  --
222 63 zero_gravi
  signal gpio_o_int      : std_ulogic_vector(63 downto 0);
223
  signal gpio_i_int      : std_ulogic_vector(63 downto 0);
224
  --
225
  signal uart0_txd_o_int : std_ulogic;
226
  signal uart0_rxd_i_int : std_ulogic;
227
  signal uart0_rts_o_int : std_ulogic;
228
  signal uart0_cts_i_int : std_ulogic;
229
  --
230
  signal uart1_txd_o_int : std_ulogic;
231
  signal uart1_rxd_i_int : std_ulogic;
232
  signal uart1_rts_o_int : std_ulogic;
233
  signal uart1_cts_i_int : std_ulogic;
234
  --
235
  signal spi_sck_o_int   : std_ulogic;
236
  signal spi_sdo_o_int   : std_ulogic;
237
  signal spi_sdi_i_int   : std_ulogic;
238
  signal spi_csn_o_int   : std_ulogic_vector(07 downto 0);
239
  --
240 70 zero_gravi
  signal pwm_o_int       : std_ulogic_vector(59 downto 0);
241 63 zero_gravi
  --
242
  signal cfs_in_i_int    : std_ulogic_vector(IO_CFS_IN_SIZE-1  downto 0);
243
  signal cfs_out_o_int   : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0);
244
  --
245
  signal neoled_o_int    : std_ulogic;
246
  --
247 70 zero_gravi
  signal xirq_i_int      : std_ulogic_vector(31 downto 0);
248 63 zero_gravi
  --
249
  signal msw_irq_i_int   : std_ulogic;
250
  signal mext_irq_i_int  : std_ulogic;
251
 
252
  -- internal wishbone bus --
253
  type wb_bus_t is record
254
    adr  : std_ulogic_vector(31 downto 0); -- address
255
    di   : std_ulogic_vector(31 downto 0); -- processor input data
256
    do   : std_ulogic_vector(31 downto 0); -- processor output data
257
    we   : std_ulogic; -- write enable
258
    sel  : std_ulogic_vector(03 downto 0); -- byte enable
259
    stb  : std_ulogic; -- strobe
260
    cyc  : std_ulogic; -- valid cycle
261
    ack  : std_ulogic; -- transfer acknowledge
262
    err  : std_ulogic; -- transfer error
263
    tag  : std_ulogic_vector(02 downto 0); -- tag
264
    lock : std_ulogic; -- exclusive access request
265
  end record;
266
  signal wb_core : wb_bus_t;
267
 
268
  -- AXI bridge control --
269
  type ctrl_t is record
270
    radr_received : std_ulogic;
271
    wadr_received : std_ulogic;
272
    wdat_received : std_ulogic;
273
  end record;
274
  signal ctrl : ctrl_t;
275
 
276
  signal ack_read, ack_write : std_ulogic; -- normal transfer termination
277
  signal err_read, err_write : std_ulogic; -- error transfer termination
278
 
279
begin
280
 
281
  -- Sanity Checks --------------------------------------------------------------------------
282
  -- -------------------------------------------------------------------------------------------
283
  assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 PROCESSOR CONFIG WARNING: AXI4-Lite provides NO support for atomic memory operations. LR/SC access via AXI will raise a bus exception." severity warning;
284
 
285
 
286
  -- The Core Of The Problem ----------------------------------------------------------------
287
  -- -------------------------------------------------------------------------------------------
288
  neorv32_top_inst: neorv32_top
289
  generic map (
290
    -- General --
291
    CLOCK_FREQUENCY              => CLOCK_FREQUENCY,    -- clock frequency of clk_i in Hz
292
    INT_BOOTLOADER_EN            => INT_BOOTLOADER_EN,  -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
293
    HW_THREAD_ID                 => HW_THREAD_ID,       -- hardware thread id (hartid)
294
    -- On-Chip Debugger (OCD) --
295
    ON_CHIP_DEBUGGER_EN          => ON_CHIP_DEBUGGER_EN,          -- implement on-chip debugger
296
    -- RISC-V CPU Extensions --
297
    CPU_EXTENSION_RISCV_A        => CPU_EXTENSION_RISCV_A,        -- implement atomic extension?
298 66 zero_gravi
    CPU_EXTENSION_RISCV_B        => CPU_EXTENSION_RISCV_B,        -- implement bit-manipulation extension?
299 63 zero_gravi
    CPU_EXTENSION_RISCV_C        => CPU_EXTENSION_RISCV_C,        -- implement compressed extension?
300
    CPU_EXTENSION_RISCV_E        => CPU_EXTENSION_RISCV_E,        -- implement embedded RF extension?
301
    CPU_EXTENSION_RISCV_M        => CPU_EXTENSION_RISCV_M,        -- implement muld/div extension?
302
    CPU_EXTENSION_RISCV_U        => CPU_EXTENSION_RISCV_U,        -- implement user mode extension?
303
    CPU_EXTENSION_RISCV_Zfinx    => CPU_EXTENSION_RISCV_Zfinx,    -- implement 32-bit floating-point extension (using INT reg!)
304
    CPU_EXTENSION_RISCV_Zicsr    => CPU_EXTENSION_RISCV_Zicsr,    -- implement CSR system?
305 66 zero_gravi
    CPU_EXTENSION_RISCV_Zicntr   => CPU_EXTENSION_RISCV_Zicntr,   -- implement base counters?
306
    CPU_EXTENSION_RISCV_Zihpm    => CPU_EXTENSION_RISCV_Zihpm,    -- implement hardware performance monitors?
307 63 zero_gravi
    CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
308 72 zero_gravi
    CPU_EXTENSION_RISCV_Zmmul    => CPU_EXTENSION_RISCV_Zmmul,    -- implement multiply-only M sub-extension?
309
    CPU_EXTENSION_RISCV_Zxcfu    => CPU_EXTENSION_RISCV_Zxcfu,    -- implement custom (instr.) functions unit?
310 63 zero_gravi
    -- Extension Options --
311
    FAST_MUL_EN                  => FAST_MUL_EN,        -- use DSPs for M extension's multiplier
312
    FAST_SHIFT_EN                => FAST_SHIFT_EN,      -- use barrel shifter for shift operations
313
    CPU_CNT_WIDTH                => CPU_CNT_WIDTH,      -- total width of CPU cycle and instret counters (0..64)
314
    -- Physical Memory Protection (PMP) --
315
    PMP_NUM_REGIONS              => PMP_NUM_REGIONS,    -- number of regions (0..64)
316
    PMP_MIN_GRANULARITY          => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
317
    -- Hardware Performance Monitors (HPM) --
318
    HPM_NUM_CNTS                 => HPM_NUM_CNTS,       -- number of implemented HPM counters (0..29)
319
    HPM_CNT_WIDTH                => HPM_CNT_WIDTH,      -- total size of HPM counters (0..64)
320
    -- Internal Instruction memory --
321
    MEM_INT_IMEM_EN              => MEM_INT_IMEM_EN,    -- implement processor-internal instruction memory
322
    MEM_INT_IMEM_SIZE            => MEM_INT_IMEM_SIZE,  -- size of processor-internal instruction memory in bytes
323
    -- Internal Data memory --
324
    MEM_INT_DMEM_EN              => MEM_INT_DMEM_EN,    -- implement processor-internal data memory
325
    MEM_INT_DMEM_SIZE            => MEM_INT_DMEM_SIZE,  -- size of processor-internal data memory in bytes
326
    -- Internal Cache memory --
327
    ICACHE_EN                    => ICACHE_EN,          -- implement instruction cache
328
    ICACHE_NUM_BLOCKS            => ICACHE_NUM_BLOCKS,  -- i-cache: number of blocks (min 1), has to be a power of 2
329
    ICACHE_BLOCK_SIZE            => ICACHE_BLOCK_SIZE,  -- i-cache: block size in bytes (min 4), has to be a power of 2
330
    ICACHE_ASSOCIATIVITY         => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
331
    -- External memory interface --
332
    MEM_EXT_EN                   => true,               -- implement external memory bus interface?
333
    MEM_EXT_TIMEOUT              => 0,                  -- cycles after a pending bus access auto-terminates (0 = disabled)
334
    MEM_EXT_PIPE_MODE            => false,              -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
335
    MEM_EXT_BIG_ENDIAN           => false,              -- byte order: true=big-endian, false=little-endian
336
    MEM_EXT_ASYNC_RX             => false,              -- use register buffer for RX data when false
337
    -- External Interrupts Controller (XIRQ) --
338
    XIRQ_NUM_CH                  => XIRQ_NUM_CH, -- number of external IRQ channels (0..32)
339
    XIRQ_TRIGGER_TYPE            => XIRQ_TRIGGER_TYPE_INT, -- trigger type: 0=level, 1=edge
340
    XIRQ_TRIGGER_POLARITY        => XIRQ_TRIGGER_POLARITY_INT, -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
341
    -- Processor peripherals --
342
    IO_GPIO_EN                   => IO_GPIO_EN,         -- implement general purpose input/output port unit (GPIO)?
343
    IO_MTIME_EN                  => IO_MTIME_EN,        -- implement machine system timer (MTIME)?
344
    IO_UART0_EN                  => IO_UART0_EN,        -- implement primary universal asynchronous receiver/transmitter (UART0)?
345 65 zero_gravi
    IO_UART0_RX_FIFO             => IO_UART0_RX_FIFO,   -- RX fifo depth, has to be a power of two, min 1
346
    IO_UART0_TX_FIFO             => IO_UART0_TX_FIFO,   -- TX fifo depth, has to be a power of two, min 1
347 63 zero_gravi
    IO_UART1_EN                  => IO_UART1_EN,        -- implement secondary universal asynchronous receiver/transmitter (UART1)?
348 65 zero_gravi
    IO_UART1_RX_FIFO             => IO_UART1_RX_FIFO,   -- RX fifo depth, has to be a power of two, min 1
349
    IO_UART1_TX_FIFO             => IO_UART1_TX_FIFO,   -- TX fifo depth, has to be a power of two, min 1
350 63 zero_gravi
    IO_SPI_EN                    => IO_SPI_EN,          -- implement serial peripheral interface (SPI)?
351
    IO_TWI_EN                    => IO_TWI_EN,          -- implement two-wire interface (TWI)?
352
    IO_PWM_NUM_CH                => IO_PWM_NUM_CH,      -- number of PWM channels to implement (0..60); 0 = disabled
353
    IO_WDT_EN                    => IO_WDT_EN,          -- implement watch dog timer (WDT)?
354
    IO_TRNG_EN                   => IO_TRNG_EN,         -- implement true random number generator (TRNG)?
355
    IO_CFS_EN                    => IO_CFS_EN,          -- implement custom functions subsystem (CFS)?
356
    IO_CFS_CONFIG                => IO_CFS_CONFIG_INT,  -- custom CFS configuration generic
357
    IO_CFS_IN_SIZE               => IO_CFS_IN_SIZE,     -- size of CFS input conduit in bits
358
    IO_CFS_OUT_SIZE              => IO_CFS_OUT_SIZE,    -- size of CFS output conduit in bits
359 65 zero_gravi
    IO_NEOLED_EN                 => IO_NEOLED_EN,       -- implement NeoPixel-compatible smart LED interface (NEOLED)?
360 67 zero_gravi
    IO_NEOLED_TX_FIFO            => IO_NEOLED_TX_FIFO,  -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
361 70 zero_gravi
    IO_GPTMR_EN                  => IO_GPTMR_EN,        -- implement general purpose timer (GPTMR)?
362
    IO_XIP_EN                    => IO_XIP_EN           -- implement execute in place module (XIP)?
363 63 zero_gravi
  )
364
  port map (
365
    -- Global control --
366
    clk_i       => clk_i_int,       -- global clock, rising edge
367
    rstn_i      => rstn_i_int,      -- global reset, low-active, async
368
    -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
369
    jtag_trst_i => jtag_trst_i_int, -- low-active TAP reset (optional)
370
    jtag_tck_i  => jtag_tck_i_int,  -- serial clock
371
    jtag_tdi_i  => jtag_tdi_i_int,  -- serial data input
372
    jtag_tdo_o  => jtag_tdo_o_int,  -- serial data output
373
    jtag_tms_i  => jtag_tms_i_int,  -- mode select
374
    -- Wishbone bus interface (available if MEM_EXT_EN = true) --
375
    wb_tag_o    => wb_core.tag,     -- tag
376
    wb_adr_o    => wb_core.adr,     -- address
377
    wb_dat_i    => wb_core.di,      -- read data
378
    wb_dat_o    => wb_core.do,      -- write data
379
    wb_we_o     => wb_core.we,      -- read/write
380
    wb_sel_o    => wb_core.sel,     -- byte enable
381
    wb_stb_o    => wb_core.stb,     -- strobe
382
    wb_cyc_o    => wb_core.cyc,     -- valid cycle
383
    wb_lock_o   => wb_core.lock,    -- exclusive access request
384
    wb_ack_i    => wb_core.ack,     -- transfer acknowledge
385
    wb_err_i    => wb_core.err,     -- transfer error
386
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
387
    fence_o     => open,            -- indicates an executed FENCE operation
388
    fencei_o    => open,            -- indicates an executed FENCEI operation
389 70 zero_gravi
    -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
390
    xip_csn_o   => xip_csn_o_int,   -- chip-select, low-active
391
    xip_clk_o   => xip_clk_o_int,   -- serial clock
392
    xip_sdi_i   => xip_sdi_i_int,   -- device data input
393
    xip_sdo_o   => xip_sdo_o_int,   -- controller data output
394 63 zero_gravi
    -- GPIO (available if IO_GPIO_EN = true) --
395
    gpio_o      => gpio_o_int,      -- parallel output
396
    gpio_i      => gpio_i_int,      -- parallel input
397
    -- primary UART0 (available if IO_UART0_EN = true) --
398
    uart0_txd_o => uart0_txd_o_int, -- UART0 send data
399
    uart0_rxd_i => uart0_rxd_i_int, -- UART0 receive data
400
    uart0_rts_o => uart0_rts_o_int, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
401
    uart0_cts_i => uart0_cts_i_int, -- hw flow control: UART0.TX allowed to transmit, low-active, optional
402
    -- secondary UART1 (available if IO_UART1_EN = true) --
403
    uart1_txd_o => uart1_txd_o_int, -- UART1 send data
404
    uart1_rxd_i => uart1_rxd_i_int, -- UART1 receive data
405
    uart1_rts_o => uart1_rts_o_int, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
406
    uart1_cts_i => uart1_cts_i_int, -- hw flow control: UART1.TX allowed to transmit, low-active, optional
407
    -- SPI (available if IO_SPI_EN = true) --
408
    spi_sck_o   => spi_sck_o_int,   -- SPI serial clock
409
    spi_sdo_o   => spi_sdo_o_int,   -- controller data out, peripheral data in
410
    spi_sdi_i   => spi_sdi_i_int,   -- controller data in, peripheral data out
411
    spi_csn_o   => spi_csn_o_int,   -- SPI CS
412
    -- TWI (available if IO_TWI_EN = true) --
413
    twi_sda_io  => twi_sda_io,      -- twi serial data line
414
    twi_scl_io  => twi_scl_io,      -- twi serial clock line
415
    -- PWM available if IO_PWM_NUM_CH > 0) --
416
    pwm_o       => pwm_o_int,       -- pwm channels
417
    -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
418
    cfs_in_i    => cfs_in_i_int,    -- custom inputs
419
    cfs_out_o   => cfs_out_o_int,   -- custom outputs
420
    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
421
    neoled_o    => neoled_o_int,    -- async serial data line
422
    -- System time --
423
    mtime_i     => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false)
424
    mtime_o     => open,            -- current system time from int. MTIME (if IO_MTIME_EN = true)
425
    -- External platform interrupts (available if XIRQ_NUM_CH > 0) --
426
    xirq_i      => xirq_i_int,      -- IRQ channels
427
    -- CPU Interrupts --
428
    mtime_irq_i => '0',             -- machine timer interrupt, available if IO_MTIME_EN = false
429
    msw_irq_i   => msw_irq_i_int,   -- machine software interrupt
430
    mext_irq_i  => mext_irq_i_int   -- machine external interrupt
431
  );
432
 
433
  -- type conversion --
434 70 zero_gravi
  xip_csn_o       <= std_logic(xip_csn_o_int);
435
  xip_clk_o       <= std_logic(xip_clk_o_int);
436
  xip_sdi_i_int   <= std_ulogic(xip_sdi_i);
437
  xip_sdo_o       <= std_logic(xip_sdo_o_int);
438
 
439 63 zero_gravi
  gpio_o          <= std_logic_vector(gpio_o_int);
440
  gpio_i_int      <= std_ulogic_vector(gpio_i);
441
 
442
  jtag_trst_i_int <= std_ulogic(jtag_trst_i);
443
  jtag_tck_i_int  <= std_ulogic(jtag_tck_i);
444
  jtag_tdi_i_int  <= std_ulogic(jtag_tdi_i);
445
  jtag_tdo_o      <= std_logic(jtag_tdo_o_int);
446
  jtag_tms_i_int  <= std_ulogic(jtag_tms_i);
447
 
448
  uart0_txd_o     <= std_logic(uart0_txd_o_int);
449
  uart0_rxd_i_int <= std_ulogic(uart0_rxd_i);
450 65 zero_gravi
  uart0_rts_o     <= std_logic(uart0_rts_o_int);
451
  uart0_cts_i_int <= std_ulogic(uart0_cts_i);
452
  uart1_txd_o     <= std_logic(uart1_txd_o_int);
453
  uart1_rxd_i_int <= std_ulogic(uart1_rxd_i);
454
  uart1_rts_o     <= std_logic(uart1_rts_o_int);
455
  uart1_cts_i_int <= std_ulogic(uart1_cts_i);
456 63 zero_gravi
 
457
  spi_sck_o       <= std_logic(spi_sck_o_int);
458
  spi_sdo_o       <= std_logic(spi_sdo_o_int);
459
  spi_sdi_i_int   <= std_ulogic(spi_sdi_i);
460
  spi_csn_o       <= std_logic_vector(spi_csn_o_int);
461
 
462
  pwm_o           <= std_logic_vector(pwm_o_int);
463
 
464
  cfs_in_i_int    <= std_ulogic_vector(cfs_in_i);
465
  cfs_out_o       <= std_logic_vector(cfs_out_o_int);
466
 
467
  neoled_o        <= std_logic(neoled_o_int);
468
 
469 64 zero_gravi
  xirq_i_int      <= std_ulogic_vector(xirq_i);
470
 
471
  msw_irq_i_int   <= std_ulogic(msw_irq_i);
472 63 zero_gravi
  mext_irq_i_int  <= std_ulogic(mext_irq_i);
473
 
474
 
475
  -- Wishbone to AXI4-Lite Bridge -----------------------------------------------------------
476
  -- -------------------------------------------------------------------------------------------
477
 
478
  -- access arbiter --
479
  axi_access_arbiter: process(rstn_i_int, clk_i_int)
480
  begin
481
    if (rstn_i_int = '0') then
482
      ctrl.radr_received <= '0';
483
      ctrl.wadr_received <= '0';
484
      ctrl.wdat_received <= '0';
485
    elsif rising_edge(clk_i_int) then
486
      if (wb_core.cyc = '0') then -- idle
487
        ctrl.radr_received <= '0';
488
        ctrl.wadr_received <= '0';
489
        ctrl.wdat_received <= '0';
490
      else -- busy
491
        -- "read address received" flag --
492
        if (wb_core.we = '0') then -- pending READ
493
          if (m_axi_arready = '1') then -- read address received by interconnect?
494
            ctrl.radr_received <= '1';
495
          end if;
496
        end if;
497
        -- "write address received" flag --
498
        if (wb_core.we = '1') then -- pending WRITE
499
          if (m_axi_awready = '1') then -- write address received by interconnect?
500
            ctrl.wadr_received <= '1';
501
          end if;
502
        end if;
503
        -- "write data received" flag --
504
        if (wb_core.we = '1') then -- pending WRITE
505
          if (m_axi_wready = '1') then -- write data received by interconnect?
506
            ctrl.wdat_received <= '1';
507
          end if;
508
        end if;
509
      end if;
510
    end if;
511
  end process axi_access_arbiter;
512
 
513
 
514
  -- AXI4-Lite Global Signals --
515
  clk_i_int     <= std_ulogic(m_axi_aclk);
516
  rstn_i_int    <= std_ulogic(m_axi_aresetn);
517
 
518
 
519
  -- AXI4-Lite Read Address Channel --
520
  m_axi_araddr  <= std_logic_vector(wb_core.adr);
521
  m_axi_arvalid <= std_logic((wb_core.cyc and (not wb_core.we)) and (not ctrl.radr_received));
522
--m_axi_arprot  <= "000"; -- recommended by Xilinx
523
  m_axi_arprot(0) <= wb_core.tag(0); -- 0:unprivileged access, 1:privileged access
524
  m_axi_arprot(1) <= wb_core.tag(1); -- 0:secure access, 1:non-secure access
525
  m_axi_arprot(2) <= wb_core.tag(2); -- 0:data access, 1:instruction access
526
 
527
  -- AXI4-Lite Read Data Channel --
528
  m_axi_rready  <= std_logic(wb_core.cyc and (not wb_core.we));
529
  wb_core.di    <= std_ulogic_vector(m_axi_rdata);
530
  ack_read      <= std_ulogic(m_axi_rvalid);
531
  err_read      <= '0' when (m_axi_rresp = "00") else '1'; -- read response = ok? check this signal only when m_axi_rvalid = '1'
532
 
533
 
534
  -- AXI4-Lite Write Address Channel --
535
  m_axi_awaddr  <= std_logic_vector(wb_core.adr);
536
  m_axi_awvalid <= std_logic((wb_core.cyc and wb_core.we) and (not ctrl.wadr_received));
537
--m_axi_awprot  <= "000"; -- recommended by Xilinx
538
  m_axi_awprot(0) <= wb_core.tag(0); -- 0:unprivileged access, 1:privileged access
539
  m_axi_awprot(1) <= wb_core.tag(1); -- 0:secure access, 1:non-secure access
540
  m_axi_awprot(2) <= wb_core.tag(2); -- 0:data access, 1:instruction access
541
 
542
  -- AXI4-Lite Write Data Channel --
543
  m_axi_wdata   <= std_logic_vector(wb_core.do);
544
  m_axi_wvalid  <= std_logic((wb_core.cyc and wb_core.we) and (not ctrl.wdat_received));
545
  m_axi_wstrb   <= std_logic_vector(wb_core.sel); -- byte-enable
546
 
547
  -- AXI4-Lite Write Response Channel --
548
  m_axi_bready  <= std_logic(wb_core.cyc and wb_core.we);
549
  ack_write     <= std_ulogic(m_axi_bvalid);
550
  err_write     <= '0' when (m_axi_bresp = "00") else '1'; -- write response = ok? check this signal only when m_axi_bvalid = '1'
551
 
552
 
553
  -- Wishbone transfer termination --
554
  wb_core.ack   <= ack_read or ack_write;
555
  wb_core.err   <= (ack_read and err_read) or (ack_write and err_write) or wb_core.lock;
556
 
557
 
558
end architecture;

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