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-- #################################################################################################

-- # << NEORV32 - Test Setup using the UART-Bootloader to upload and run executables >>            #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #

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-- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32                           #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library neorv32;

use neorv32.neorv32_package.all;

entity neorv32_test_setup_bootloader is

  generic (

    -- adapt these for your setup --

    CLOCK_FREQUENCY   : natural := 100000000; -- clock frequency of clk_i in Hz

    MEM_INT_IMEM_SIZE : natural := 16*1024;   -- size of processor-internal instruction memory in bytes

    MEM_INT_DMEM_SIZE : natural := 8*1024     -- size of processor-internal data memory in bytes

  );

  port (

    -- Global control --

    clk_i       : in  std_ulogic; -- global clock, rising edge

    rstn_i      : in  std_ulogic; -- global reset, low-active, async

    -- GPIO --

    gpio_o      : out std_ulogic_vector(7 downto 0); -- parallel output

    -- UART0 --

    uart0_txd_o : out std_ulogic; -- UART0 send data

    uart0_rxd_i : in  std_ulogic  -- UART0 receive data

  );

end entity;

architecture neorv32_test_setup_bootloader_rtl of neorv32_test_setup_bootloader is

  signal con_gpio_o : std_ulogic_vector(63 downto 0);

begin

  -- The Core Of The Problem ----------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  neorv32_top_inst: neorv32_top

  generic map (

    -- General --

    CLOCK_FREQUENCY              => CLOCK_FREQUENCY,   -- clock frequency of clk_i in Hz

    INT_BOOTLOADER_EN            => true,              -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM

    -- RISC-V CPU Extensions --

    CPU_EXTENSION_RISCV_C        => true,              -- implement compressed extension?

    CPU_EXTENSION_RISCV_M        => true,              -- implement mul/div extension?

    CPU_EXTENSION_RISCV_Zicsr    => true,              -- implement CSR system?

    -- Internal Instruction memory --

    MEM_INT_IMEM_EN              => true,              -- implement processor-internal instruction memory

    MEM_INT_IMEM_SIZE            => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes

    -- Internal Data memory --

    MEM_INT_DMEM_EN              => true,              -- implement processor-internal data memory

    MEM_INT_DMEM_SIZE            => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes

    -- Processor peripherals --

    IO_GPIO_EN                   => true,              -- implement general purpose input/output port unit (GPIO)?

    IO_MTIME_EN                  => true,              -- implement machine system timer (MTIME)?

    IO_UART0_EN                  => true               -- implement primary universal asynchronous receiver/transmitter (UART0)?

  )

  port map (

    -- Global control --

    clk_i       => clk_i,       -- global clock, rising edge

    rstn_i      => rstn_i,      -- global reset, low-active, async

    -- GPIO (available if IO_GPIO_EN = true) --

    gpio_o      => con_gpio_o,  -- parallel output

    -- primary UART0 (available if IO_UART0_EN = true) --

    uart0_txd_o => uart0_txd_o, -- UART0 send data

    uart0_rxd_i => uart0_rxd_i  -- UART0 receive data

  );

  -- GPIO output --

  gpio_o <= con_gpio_o(7 downto 0);

end architecture;