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## Simulation Source Folder
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### [`ghdl`](https://github.com/stnolting/neorv32/tree/master/sim/ghdl)
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This folder contains a script for simulating the processor using GHDL.
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### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)
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This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.
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### [`vivado`](https://github.com/stnolting/neorv32/tree/master/sim/vivado)
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This folder provides an example waveform configuration (for Xilinx ISIM simulator) for the default testbench.
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### [`neorv32_tb.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.vhd)
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Default testbench for the NEORV32 Processor.
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