Back to project
URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/ ] [neorv32/ ] [trunk/ ] [sim/ ] [README.md ] - Blame information for rev 61
Go to most recent revision Details Compare with Previous View Log
Line No.
Rev
Author
Line
1
40 zero_gravi
## Simulation Source Folder
2
3
### [`ghdl`](https://github.com/stnolting/neorv32/tree/master/sim/ghdl)
4
5
This folder contains a script for simulating the processor using GHDL.
6
7
### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)
8
9
42 zero_gravi
This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.
10
40 zero_gravi
11
61 zero_gravi
### [`neorv32_tb.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.vhd)
12
40 zero_gravi
13
61 zero_gravi
VUnit testbench for the NEORV32 Processor.
14
40 zero_gravi
15
61 zero_gravi
### [`neorv32_tb.simple.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.simple.vhd)
16
40 zero_gravi
17
61 zero_gravi
Simple testbench for the NEORV32 Processor.
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
