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[/] [neorv32/] [trunk/] [sim/] [neorv32_tb.vhd] - Blame information for rev 14

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1 2 zero_gravi
-- #################################################################################################
2 3 zero_gravi
-- # << NEORV32 - Simple Testbench >>                                                              #
3 2 zero_gravi
-- # ********************************************************************************************* #
4 3 zero_gravi
-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o       #
5
-- # signals. The received chars are shown in the simulator console and also written to a file     #
6
-- # ("neorv32.testbench_uart.out").                                                               #
7
-- # Futhermore, this testbench provides a simple RAM connected to the external Wishbone bus.      #
8 11 zero_gravi
-- # The testbench configures the processor with all optional element enabled by default.          #
9 3 zero_gravi
-- # ********************************************************************************************* #
10 2 zero_gravi
-- # BSD 3-Clause License                                                                          #
11
-- #                                                                                               #
12
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
13
-- #                                                                                               #
14
-- # Redistribution and use in source and binary forms, with or without modification, are          #
15
-- # permitted provided that the following conditions are met:                                     #
16
-- #                                                                                               #
17
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
18
-- #    conditions and the following disclaimer.                                                   #
19
-- #                                                                                               #
20
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
21
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
22
-- #    provided with the distribution.                                                            #
23
-- #                                                                                               #
24
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
25
-- #    endorse or promote products derived from this software without specific prior written      #
26
-- #    permission.                                                                                #
27
-- #                                                                                               #
28
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
29
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
30
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
31
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
32
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
33
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
34
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
35
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
36
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
37
-- # ********************************************************************************************* #
38
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
39
-- #################################################################################################
40
 
41
library ieee;
42
use ieee.std_logic_1164.all;
43
use ieee.numeric_std.all;
44
use ieee.math_real.all;
45
 
46
library neorv32;
47
use neorv32.neorv32_package.all;
48
use std.textio.all;
49
 
50
entity neorv32_tb is
51
end neorv32_tb;
52
 
53
architecture neorv32_tb_rtl of neorv32_tb is
54
 
55
  -- User Configuration ---------------------------------------------------------------------
56
  -- -------------------------------------------------------------------------------------------
57
  constant t_clock_c          : time := 10 ns; -- main clock period
58
  constant f_clock_c          : real := 100000000.0; -- main clock in Hz
59
  constant f_clock_nat_c      : natural := 100000000; -- main clock in Hz
60
  constant baud_rate_c        : real := 19200.0; -- standard UART baudrate
61 3 zero_gravi
  constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address
62 2 zero_gravi
  constant wb_mem_size_c      : natural := 256; -- wishbone memory size in bytes
63
  -- -------------------------------------------------------------------------------------------
64
 
65 3 zero_gravi
  -- text.io --
66
  file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
67 2 zero_gravi
 
68
  -- internal configuration --
69
  constant baud_val_c : real    := f_clock_c / baud_rate_c;
70
  constant f_clk_c    : natural := natural(f_clock_c);
71
 
72
  -- generators --
73
  signal clk_gen, rst_gen : std_ulogic := '0';
74
 
75
  -- simulation uart receiver --
76
  signal uart_txd         : std_ulogic;
77
  signal uart_rx_sync     : std_ulogic_vector(04 downto 0) := (others => '1');
78
  signal uart_rx_busy     : std_ulogic := '0';
79
  signal uart_rx_sreg     : std_ulogic_vector(08 downto 0) := (others => '0');
80
  signal uart_rx_baud_cnt : real;
81
  signal uart_rx_bitcnt   : natural;
82
 
83
  -- gpio --
84
  signal gpio : std_ulogic_vector(15 downto 0);
85
 
86
  -- twi --
87
  signal twi_scl, twi_sda : std_logic;
88
 
89
  -- spi --
90
  signal spi_data : std_logic;
91
 
92
  -- Wishbone bus --
93
  type wishbone_t is record
94
    addr  : std_ulogic_vector(31 downto 0); -- address
95
    wdata : std_ulogic_vector(31 downto 0); -- master write data
96
    rdata : std_ulogic_vector(31 downto 0); -- master read data
97
    we    : std_ulogic; -- write enable
98
    sel   : std_ulogic_vector(03 downto 0); -- byte enable
99
    stb   : std_ulogic; -- strobe
100
    cyc   : std_ulogic; -- valid cycle
101
    ack   : std_ulogic; -- transfer acknowledge
102
    err   : std_ulogic; -- transfer error
103
  end record;
104
  signal wb_cpu : wishbone_t;
105
 
106
 
107 3 zero_gravi
  -- Wishbone memory, SimCom --
108 2 zero_gravi
  type wb_mem_file_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
109 3 zero_gravi
  signal wb_mem_file  : wb_mem_file_t := (others => (others => '0'));
110
  signal rb_en        : std_ulogic;
111
  signal r_data       : std_ulogic_vector(31 downto 0);
112
  signal wb_acc_en    : std_ulogic;
113
  signal wb_mem_rdata : std_ulogic_vector(31 downto 0);
114
  signal wb_mem_ack   : std_ulogic;
115 2 zero_gravi
 
116
begin
117
 
118
  -- Clock/Reset Generator ------------------------------------------------------------------
119
  -- -------------------------------------------------------------------------------------------
120
  clk_gen <= not clk_gen after (t_clock_c/2);
121
  rst_gen <= '0', '1' after 60*(t_clock_c/2);
122
 
123
 
124
  -- CPU Core -------------------------------------------------------------------------------
125
  -- -------------------------------------------------------------------------------------------
126
  neorv32_top_inst: neorv32_top
127
  generic map (
128
    -- General --
129 8 zero_gravi
    CLOCK_FREQUENCY              => f_clock_nat_c, -- clock frequency of clk_i in Hz
130
    BOOTLOADER_USE               => false,         -- implement processor-internal bootloader?
131
    CSR_COUNTERS_USE             => true,          -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
132 12 zero_gravi
    USER_CODE                    => x"19880704",   -- custom user code
133 2 zero_gravi
    -- RISC-V CPU Extensions --
134 8 zero_gravi
    CPU_EXTENSION_RISCV_C        => true,          -- implement compressed extension?
135
    CPU_EXTENSION_RISCV_E        => false,         -- implement embedded RF extension?
136
    CPU_EXTENSION_RISCV_M        => true,          -- implement muld/div extension?
137
    CPU_EXTENSION_RISCV_Zicsr    => true,          -- implement CSR system?
138
    CPU_EXTENSION_RISCV_Zifencei => true,          -- implement instruction stream sync.?
139 2 zero_gravi
    -- Memory configuration: Instruction memory --
140 8 zero_gravi
    MEM_ISPACE_BASE              => x"00000000",   -- base address of instruction memory space
141
    MEM_ISPACE_SIZE              => 16*1024,       -- total size of instruction memory space in byte
142
    MEM_INT_IMEM_USE             => true,          -- implement processor-internal instruction memory
143
    MEM_INT_IMEM_SIZE            => 16*1024,       -- size of processor-internal instruction memory in bytes
144
    MEM_INT_IMEM_ROM             => false,         -- implement processor-internal instruction memory as ROM
145 2 zero_gravi
    -- Memory configuration: Data memory --
146 8 zero_gravi
    MEM_DSPACE_BASE              => x"80000000",   -- base address of data memory space
147
    MEM_DSPACE_SIZE              => 8*1024,        -- total size of data memory space in byte
148
    MEM_INT_DMEM_USE             => true,          -- implement processor-internal data memory
149
    MEM_INT_DMEM_SIZE            => 8*1024,        -- size of processor-internal data memory in bytes
150 2 zero_gravi
    -- Memory configuration: External memory interface --
151 8 zero_gravi
    MEM_EXT_USE                  => true,          -- implement external memory bus interface?
152
    MEM_EXT_REG_STAGES           => 2,             -- number of interface register stages (0,1,2)
153
    MEM_EXT_TIMEOUT              => 15,            -- cycles after which a valid bus access will timeout
154 2 zero_gravi
    -- Processor peripherals --
155 8 zero_gravi
    IO_GPIO_USE                  => true,          -- implement general purpose input/output port unit (GPIO)?
156
    IO_MTIME_USE                 => true,          -- implement machine system timer (MTIME)?
157
    IO_UART_USE                  => true,          -- implement universal asynchronous receiver/transmitter (UART)?
158
    IO_SPI_USE                   => true,          -- implement serial peripheral interface (SPI)?
159
    IO_TWI_USE                   => true,          -- implement two-wire interface (TWI)?
160
    IO_PWM_USE                   => true,          -- implement pulse-width modulation unit (PWM)?
161
    IO_WDT_USE                   => true,          -- implement watch dog timer (WDT)?
162 11 zero_gravi
    IO_TRNG_USE                  => false,         -- CANNOT BE SIMULATED!
163 8 zero_gravi
    IO_DEVNULL_USE               => true           -- implement dummy device (DEVNULL)?
164 2 zero_gravi
  )
165
  port map (
166
    -- Global control --
167
    clk_i      => clk_gen,         -- global clock, rising edge
168
    rstn_i     => rst_gen,         -- global reset, low-active, async
169
    -- Wishbone bus interface --
170
    wb_adr_o   => wb_cpu.addr,     -- address
171
    wb_dat_i   => wb_cpu.rdata,    -- read data
172
    wb_dat_o   => wb_cpu.wdata,    -- write data
173
    wb_we_o    => wb_cpu.we,       -- read/write
174
    wb_sel_o   => wb_cpu.sel,      -- byte enable
175
    wb_stb_o   => wb_cpu.stb,      -- strobe
176
    wb_cyc_o   => wb_cpu.cyc,      -- valid cycle
177
    wb_ack_i   => wb_cpu.ack,      -- transfer acknowledge
178
    wb_err_i   => wb_cpu.err,      -- transfer error
179 12 zero_gravi
    -- Advanced memory control signals --
180
    fence_o    => open,            -- indicates an executed FENCE operation
181
    fencei_o   => open,            -- indicates an executed FENCEI operation
182 2 zero_gravi
    -- GPIO --
183
    gpio_o     => gpio,            -- parallel output
184
    gpio_i     => gpio,            -- parallel input
185
    -- UART --
186
    uart_txd_o => uart_txd,        -- UART send data
187
    uart_rxd_i => uart_txd,        -- UART receive data
188
    -- SPI --
189 6 zero_gravi
    spi_sck_o  => open,            -- SPI serial clock
190
    spi_sdo_o  => spi_data,        -- controller data out, peripheral data in
191
    spi_sdi_i  => spi_data,        -- controller data in, peripheral data out
192 2 zero_gravi
    spi_csn_o  => open,            -- SPI CS
193
    -- TWI --
194
    twi_sda_io => twi_sda,         -- twi serial data line
195
    twi_scl_io => twi_scl,         -- twi serial clock line
196
    -- PWM --
197
    pwm_o      => open,            -- pwm channels
198
    -- Interrupts --
199 14 zero_gravi
    mext_irq_i => '0'              -- machine external interrupt
200 2 zero_gravi
  );
201
 
202 3 zero_gravi
  -- TWI termination --
203 2 zero_gravi
  twi_scl <= 'H';
204
  twi_sda <= 'H';
205
 
206 3 zero_gravi
  -- Wishbone read-back --
207
  wb_cpu.rdata <= wb_mem_rdata;
208
  wb_cpu.ack   <= wb_mem_ack;
209
  wb_cpu.err   <= '0';
210 2 zero_gravi
 
211 3 zero_gravi
 
212 2 zero_gravi
  -- Console UART Receiver ------------------------------------------------------------------
213
  -- -------------------------------------------------------------------------------------------
214
  uart_rx_console: process(clk_gen)
215 3 zero_gravi
    variable i : integer;
216
    variable l : line;
217 2 zero_gravi
  begin
218
    -- "UART" --
219
    if rising_edge(clk_gen) then
220
      -- synchronizer --
221
      uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
222
      -- arbiter --
223
      if (uart_rx_busy = '0') then -- idle
224
        uart_rx_busy     <= '0';
225
        uart_rx_baud_cnt <= round(0.5 * baud_val_c);
226
        uart_rx_bitcnt   <= 9;
227
        if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
228
          uart_rx_busy <= '1';
229
        end if;
230
      else
231
        if (uart_rx_baud_cnt = 0.0) then
232
          if (uart_rx_bitcnt = 1) then
233
            uart_rx_baud_cnt <= round(0.5 * baud_val_c);
234
          else
235
            uart_rx_baud_cnt <= round(baud_val_c);
236
          end if;
237
          if (uart_rx_bitcnt = 0) then
238
            uart_rx_busy <= '0'; -- done
239
            i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
240
 
241 3 zero_gravi
            if (i < 32) or (i > 32+95) then -- printable char?
242
              report "SIM_UART TX: (" & integer'image(i) & ")"; -- print code
243 2 zero_gravi
            else
244 3 zero_gravi
              report "SIM_UART TX: " & character'val(i); -- print ASCII
245 2 zero_gravi
            end if;
246
 
247
            if (i = 10) then -- Linux line break
248 3 zero_gravi
              writeline(file_uart_tx_out, l);
249 2 zero_gravi
            elsif (i /= 13) then -- Remove additional carriage return
250 3 zero_gravi
              write(l, character'val(i));
251 2 zero_gravi
            end if;
252
          else
253
            uart_rx_sreg   <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
254
            uart_rx_bitcnt <= uart_rx_bitcnt - 1;
255
          end if;
256
        else
257
          uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
258
        end if;
259
      end if;
260
    end if;
261
  end process uart_rx_console;
262
 
263
 
264
  -- Wishbone Memory ------------------------------------------------------------------------
265
  -- -------------------------------------------------------------------------------------------
266
    wb_mem_file_access: process(clk_gen)
267
    begin
268
      if rising_edge(clk_gen) then
269
        rb_en <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en and (not wb_cpu.we); -- read-back control
270 3 zero_gravi
        wb_mem_ack <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en; -- wishbone acknowledge
271 2 zero_gravi
        if ((wb_cpu.cyc and wb_cpu.stb and wb_acc_en and wb_cpu.we) = '1') then -- valid write access
272
          for i in 0 to 3 loop
273
            if (wb_cpu.sel(i) = '1') then
274
              wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8);
275
            end if;
276
          end loop; -- i
277
        end if;
278
        r_data <= wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
279
      end if;
280
    end process wb_mem_file_access;
281
 
282
  -- wb mem access --
283
  wb_acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
284
 
285
  -- output gate --
286 3 zero_gravi
  wb_mem_rdata <= r_data when (rb_en = '1') else (others=> '0');
287 2 zero_gravi
 
288 3 zero_gravi
 
289 2 zero_gravi
end neorv32_tb_rtl;

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