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zero_gravi |
-- #################################################################################################
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zero_gravi |
-- # << NEORV32 - Simple Testbench >> #
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2 |
zero_gravi |
-- # ********************************************************************************************* #
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3 |
zero_gravi |
-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o #
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5 |
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-- # signals. The received chars are shown in the simulator console and also written to a file #
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-- # ("neorv32.testbench_uart.out"). #
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-- # Futhermore, this testbench provides a simple RAM connected to the external Wishbone bus. #
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11 |
zero_gravi |
-- # The testbench configures the processor with all optional element enabled by default. #
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9 |
3 |
zero_gravi |
-- # ********************************************************************************************* #
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2 |
zero_gravi |
-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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39 |
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-- #################################################################################################
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library ieee;
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42 |
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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44 |
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use ieee.math_real.all;
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45 |
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46 |
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library neorv32;
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47 |
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use neorv32.neorv32_package.all;
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48 |
30 |
zero_gravi |
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
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49 |
2 |
zero_gravi |
use std.textio.all;
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50 |
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51 |
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entity neorv32_tb is
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52 |
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end neorv32_tb;
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53 |
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54 |
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architecture neorv32_tb_rtl of neorv32_tb is
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55 |
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56 |
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-- User Configuration ---------------------------------------------------------------------
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57 |
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-- -------------------------------------------------------------------------------------------
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58 |
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constant t_clock_c : time := 10 ns; -- main clock period
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59 |
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constant f_clock_c : real := 100000000.0; -- main clock in Hz
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60 |
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constant f_clock_nat_c : natural := 100000000; -- main clock in Hz
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61 |
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constant baud_rate_c : real := 19200.0; -- standard UART baudrate
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62 |
30 |
zero_gravi |
--
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63 |
3 |
zero_gravi |
constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address
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64 |
2 |
zero_gravi |
constant wb_mem_size_c : natural := 256; -- wishbone memory size in bytes
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65 |
23 |
zero_gravi |
constant wb_mem_latency_c : natural := 8; -- latency in clock cycles (min 1)
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66 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
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67 |
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3 |
zero_gravi |
-- text.io --
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
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2 |
zero_gravi |
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71 |
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-- internal configuration --
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72 |
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constant baud_val_c : real := f_clock_c / baud_rate_c;
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73 |
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constant f_clk_c : natural := natural(f_clock_c);
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74 |
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-- generators --
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76 |
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signal clk_gen, rst_gen : std_ulogic := '0';
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77 |
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-- simulation uart receiver --
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79 |
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signal uart_txd : std_ulogic;
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80 |
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signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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81 |
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signal uart_rx_busy : std_ulogic := '0';
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82 |
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signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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83 |
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signal uart_rx_baud_cnt : real;
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84 |
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signal uart_rx_bitcnt : natural;
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85 |
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-- gpio --
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87 |
22 |
zero_gravi |
signal gpio : std_ulogic_vector(31 downto 0);
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2 |
zero_gravi |
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89 |
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-- twi --
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signal twi_scl, twi_sda : std_logic;
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-- spi --
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93 |
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signal spi_data : std_logic;
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94 |
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95 |
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-- Wishbone bus --
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96 |
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type wishbone_t is record
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addr : std_ulogic_vector(31 downto 0); -- address
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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rdata : std_ulogic_vector(31 downto 0); -- master read data
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we : std_ulogic; -- write enable
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sel : std_ulogic_vector(03 downto 0); -- byte enable
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stb : std_ulogic; -- strobe
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cyc : std_ulogic; -- valid cycle
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ack : std_ulogic; -- transfer acknowledge
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105 |
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err : std_ulogic; -- transfer error
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end record;
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107 |
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signal wb_cpu : wishbone_t;
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23 |
zero_gravi |
-- Wishbone memory --
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type wb_mem_ram_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type wb_mem_read_latency_t is array (0 to wb_mem_latency_c-1) of std_ulogic_vector(31 downto 0);
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112 |
30 |
zero_gravi |
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-- init function --
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-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
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impure function init_wbmem(init : application_init_image_t) return wb_mem_ram_t is
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variable mem_v : wb_mem_ram_t;
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begin
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mem_v := (others => (others => '0'));
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for i in 0 to init'length-1 loop -- init only in range of source data array
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120 |
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mem_v(i) := init(i);
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121 |
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end loop; -- i
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return mem_v;
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end function init_wbmem;
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124 |
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-- ---------------------------------------------- --
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126 |
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-- How to simulate a boot from an external memory --
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127 |
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-- ---------------------------------------------- --
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128 |
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-- The simulated Wishbone memory can be initialized with the compiled application init.
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129 |
31 |
zero_gravi |
-- 1. Uncomment the init_wbmen function below; this will initialize the simulated wishbone memory with the neorv32_application_image.vhd image
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130 |
30 |
zero_gravi |
-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB)
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131 |
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-- 3. Disable the processor-internal IMEM in the processor instantiation below (MEM_INT_IMEM_USE => false)
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132 |
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-- 4. Set the Wishbone memory base address wb_mem_base_addr_c (above) to zero (constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000";)
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133 |
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-- 5. Simulate!
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134 |
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135 |
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signal wb_ram : wb_mem_ram_t;-- := init_wbmem(application_init_image); -- uncomment if you want to init the WB ram with app image
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136 |
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|
137 |
23 |
zero_gravi |
type wb_mem_t is record
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138 |
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rdata : wb_mem_read_latency_t;
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139 |
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acc_en : std_ulogic;
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140 |
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ack : std_ulogic_vector(wb_mem_latency_c-1 downto 0);
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141 |
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rb_en : std_ulogic_vector(wb_mem_latency_c-1 downto 0);
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142 |
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|
end record;
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143 |
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signal wb_mem : wb_mem_t;
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144 |
2 |
zero_gravi |
|
145 |
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begin
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146 |
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|
147 |
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-- Clock/Reset Generator ------------------------------------------------------------------
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148 |
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-- -------------------------------------------------------------------------------------------
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149 |
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clk_gen <= not clk_gen after (t_clock_c/2);
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150 |
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rst_gen <= '0', '1' after 60*(t_clock_c/2);
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151 |
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152 |
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153 |
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-- CPU Core -------------------------------------------------------------------------------
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154 |
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-- -------------------------------------------------------------------------------------------
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155 |
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neorv32_top_inst: neorv32_top
|
156 |
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generic map (
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157 |
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-- General --
|
158 |
8 |
zero_gravi |
CLOCK_FREQUENCY => f_clock_nat_c, -- clock frequency of clk_i in Hz
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159 |
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BOOTLOADER_USE => false, -- implement processor-internal bootloader?
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160 |
12 |
zero_gravi |
USER_CODE => x"19880704", -- custom user code
|
161 |
2 |
zero_gravi |
-- RISC-V CPU Extensions --
|
162 |
8 |
zero_gravi |
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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163 |
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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164 |
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CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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165 |
15 |
zero_gravi |
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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166 |
8 |
zero_gravi |
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
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167 |
|
|
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
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168 |
19 |
zero_gravi |
-- Extension Options --
|
169 |
|
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FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
|
170 |
34 |
zero_gravi |
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
|
171 |
15 |
zero_gravi |
-- Physical Memory Protection (PMP) --
|
172 |
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|
PMP_USE => true, -- implement PMP?
|
173 |
|
|
PMP_NUM_REGIONS => 4, -- number of regions (max 16)
|
174 |
16 |
zero_gravi |
PMP_GRANULARITY => 14, -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
175 |
23 |
zero_gravi |
-- Internal Instruction memory --
|
176 |
8 |
zero_gravi |
MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory
|
177 |
|
|
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes
|
178 |
|
|
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
|
179 |
23 |
zero_gravi |
-- Internal Data memory --
|
180 |
8 |
zero_gravi |
MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
|
181 |
|
|
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
|
182 |
23 |
zero_gravi |
-- External memory interface --
|
183 |
8 |
zero_gravi |
MEM_EXT_USE => true, -- implement external memory bus interface?
|
184 |
|
|
MEM_EXT_REG_STAGES => 2, -- number of interface register stages (0,1,2)
|
185 |
2 |
zero_gravi |
-- Processor peripherals --
|
186 |
8 |
zero_gravi |
IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
|
187 |
|
|
IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
|
188 |
|
|
IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
|
189 |
|
|
IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
|
190 |
|
|
IO_TWI_USE => true, -- implement two-wire interface (TWI)?
|
191 |
|
|
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
|
192 |
|
|
IO_WDT_USE => true, -- implement watch dog timer (WDT)?
|
193 |
23 |
zero_gravi |
IO_TRNG_USE => false, -- DEFAULT TRNG CONFIG CANNOT BE SIMULATED!
|
194 |
34 |
zero_gravi |
IO_CFU0_USE => true, -- implement custom functions unit 0 (CFU0)?
|
195 |
|
|
IO_CFU1_USE => true -- implement custom functions unit 1 (CFU1)?
|
196 |
2 |
zero_gravi |
)
|
197 |
|
|
port map (
|
198 |
|
|
-- Global control --
|
199 |
34 |
zero_gravi |
clk_i => clk_gen, -- global clock, rising edge
|
200 |
|
|
rstn_i => rst_gen, -- global reset, low-active, async
|
201 |
2 |
zero_gravi |
-- Wishbone bus interface --
|
202 |
34 |
zero_gravi |
wb_adr_o => wb_cpu.addr, -- address
|
203 |
|
|
wb_dat_i => wb_cpu.rdata, -- read data
|
204 |
|
|
wb_dat_o => wb_cpu.wdata, -- write data
|
205 |
|
|
wb_we_o => wb_cpu.we, -- read/write
|
206 |
|
|
wb_sel_o => wb_cpu.sel, -- byte enable
|
207 |
|
|
wb_stb_o => wb_cpu.stb, -- strobe
|
208 |
|
|
wb_cyc_o => wb_cpu.cyc, -- valid cycle
|
209 |
|
|
wb_ack_i => wb_cpu.ack, -- transfer acknowledge
|
210 |
|
|
wb_err_i => wb_cpu.err, -- transfer error
|
211 |
12 |
zero_gravi |
-- Advanced memory control signals --
|
212 |
34 |
zero_gravi |
fence_o => open, -- indicates an executed FENCE operation
|
213 |
|
|
fencei_o => open, -- indicates an executed FENCEI operation
|
214 |
2 |
zero_gravi |
-- GPIO --
|
215 |
34 |
zero_gravi |
gpio_o => gpio, -- parallel output
|
216 |
|
|
gpio_i => gpio, -- parallel input
|
217 |
2 |
zero_gravi |
-- UART --
|
218 |
34 |
zero_gravi |
uart_txd_o => uart_txd, -- UART send data
|
219 |
|
|
uart_rxd_i => uart_txd, -- UART receive data
|
220 |
2 |
zero_gravi |
-- SPI --
|
221 |
34 |
zero_gravi |
spi_sck_o => open, -- SPI serial clock
|
222 |
|
|
spi_sdo_o => spi_data, -- controller data out, peripheral data in
|
223 |
|
|
spi_sdi_i => spi_data, -- controller data in, peripheral data out
|
224 |
|
|
spi_csn_o => open, -- SPI CS
|
225 |
2 |
zero_gravi |
-- TWI --
|
226 |
34 |
zero_gravi |
twi_sda_io => twi_sda, -- twi serial data line
|
227 |
|
|
twi_scl_io => twi_scl, -- twi serial clock line
|
228 |
2 |
zero_gravi |
-- PWM --
|
229 |
34 |
zero_gravi |
pwm_o => open, -- pwm channels
|
230 |
2 |
zero_gravi |
-- Interrupts --
|
231 |
34 |
zero_gravi |
mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_USE = false
|
232 |
|
|
msw_irq_i => '0', -- machine software interrupt
|
233 |
|
|
mext_irq_i => '0' -- machine external interrupt
|
234 |
2 |
zero_gravi |
);
|
235 |
|
|
|
236 |
3 |
zero_gravi |
-- TWI termination --
|
237 |
2 |
zero_gravi |
twi_scl <= 'H';
|
238 |
|
|
twi_sda <= 'H';
|
239 |
|
|
|
240 |
|
|
|
241 |
|
|
-- Console UART Receiver ------------------------------------------------------------------
|
242 |
|
|
-- -------------------------------------------------------------------------------------------
|
243 |
|
|
uart_rx_console: process(clk_gen)
|
244 |
3 |
zero_gravi |
variable i : integer;
|
245 |
|
|
variable l : line;
|
246 |
2 |
zero_gravi |
begin
|
247 |
|
|
-- "UART" --
|
248 |
|
|
if rising_edge(clk_gen) then
|
249 |
|
|
-- synchronizer --
|
250 |
|
|
uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
|
251 |
|
|
-- arbiter --
|
252 |
|
|
if (uart_rx_busy = '0') then -- idle
|
253 |
|
|
uart_rx_busy <= '0';
|
254 |
|
|
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
|
255 |
|
|
uart_rx_bitcnt <= 9;
|
256 |
|
|
if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
|
257 |
|
|
uart_rx_busy <= '1';
|
258 |
|
|
end if;
|
259 |
|
|
else
|
260 |
|
|
if (uart_rx_baud_cnt = 0.0) then
|
261 |
|
|
if (uart_rx_bitcnt = 1) then
|
262 |
|
|
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
|
263 |
|
|
else
|
264 |
|
|
uart_rx_baud_cnt <= round(baud_val_c);
|
265 |
|
|
end if;
|
266 |
|
|
if (uart_rx_bitcnt = 0) then
|
267 |
|
|
uart_rx_busy <= '0'; -- done
|
268 |
|
|
i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
|
269 |
|
|
|
270 |
3 |
zero_gravi |
if (i < 32) or (i > 32+95) then -- printable char?
|
271 |
33 |
zero_gravi |
report "NEORV32_TB_UART.TX: (" & integer'image(i) & ")"; -- print code
|
272 |
2 |
zero_gravi |
else
|
273 |
33 |
zero_gravi |
report "NEORV32_TB_UART.TX: " & character'val(i); -- print ASCII
|
274 |
2 |
zero_gravi |
end if;
|
275 |
|
|
|
276 |
|
|
if (i = 10) then -- Linux line break
|
277 |
3 |
zero_gravi |
writeline(file_uart_tx_out, l);
|
278 |
2 |
zero_gravi |
elsif (i /= 13) then -- Remove additional carriage return
|
279 |
3 |
zero_gravi |
write(l, character'val(i));
|
280 |
2 |
zero_gravi |
end if;
|
281 |
|
|
else
|
282 |
|
|
uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
|
283 |
|
|
uart_rx_bitcnt <= uart_rx_bitcnt - 1;
|
284 |
|
|
end if;
|
285 |
|
|
else
|
286 |
|
|
uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
|
287 |
|
|
end if;
|
288 |
|
|
end if;
|
289 |
|
|
end if;
|
290 |
|
|
end process uart_rx_console;
|
291 |
|
|
|
292 |
|
|
|
293 |
30 |
zero_gravi |
-- Wishbone Memory (simulated external memory) --------------------------------------------
|
294 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
295 |
23 |
zero_gravi |
wb_mem_ram_access: process(clk_gen)
|
296 |
|
|
begin
|
297 |
|
|
if rising_edge(clk_gen) then
|
298 |
|
|
-- control --
|
299 |
|
|
wb_mem.rb_en(0) <= wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en and (not wb_cpu.we); -- read-back control
|
300 |
|
|
wb_mem.ack(0) <= wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en; -- wishbone acknowledge
|
301 |
|
|
-- write access --
|
302 |
|
|
if ((wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en and wb_cpu.we) = '1') then -- valid write access
|
303 |
|
|
for i in 0 to 3 loop
|
304 |
|
|
if (wb_cpu.sel(i) = '1') then
|
305 |
30 |
zero_gravi |
wb_ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8);
|
306 |
23 |
zero_gravi |
end if;
|
307 |
|
|
end loop; -- i
|
308 |
2 |
zero_gravi |
end if;
|
309 |
23 |
zero_gravi |
-- read access --
|
310 |
30 |
zero_gravi |
wb_mem.rdata(0) <= wb_ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
|
311 |
23 |
zero_gravi |
-- virtual read and ack latency --
|
312 |
|
|
if (wb_mem_latency_c > 1) then
|
313 |
|
|
for i in 1 to wb_mem_latency_c-1 loop
|
314 |
|
|
wb_mem.rdata(i) <= wb_mem.rdata(i-1);
|
315 |
|
|
wb_mem.rb_en(i) <= wb_mem.rb_en(i-1);
|
316 |
28 |
zero_gravi |
wb_mem.ack(i) <= wb_mem.ack(i-1) and wb_cpu.cyc;
|
317 |
23 |
zero_gravi |
end loop;
|
318 |
|
|
end if;
|
319 |
|
|
end if;
|
320 |
|
|
end process wb_mem_ram_access;
|
321 |
2 |
zero_gravi |
|
322 |
23 |
zero_gravi |
-- wishbone memory access? --
|
323 |
|
|
wb_mem.acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
|
324 |
2 |
zero_gravi |
|
325 |
23 |
zero_gravi |
-- output to cpu --
|
326 |
|
|
wb_cpu.rdata <= wb_mem.rdata(wb_mem_latency_c-1) when (wb_mem.rb_en(wb_mem_latency_c-1) = '1') else (others=> '0'); -- data output gate
|
327 |
31 |
zero_gravi |
wb_cpu.ack <= wb_mem.ack(wb_mem_latency_c-1) and wb_cpu.cyc; -- another AND for classic/standard wishbone transactions
|
328 |
23 |
zero_gravi |
wb_cpu.err <= '0';
|
329 |
2 |
zero_gravi |
|
330 |
3 |
zero_gravi |
|
331 |
2 |
zero_gravi |
end neorv32_tb_rtl;
|