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[/] [neorv32/] [trunk/] [sim/] [neorv32_tb.vhd] - Blame information for rev 49

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1 2 zero_gravi
-- #################################################################################################
2 36 zero_gravi
-- # << NEORV32 - Default Testbench >>                                                             #
3 2 zero_gravi
-- # ********************************************************************************************* #
4 45 zero_gravi
-- # The processor is configured to use a maximum of functional units (for testing purpose).       #
5
-- # Use the "User Configuration" section to configure the testbench according to your needs.      #
6 40 zero_gravi
-- # See NEORV32 data sheet (docs/NEORV32.pdf) for more information.                               #
7 3 zero_gravi
-- # ********************************************************************************************* #
8 2 zero_gravi
-- # BSD 3-Clause License                                                                          #
9
-- #                                                                                               #
10 42 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
11 2 zero_gravi
-- #                                                                                               #
12
-- # Redistribution and use in source and binary forms, with or without modification, are          #
13
-- # permitted provided that the following conditions are met:                                     #
14
-- #                                                                                               #
15
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
16
-- #    conditions and the following disclaimer.                                                   #
17
-- #                                                                                               #
18
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
19
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
20
-- #    provided with the distribution.                                                            #
21
-- #                                                                                               #
22
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
23
-- #    endorse or promote products derived from this software without specific prior written      #
24
-- #    permission.                                                                                #
25
-- #                                                                                               #
26
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
27
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
28
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
29
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
30
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
31
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
32
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
33
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
34
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
35
-- # ********************************************************************************************* #
36
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
37
-- #################################################################################################
38
 
39
library ieee;
40
use ieee.std_logic_1164.all;
41
use ieee.numeric_std.all;
42
use ieee.math_real.all;
43
 
44
library neorv32;
45
use neorv32.neorv32_package.all;
46 30 zero_gravi
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
47 2 zero_gravi
use std.textio.all;
48
 
49
entity neorv32_tb is
50
end neorv32_tb;
51
 
52
architecture neorv32_tb_rtl of neorv32_tb is
53
 
54
  -- User Configuration ---------------------------------------------------------------------
55
  -- -------------------------------------------------------------------------------------------
56 38 zero_gravi
  -- general --
57 39 zero_gravi
  constant ext_imem_c            : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A)
58
  constant ext_dmem_c            : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B)
59 44 zero_gravi
  constant icache_en_c           : boolean := false; -- set true to use processor-internal instruction cache
60 38 zero_gravi
  constant imem_size_c           : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A
61 39 zero_gravi
  constant dmem_size_c           : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B
62 38 zero_gravi
  constant f_clock_c             : natural := 100000000; -- main clock in Hz
63 39 zero_gravi
  constant baud_rate_c           : natural := 19200; -- simulation UART output baudrate
64 38 zero_gravi
  -- simulated external Wishbone memory A (can be used as external IMEM) --
65 39 zero_gravi
  constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
66 38 zero_gravi
  constant ext_mem_a_size_c      : natural := imem_size_c; -- wishbone memory size in bytes
67 40 zero_gravi
  constant ext_mem_a_latency_c   : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
68 39 zero_gravi
  -- simulated external Wishbone memory B (can be used as external DMEM) --
69
  constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base)
70
  constant ext_mem_b_size_c      : natural := dmem_size_c; -- wishbone memory size in bytes
71 40 zero_gravi
  constant ext_mem_b_latency_c   : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
72 39 zero_gravi
  -- simulated external Wishbone memory C (can be used as external IO) --
73
  constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
74
  constant ext_mem_c_size_c      : natural := 64; -- wishbone memory size in bytes
75 40 zero_gravi
  constant ext_mem_c_latency_c   : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
76 47 zero_gravi
  -- simulation interrupt trigger --
77
  constant irq_trigger_c         : std_ulogic_vector(31 downto 0) := x"FF000000";
78 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
79
 
80 38 zero_gravi
  -- internals - hands off! --
81 39 zero_gravi
  constant int_imem_c : boolean := not ext_imem_c;
82
  constant int_dmem_c : boolean := not ext_dmem_c;
83
  constant baud_val_c : real := real(f_clock_c) / real(baud_rate_c);
84
  constant t_clock_c  : time := (1 sec) / f_clock_c;
85 38 zero_gravi
 
86 3 zero_gravi
  -- text.io --
87
  file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
88 2 zero_gravi
 
89
  -- generators --
90
  signal clk_gen, rst_gen : std_ulogic := '0';
91
 
92
  -- simulation uart receiver --
93
  signal uart_txd         : std_ulogic;
94
  signal uart_rx_sync     : std_ulogic_vector(04 downto 0) := (others => '1');
95
  signal uart_rx_busy     : std_ulogic := '0';
96
  signal uart_rx_sreg     : std_ulogic_vector(08 downto 0) := (others => '0');
97
  signal uart_rx_baud_cnt : real;
98
  signal uart_rx_bitcnt   : natural;
99
 
100
  -- gpio --
101 22 zero_gravi
  signal gpio : std_ulogic_vector(31 downto 0);
102 2 zero_gravi
 
103
  -- twi --
104
  signal twi_scl, twi_sda : std_logic;
105
 
106
  -- spi --
107 40 zero_gravi
  signal spi_data : std_ulogic;
108 2 zero_gravi
 
109 40 zero_gravi
  -- irq --
110
  signal msi_ring, mei_ring : std_ulogic;
111 48 zero_gravi
  signal soc_firq_ring      : std_ulogic_vector(7 downto 0);
112 40 zero_gravi
 
113 2 zero_gravi
  -- Wishbone bus --
114
  type wishbone_t is record
115
    addr  : std_ulogic_vector(31 downto 0); -- address
116
    wdata : std_ulogic_vector(31 downto 0); -- master write data
117
    rdata : std_ulogic_vector(31 downto 0); -- master read data
118
    we    : std_ulogic; -- write enable
119
    sel   : std_ulogic_vector(03 downto 0); -- byte enable
120
    stb   : std_ulogic; -- strobe
121
    cyc   : std_ulogic; -- valid cycle
122
    ack   : std_ulogic; -- transfer acknowledge
123
    err   : std_ulogic; -- transfer error
124 36 zero_gravi
    tag   : std_ulogic_vector(2 downto 0); -- tag
125 39 zero_gravi
    lock  : std_ulogic; -- locked/exclusive bus access
126 2 zero_gravi
  end record;
127 47 zero_gravi
  signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
128 2 zero_gravi
 
129 38 zero_gravi
  -- Wishbone memories --
130
  type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
131
  type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
132 39 zero_gravi
  type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
133 38 zero_gravi
  type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
134 30 zero_gravi
 
135
  -- init function --
136
  -- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
137 38 zero_gravi
  impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
138
    variable mem_v : ext_mem_a_ram_t;
139 30 zero_gravi
  begin
140
    mem_v := (others => (others => '0'));
141
    for i in 0 to init'length-1 loop -- init only in range of source data array
142 40 zero_gravi
      if (xbus_big_endian_c = true) then
143 30 zero_gravi
        mem_v(i) := init(i);
144 40 zero_gravi
      else
145
        mem_v(i) := bswap32_f(init(i));
146
      end if;
147 30 zero_gravi
    end loop; -- i
148
    return mem_v;
149
  end function init_wbmem;
150
 
151 38 zero_gravi
  -- external memory components --
152 39 zero_gravi
  signal ext_ram_a : ext_mem_a_ram_t := init_wbmem(application_init_image); -- initialized, used to simulate external IMEM
153
  signal ext_ram_b : ext_mem_b_ram_t := (others => (others => '0')); -- zero, used to simulate external DMEM
154
  signal ext_ram_c : ext_mem_c_ram_t; -- uninitialized, used to simulate external IO
155 30 zero_gravi
 
156 38 zero_gravi
  type ext_mem_t is record
157
    rdata  : ext_mem_read_latency_t;
158 23 zero_gravi
    acc_en : std_ulogic;
159 38 zero_gravi
    ack    : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0);
160 23 zero_gravi
  end record;
161 39 zero_gravi
  signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t;
162 2 zero_gravi
 
163
begin
164
 
165
  -- Clock/Reset Generator ------------------------------------------------------------------
166
  -- -------------------------------------------------------------------------------------------
167
  clk_gen <= not clk_gen after (t_clock_c/2);
168
  rst_gen <= '0', '1' after 60*(t_clock_c/2);
169
 
170
 
171 48 zero_gravi
  -- The Core of the Problem ----------------------------------------------------------------
172 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
173
  neorv32_top_inst: neorv32_top
174
  generic map (
175
    -- General --
176 38 zero_gravi
    CLOCK_FREQUENCY              => f_clock_c,     -- clock frequency of clk_i in Hz
177 44 zero_gravi
    BOOTLOADER_EN                => false,         -- implement processor-internal bootloader?
178 36 zero_gravi
    USER_CODE                    => x"12345678",   -- custom user code
179 49 zero_gravi
    HW_THREAD_ID                 => 0,             -- hardware thread id (hartid) (32-bit)
180 2 zero_gravi
    -- RISC-V CPU Extensions --
181 39 zero_gravi
    CPU_EXTENSION_RISCV_A        => true,          -- implement atomic extension?
182 44 zero_gravi
    CPU_EXTENSION_RISCV_B        => true,          -- implement bit manipulation extensions?
183 8 zero_gravi
    CPU_EXTENSION_RISCV_C        => true,          -- implement compressed extension?
184
    CPU_EXTENSION_RISCV_E        => false,         -- implement embedded RF extension?
185
    CPU_EXTENSION_RISCV_M        => true,          -- implement muld/div extension?
186 15 zero_gravi
    CPU_EXTENSION_RISCV_U        => true,          -- implement user mode extension?
187 8 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    => true,          -- implement CSR system?
188
    CPU_EXTENSION_RISCV_Zifencei => true,          -- implement instruction stream sync.?
189 19 zero_gravi
    -- Extension Options --
190
    FAST_MUL_EN                  => false,         -- use DSPs for M extension's multiplier
191 34 zero_gravi
    FAST_SHIFT_EN                => false,         -- use barrel shifter for shift operations
192 15 zero_gravi
    -- Physical Memory Protection (PMP) --
193 47 zero_gravi
    PMP_NUM_REGIONS              => 4,             -- number of regions (0..64)
194 42 zero_gravi
    PMP_MIN_GRANULARITY          => 64*1024,       -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
195
    -- Hardware Performance Monitors (HPM) --
196
    HPM_NUM_CNTS                 => 12,            -- number of inmplemnted HPM counters (0..29)
197 23 zero_gravi
    -- Internal Instruction memory --
198 44 zero_gravi
    MEM_INT_IMEM_EN              => int_imem_c ,   -- implement processor-internal instruction memory
199 38 zero_gravi
    MEM_INT_IMEM_SIZE            => imem_size_c,   -- size of processor-internal instruction memory in bytes
200 8 zero_gravi
    MEM_INT_IMEM_ROM             => false,         -- implement processor-internal instruction memory as ROM
201 23 zero_gravi
    -- Internal Data memory --
202 44 zero_gravi
    MEM_INT_DMEM_EN              => int_dmem_c,    -- implement processor-internal data memory
203 39 zero_gravi
    MEM_INT_DMEM_SIZE            => dmem_size_c,   -- size of processor-internal data memory in bytes
204 41 zero_gravi
    -- Internal Cache memory --
205 44 zero_gravi
    ICACHE_EN                    => icache_en_c,   -- implement instruction cache
206 41 zero_gravi
    ICACHE_NUM_BLOCKS            => 8,             -- i-cache: number of blocks (min 2), has to be a power of 2
207
    ICACHE_BLOCK_SIZE            => 64,            -- i-cache: block size in bytes (min 4), has to be a power of 2
208 45 zero_gravi
    ICACHE_ASSOCIATIVITY         => 2,             -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
209 23 zero_gravi
    -- External memory interface --
210 44 zero_gravi
    MEM_EXT_EN                   => true,          -- implement external memory bus interface?
211 2 zero_gravi
    -- Processor peripherals --
212 44 zero_gravi
    IO_GPIO_EN                   => true,          -- implement general purpose input/output port unit (GPIO)?
213
    IO_MTIME_EN                  => true,          -- implement machine system timer (MTIME)?
214
    IO_UART_EN                   => true,          -- implement universal asynchronous receiver/transmitter (UART)?
215
    IO_SPI_EN                    => true,          -- implement serial peripheral interface (SPI)?
216
    IO_TWI_EN                    => true,          -- implement two-wire interface (TWI)?
217
    IO_PWM_EN                    => true,          -- implement pulse-width modulation unit (PWM)?
218
    IO_WDT_EN                    => true,          -- implement watch dog timer (WDT)?
219
    IO_TRNG_EN                   => false,         -- trng cannot be simulated
220 47 zero_gravi
    IO_CFS_EN                    => true,          -- implement custom functions subsystem (CFS)?
221 49 zero_gravi
    IO_CFS_CONFIG                => (others => '0'), -- custom CFS configuration generic
222
    IO_NCO_EN                    => true           -- implement numerically-controlled oscillator (NCO)?
223 2 zero_gravi
  )
224
  port map (
225
    -- Global control --
226 34 zero_gravi
    clk_i       => clk_gen,         -- global clock, rising edge
227
    rstn_i      => rst_gen,         -- global reset, low-active, async
228 49 zero_gravi
    -- Wishbone bus interface (available if MEM_EXT_EN = true) --
229 36 zero_gravi
    wb_tag_o    => wb_cpu.tag,      -- tag
230 34 zero_gravi
    wb_adr_o    => wb_cpu.addr,     -- address
231
    wb_dat_i    => wb_cpu.rdata,    -- read data
232
    wb_dat_o    => wb_cpu.wdata,    -- write data
233
    wb_we_o     => wb_cpu.we,       -- read/write
234
    wb_sel_o    => wb_cpu.sel,      -- byte enable
235
    wb_stb_o    => wb_cpu.stb,      -- strobe
236
    wb_cyc_o    => wb_cpu.cyc,      -- valid cycle
237 39 zero_gravi
    wb_lock_o   => wb_cpu.lock,     -- locked/exclusive bus access
238 34 zero_gravi
    wb_ack_i    => wb_cpu.ack,      -- transfer acknowledge
239
    wb_err_i    => wb_cpu.err,      -- transfer error
240 49 zero_gravi
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
241 34 zero_gravi
    fence_o     => open,            -- indicates an executed FENCE operation
242
    fencei_o    => open,            -- indicates an executed FENCEI operation
243 49 zero_gravi
    -- GPIO (available if IO_GPIO_EN = true) --
244 34 zero_gravi
    gpio_o      => gpio,            -- parallel output
245
    gpio_i      => gpio,            -- parallel input
246 49 zero_gravi
    -- UART (available if IO_UART_EN = true) --
247 34 zero_gravi
    uart_txd_o  => uart_txd,        -- UART send data
248
    uart_rxd_i  => uart_txd,        -- UART receive data
249 49 zero_gravi
    -- SPI (available if IO_SPI_EN = true) --
250 34 zero_gravi
    spi_sck_o   => open,            -- SPI serial clock
251
    spi_sdo_o   => spi_data,        -- controller data out, peripheral data in
252
    spi_sdi_i   => spi_data,        -- controller data in, peripheral data out
253
    spi_csn_o   => open,            -- SPI CS
254 49 zero_gravi
    -- TWI (available if IO_TWI_EN = true) --
255 34 zero_gravi
    twi_sda_io  => twi_sda,         -- twi serial data line
256
    twi_scl_io  => twi_scl,         -- twi serial clock line
257 49 zero_gravi
    -- PWM (available if IO_PWM_EN = true) --
258 34 zero_gravi
    pwm_o       => open,            -- pwm channels
259 47 zero_gravi
    -- Custom Functions Subsystem IO --
260
    cfs_in_i    => (others => '0'), -- custom CFS inputs
261
    cfs_out_o   => open,            -- custom CFS outputs
262 49 zero_gravi
    -- NCO output (available if IO_NCO_EN = true) --
263
    nco_o      => open,             -- numerically-controlled oscillator channels
264 44 zero_gravi
    -- system time input from external MTIME (available if IO_MTIME_EN = false) --
265 40 zero_gravi
    mtime_i     => (others => '0'), -- current system time
266 2 zero_gravi
    -- Interrupts --
267 47 zero_gravi
    soc_firq_i  => soc_firq_ring,   -- fast interrupt channels
268 44 zero_gravi
    mtime_irq_i => '0',             -- machine software interrupt, available if IO_MTIME_EN = false
269 40 zero_gravi
    msw_irq_i   => msi_ring,        -- machine software interrupt
270
    mext_irq_i  => mei_ring         -- machine external interrupt
271 2 zero_gravi
  );
272
 
273 36 zero_gravi
  -- TWI termination (pull-ups) --
274 2 zero_gravi
  twi_scl <= 'H';
275
  twi_sda <= 'H';
276
 
277
 
278
  -- Console UART Receiver ------------------------------------------------------------------
279
  -- -------------------------------------------------------------------------------------------
280
  uart_rx_console: process(clk_gen)
281 3 zero_gravi
    variable i : integer;
282
    variable l : line;
283 2 zero_gravi
  begin
284
    -- "UART" --
285
    if rising_edge(clk_gen) then
286
      -- synchronizer --
287
      uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
288
      -- arbiter --
289
      if (uart_rx_busy = '0') then -- idle
290
        uart_rx_busy     <= '0';
291
        uart_rx_baud_cnt <= round(0.5 * baud_val_c);
292
        uart_rx_bitcnt   <= 9;
293
        if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
294
          uart_rx_busy <= '1';
295
        end if;
296
      else
297 38 zero_gravi
        if (uart_rx_baud_cnt <= 0.0) then
298 2 zero_gravi
          if (uart_rx_bitcnt = 1) then
299
            uart_rx_baud_cnt <= round(0.5 * baud_val_c);
300
          else
301
            uart_rx_baud_cnt <= round(baud_val_c);
302
          end if;
303
          if (uart_rx_bitcnt = 0) then
304
            uart_rx_busy <= '0'; -- done
305
            i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
306
 
307 3 zero_gravi
            if (i < 32) or (i > 32+95) then -- printable char?
308 33 zero_gravi
              report "NEORV32_TB_UART.TX: (" & integer'image(i) & ")"; -- print code
309 2 zero_gravi
            else
310 33 zero_gravi
              report "NEORV32_TB_UART.TX: " & character'val(i); -- print ASCII
311 2 zero_gravi
            end if;
312
 
313
            if (i = 10) then -- Linux line break
314 3 zero_gravi
              writeline(file_uart_tx_out, l);
315 2 zero_gravi
            elsif (i /= 13) then -- Remove additional carriage return
316 3 zero_gravi
              write(l, character'val(i));
317 2 zero_gravi
            end if;
318
          else
319
            uart_rx_sreg   <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
320
            uart_rx_bitcnt <= uart_rx_bitcnt - 1;
321
          end if;
322
        else
323
          uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
324
        end if;
325
      end if;
326
    end if;
327
  end process uart_rx_console;
328
 
329
 
330 38 zero_gravi
  -- Wishbone Fabric ------------------------------------------------------------------------
331 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
332 38 zero_gravi
  -- CPU broadcast signals --
333
  wb_mem_a.addr  <= wb_cpu.addr;
334 39 zero_gravi
  wb_mem_a.wdata <= wb_cpu.wdata;
335
  wb_mem_a.we    <= wb_cpu.we;
336
  wb_mem_a.sel   <= wb_cpu.sel;
337
  wb_mem_a.tag   <= wb_cpu.tag;
338
  wb_mem_a.cyc   <= wb_cpu.cyc;
339
  wb_mem_a.lock  <= wb_cpu.lock;
340
 
341 38 zero_gravi
  wb_mem_b.addr  <= wb_cpu.addr;
342
  wb_mem_b.wdata <= wb_cpu.wdata;
343
  wb_mem_b.we    <= wb_cpu.we;
344
  wb_mem_b.sel   <= wb_cpu.sel;
345
  wb_mem_b.tag   <= wb_cpu.tag;
346
  wb_mem_b.cyc   <= wb_cpu.cyc;
347 39 zero_gravi
  wb_mem_b.lock  <= wb_cpu.lock;
348
 
349
  wb_mem_c.addr  <= wb_cpu.addr;
350
  wb_mem_c.wdata <= wb_cpu.wdata;
351
  wb_mem_c.we    <= wb_cpu.we;
352
  wb_mem_c.sel   <= wb_cpu.sel;
353
  wb_mem_c.tag   <= wb_cpu.tag;
354
  wb_mem_c.cyc   <= wb_cpu.cyc;
355
  wb_mem_c.lock  <= wb_cpu.lock;
356
 
357 47 zero_gravi
  wb_irq.addr    <= wb_cpu.addr;
358
  wb_irq.wdata   <= wb_cpu.wdata;
359
  wb_irq.we      <= wb_cpu.we;
360
  wb_irq.sel     <= wb_cpu.sel;
361
  wb_irq.tag     <= wb_cpu.tag;
362
  wb_irq.cyc     <= wb_cpu.cyc;
363
  wb_irq.lock    <= wb_cpu.lock;
364 40 zero_gravi
 
365 38 zero_gravi
  -- CPU read-back signals (no mux here since peripherals have "output gates") --
366 47 zero_gravi
  wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata;
367
  wb_cpu.ack   <= wb_mem_a.ack   or wb_mem_b.ack   or wb_mem_c.ack   or wb_irq.ack;
368
  wb_cpu.err   <= wb_mem_a.err   or wb_mem_b.err   or wb_mem_c.err   or wb_irq.err;
369 38 zero_gravi
 
370
  -- peripheral select via STROBE signal --
371
  wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
372
  wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
373 39 zero_gravi
  wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
374 47 zero_gravi
  wb_irq.stb   <= wb_cpu.stb when (wb_cpu.addr =  irq_trigger_c) else '0';
375 38 zero_gravi
 
376
 
377 39 zero_gravi
  -- Wishbone Memory A (simulated external IMEM) --------------------------------------------
378 38 zero_gravi
  -- -------------------------------------------------------------------------------------------
379
  ext_mem_a_access: process(clk_gen)
380 23 zero_gravi
  begin
381
    if rising_edge(clk_gen) then
382
      -- control --
383 38 zero_gravi
      ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge
384
 
385 23 zero_gravi
      -- write access --
386 38 zero_gravi
      if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access
387 23 zero_gravi
        for i in 0 to 3 loop
388 38 zero_gravi
          if (wb_mem_a.sel(i) = '1') then
389
            ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_a.wdata(7+i*8 downto 0+i*8);
390 23 zero_gravi
          end if;
391
        end loop; -- i
392 2 zero_gravi
      end if;
393 38 zero_gravi
 
394 23 zero_gravi
      -- read access --
395 38 zero_gravi
      ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned
396 23 zero_gravi
      -- virtual read and ack latency --
397 38 zero_gravi
      if (ext_mem_a_latency_c > 1) then
398
        for i in 1 to ext_mem_a_latency_c-1 loop
399
          ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1);
400
          ext_mem_a.ack(i)   <= ext_mem_a.ack(i-1) and wb_mem_a.cyc;
401 23 zero_gravi
        end loop;
402
      end if;
403 38 zero_gravi
 
404
      -- bus output register --
405
      wb_mem_a.err <= '0';
406
      if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
407
        wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
408
        wb_mem_a.ack   <= '1';
409
      else
410
        wb_mem_a.rdata <= (others => '0');
411
        wb_mem_a.ack   <= '0';
412
      end if;
413 23 zero_gravi
    end if;
414 38 zero_gravi
  end process ext_mem_a_access;
415 2 zero_gravi
 
416
 
417 39 zero_gravi
  -- Wishbone Memory B (simulated external DMEM) --------------------------------------------
418 38 zero_gravi
  -- -------------------------------------------------------------------------------------------
419
  ext_mem_b_access: process(clk_gen)
420
  begin
421
    if rising_edge(clk_gen) then
422
      -- control --
423
      ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge
424 2 zero_gravi
 
425 38 zero_gravi
      -- write access --
426
      if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access
427
        for i in 0 to 3 loop
428
          if (wb_mem_b.sel(i) = '1') then
429
            ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_b.wdata(7+i*8 downto 0+i*8);
430
          end if;
431
        end loop; -- i
432
      end if;
433 3 zero_gravi
 
434 38 zero_gravi
      -- read access --
435
      ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned
436
      -- virtual read and ack latency --
437
      if (ext_mem_b_latency_c > 1) then
438
        for i in 1 to ext_mem_b_latency_c-1 loop
439
          ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1);
440
          ext_mem_b.ack(i)   <= ext_mem_b.ack(i-1) and wb_mem_b.cyc;
441
        end loop;
442
      end if;
443
 
444
      -- bus output register --
445
      wb_mem_b.err <= '0';
446
      if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
447
        wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
448
        wb_mem_b.ack   <= '1';
449
      else
450
        wb_mem_b.rdata <= (others => '0');
451
        wb_mem_b.ack   <= '0';
452
      end if;
453
    end if;
454
  end process ext_mem_b_access;
455
 
456
 
457 39 zero_gravi
  -- Wishbone Memory C (simulated external IO) ----------------------------------------------
458
  -- -------------------------------------------------------------------------------------------
459
  ext_mem_c_access: process(clk_gen)
460
  begin
461
    if rising_edge(clk_gen) then
462
      -- control --
463
      ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge
464
 
465
      -- write access --
466
      if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access
467
        for i in 0 to 3 loop
468
          if (wb_mem_c.sel(i) = '1') then
469
            ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8);
470
          end if;
471
        end loop; -- i
472
      end if;
473
 
474
      -- read access --
475
      ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned
476
      -- virtual read and ack latency --
477
      if (ext_mem_c_latency_c > 1) then
478
        for i in 1 to ext_mem_c_latency_c-1 loop
479
          ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1);
480
          ext_mem_c.ack(i)   <= ext_mem_c.ack(i-1) and wb_mem_c.cyc;
481
        end loop;
482
      end if;
483
 
484
      -- error to simulate interrupted LOCKED/EXCLUSIVE bus access --
485
      wb_mem_c.err <= wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.lock and wb_mem_c.addr(2); -- locked access to odd word-addresses will fail
486
 
487
      -- bus output register --
488
      if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') then
489
        wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
490
        wb_mem_c.ack   <= '1';
491
      else
492
        wb_mem_c.rdata <= (others => '0');
493
        wb_mem_c.ack   <= '0';
494
      end if;
495
    end if;
496
  end process ext_mem_c_access;
497
 
498
 
499 40 zero_gravi
  -- Wishbone IRQ Triggers ------------------------------------------------------------------
500
  -- -------------------------------------------------------------------------------------------
501 45 zero_gravi
  irq_trigger: process(clk_gen)
502 40 zero_gravi
  begin
503
    if rising_edge(clk_gen) then
504 47 zero_gravi
      -- bus interface --
505
      wb_irq.rdata  <= (others => '0');
506 48 zero_gravi
      wb_irq.ack    <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel);
507 47 zero_gravi
      wb_irq.err    <= '0';
508
      -- trigger IRQ using CSR.MIE bit layout --
509
      msi_ring      <= '0';
510
      mei_ring      <= '0';
511
      soc_firq_ring <= (others => '0');
512 48 zero_gravi
      if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
513 47 zero_gravi
        msi_ring         <= wb_irq.wdata(03); -- machine software interrupt
514
        mei_ring         <= wb_irq.wdata(11); -- machine software interrupt
515 48 zero_gravi
        soc_firq_ring(0) <= wb_irq.wdata(24); -- fast interrupt SoC channel 0
516
        soc_firq_ring(1) <= wb_irq.wdata(25); -- fast interrupt SoC channel 1
517
        soc_firq_ring(2) <= wb_irq.wdata(26); -- fast interrupt SoC channel 2
518
        soc_firq_ring(3) <= wb_irq.wdata(27); -- fast interrupt SoC channel 3
519
        soc_firq_ring(4) <= wb_irq.wdata(28); -- fast interrupt SoC channel 4
520
        soc_firq_ring(5) <= wb_irq.wdata(29); -- fast interrupt SoC channel 5
521
        soc_firq_ring(6) <= wb_irq.wdata(30); -- fast interrupt SoC channel 6
522
        soc_firq_ring(7) <= wb_irq.wdata(31); -- fast interrupt SoC channel 7
523 40 zero_gravi
      end if;
524
    end if;
525 45 zero_gravi
  end process irq_trigger;
526 40 zero_gravi
 
527
 
528 2 zero_gravi
end neorv32_tb_rtl;

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