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1 2 zero_gravi
-- #################################################################################################
2 36 zero_gravi
-- # << NEORV32 - Default Testbench >>                                                             #
3 2 zero_gravi
-- # ********************************************************************************************* #
4 45 zero_gravi
-- # The processor is configured to use a maximum of functional units (for testing purpose).       #
5
-- # Use the "User Configuration" section to configure the testbench according to your needs.      #
6 40 zero_gravi
-- # See NEORV32 data sheet (docs/NEORV32.pdf) for more information.                               #
7 3 zero_gravi
-- # ********************************************************************************************* #
8 2 zero_gravi
-- # BSD 3-Clause License                                                                          #
9
-- #                                                                                               #
10 42 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
11 2 zero_gravi
-- #                                                                                               #
12
-- # Redistribution and use in source and binary forms, with or without modification, are          #
13
-- # permitted provided that the following conditions are met:                                     #
14
-- #                                                                                               #
15
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
16
-- #    conditions and the following disclaimer.                                                   #
17
-- #                                                                                               #
18
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
19
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
20
-- #    provided with the distribution.                                                            #
21
-- #                                                                                               #
22
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
23
-- #    endorse or promote products derived from this software without specific prior written      #
24
-- #    permission.                                                                                #
25
-- #                                                                                               #
26
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
27
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
28
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
29
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
30
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
31
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
32
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
33
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
34
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
35
-- # ********************************************************************************************* #
36
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
37
-- #################################################################################################
38
 
39
library ieee;
40
use ieee.std_logic_1164.all;
41
use ieee.numeric_std.all;
42
use ieee.math_real.all;
43
 
44
library neorv32;
45
use neorv32.neorv32_package.all;
46 30 zero_gravi
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
47 2 zero_gravi
use std.textio.all;
48
 
49
entity neorv32_tb is
50
end neorv32_tb;
51
 
52
architecture neorv32_tb_rtl of neorv32_tb is
53
 
54
  -- User Configuration ---------------------------------------------------------------------
55
  -- -------------------------------------------------------------------------------------------
56 38 zero_gravi
  -- general --
57 39 zero_gravi
  constant ext_imem_c            : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A)
58
  constant ext_dmem_c            : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B)
59 44 zero_gravi
  constant icache_en_c           : boolean := false; -- set true to use processor-internal instruction cache
60 38 zero_gravi
  constant imem_size_c           : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A
61 39 zero_gravi
  constant dmem_size_c           : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B
62 38 zero_gravi
  constant f_clock_c             : natural := 100000000; -- main clock in Hz
63 50 zero_gravi
  constant baud0_rate_c          : natural := 19200; -- simulation UART0 (primary UART) baud rate
64
  constant baud1_rate_c          : natural := 19200; -- simulation UART1 (secondary UART) baud rate
65 38 zero_gravi
  -- simulated external Wishbone memory A (can be used as external IMEM) --
66 39 zero_gravi
  constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
67 38 zero_gravi
  constant ext_mem_a_size_c      : natural := imem_size_c; -- wishbone memory size in bytes
68 40 zero_gravi
  constant ext_mem_a_latency_c   : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
69 39 zero_gravi
  -- simulated external Wishbone memory B (can be used as external DMEM) --
70
  constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base)
71
  constant ext_mem_b_size_c      : natural := dmem_size_c; -- wishbone memory size in bytes
72 40 zero_gravi
  constant ext_mem_b_latency_c   : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
73 39 zero_gravi
  -- simulated external Wishbone memory C (can be used as external IO) --
74
  constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
75
  constant ext_mem_c_size_c      : natural := 64; -- wishbone memory size in bytes
76 40 zero_gravi
  constant ext_mem_c_latency_c   : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
77 47 zero_gravi
  -- simulation interrupt trigger --
78
  constant irq_trigger_c         : std_ulogic_vector(31 downto 0) := x"FF000000";
79 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
80
 
81 38 zero_gravi
  -- internals - hands off! --
82 50 zero_gravi
  constant int_imem_c       : boolean := not ext_imem_c;
83
  constant int_dmem_c       : boolean := not ext_dmem_c;
84
  constant uart0_baud_val_c : real := real(f_clock_c) / real(baud0_rate_c);
85
  constant uart1_baud_val_c : real := real(f_clock_c) / real(baud1_rate_c);
86
  constant t_clock_c        : time := (1 sec) / f_clock_c;
87 38 zero_gravi
 
88 2 zero_gravi
  -- generators --
89
  signal clk_gen, rst_gen : std_ulogic := '0';
90
 
91 50 zero_gravi
  -- text.io --
92
  file file_uart0_tx_out : text open write_mode is "neorv32.testbench_uart0.out";
93
  file file_uart1_tx_out : text open write_mode is "neorv32.testbench_uart1.out";
94 2 zero_gravi
 
95 50 zero_gravi
  -- simulation uart0 receiver --
96
  signal uart0_txd         : std_ulogic;
97
  signal uart0_rx_sync     : std_ulogic_vector(04 downto 0) := (others => '1');
98
  signal uart0_rx_busy     : std_ulogic := '0';
99
  signal uart0_rx_sreg     : std_ulogic_vector(08 downto 0) := (others => '0');
100
  signal uart0_rx_baud_cnt : real;
101
  signal uart0_rx_bitcnt   : natural;
102
 
103
  -- simulation uart1 receiver --
104
  signal uart1_txd         : std_ulogic;
105
  signal uart1_rx_sync     : std_ulogic_vector(04 downto 0) := (others => '1');
106
  signal uart1_rx_busy     : std_ulogic := '0';
107
  signal uart1_rx_sreg     : std_ulogic_vector(08 downto 0) := (others => '0');
108
  signal uart1_rx_baud_cnt : real;
109
  signal uart1_rx_bitcnt   : natural;
110
 
111 2 zero_gravi
  -- gpio --
112 22 zero_gravi
  signal gpio : std_ulogic_vector(31 downto 0);
113 2 zero_gravi
 
114
  -- twi --
115
  signal twi_scl, twi_sda : std_logic;
116
 
117
  -- spi --
118 40 zero_gravi
  signal spi_data : std_ulogic;
119 2 zero_gravi
 
120 40 zero_gravi
  -- irq --
121
  signal msi_ring, mei_ring : std_ulogic;
122 50 zero_gravi
  signal soc_firq_ring      : std_ulogic_vector(5 downto 0);
123 40 zero_gravi
 
124 2 zero_gravi
  -- Wishbone bus --
125
  type wishbone_t is record
126
    addr  : std_ulogic_vector(31 downto 0); -- address
127
    wdata : std_ulogic_vector(31 downto 0); -- master write data
128
    rdata : std_ulogic_vector(31 downto 0); -- master read data
129
    we    : std_ulogic; -- write enable
130
    sel   : std_ulogic_vector(03 downto 0); -- byte enable
131
    stb   : std_ulogic; -- strobe
132
    cyc   : std_ulogic; -- valid cycle
133
    ack   : std_ulogic; -- transfer acknowledge
134
    err   : std_ulogic; -- transfer error
135 36 zero_gravi
    tag   : std_ulogic_vector(2 downto 0); -- tag
136 39 zero_gravi
    lock  : std_ulogic; -- locked/exclusive bus access
137 2 zero_gravi
  end record;
138 47 zero_gravi
  signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
139 2 zero_gravi
 
140 38 zero_gravi
  -- Wishbone memories --
141
  type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
142
  type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
143 39 zero_gravi
  type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
144 38 zero_gravi
  type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
145 30 zero_gravi
 
146
  -- init function --
147
  -- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
148 38 zero_gravi
  impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
149
    variable mem_v : ext_mem_a_ram_t;
150 30 zero_gravi
  begin
151
    mem_v := (others => (others => '0'));
152
    for i in 0 to init'length-1 loop -- init only in range of source data array
153 40 zero_gravi
      if (xbus_big_endian_c = true) then
154 30 zero_gravi
        mem_v(i) := init(i);
155 40 zero_gravi
      else
156
        mem_v(i) := bswap32_f(init(i));
157
      end if;
158 30 zero_gravi
    end loop; -- i
159
    return mem_v;
160
  end function init_wbmem;
161
 
162 38 zero_gravi
  -- external memory components --
163 39 zero_gravi
  signal ext_ram_a : ext_mem_a_ram_t := init_wbmem(application_init_image); -- initialized, used to simulate external IMEM
164
  signal ext_ram_b : ext_mem_b_ram_t := (others => (others => '0')); -- zero, used to simulate external DMEM
165
  signal ext_ram_c : ext_mem_c_ram_t; -- uninitialized, used to simulate external IO
166 30 zero_gravi
 
167 38 zero_gravi
  type ext_mem_t is record
168
    rdata  : ext_mem_read_latency_t;
169 23 zero_gravi
    acc_en : std_ulogic;
170 38 zero_gravi
    ack    : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0);
171 23 zero_gravi
  end record;
172 39 zero_gravi
  signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t;
173 2 zero_gravi
 
174
begin
175
 
176
  -- Clock/Reset Generator ------------------------------------------------------------------
177
  -- -------------------------------------------------------------------------------------------
178
  clk_gen <= not clk_gen after (t_clock_c/2);
179
  rst_gen <= '0', '1' after 60*(t_clock_c/2);
180
 
181
 
182 48 zero_gravi
  -- The Core of the Problem ----------------------------------------------------------------
183 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
184
  neorv32_top_inst: neorv32_top
185
  generic map (
186
    -- General --
187 38 zero_gravi
    CLOCK_FREQUENCY              => f_clock_c,     -- clock frequency of clk_i in Hz
188 44 zero_gravi
    BOOTLOADER_EN                => false,         -- implement processor-internal bootloader?
189 36 zero_gravi
    USER_CODE                    => x"12345678",   -- custom user code
190 49 zero_gravi
    HW_THREAD_ID                 => 0,             -- hardware thread id (hartid) (32-bit)
191 2 zero_gravi
    -- RISC-V CPU Extensions --
192 39 zero_gravi
    CPU_EXTENSION_RISCV_A        => true,          -- implement atomic extension?
193 44 zero_gravi
    CPU_EXTENSION_RISCV_B        => true,          -- implement bit manipulation extensions?
194 8 zero_gravi
    CPU_EXTENSION_RISCV_C        => true,          -- implement compressed extension?
195
    CPU_EXTENSION_RISCV_E        => false,         -- implement embedded RF extension?
196
    CPU_EXTENSION_RISCV_M        => true,          -- implement muld/div extension?
197 15 zero_gravi
    CPU_EXTENSION_RISCV_U        => true,          -- implement user mode extension?
198 8 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    => true,          -- implement CSR system?
199
    CPU_EXTENSION_RISCV_Zifencei => true,          -- implement instruction stream sync.?
200 19 zero_gravi
    -- Extension Options --
201
    FAST_MUL_EN                  => false,         -- use DSPs for M extension's multiplier
202 34 zero_gravi
    FAST_SHIFT_EN                => false,         -- use barrel shifter for shift operations
203 15 zero_gravi
    -- Physical Memory Protection (PMP) --
204 47 zero_gravi
    PMP_NUM_REGIONS              => 4,             -- number of regions (0..64)
205 42 zero_gravi
    PMP_MIN_GRANULARITY          => 64*1024,       -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
206
    -- Hardware Performance Monitors (HPM) --
207
    HPM_NUM_CNTS                 => 12,            -- number of inmplemnted HPM counters (0..29)
208 23 zero_gravi
    -- Internal Instruction memory --
209 44 zero_gravi
    MEM_INT_IMEM_EN              => int_imem_c ,   -- implement processor-internal instruction memory
210 38 zero_gravi
    MEM_INT_IMEM_SIZE            => imem_size_c,   -- size of processor-internal instruction memory in bytes
211 8 zero_gravi
    MEM_INT_IMEM_ROM             => false,         -- implement processor-internal instruction memory as ROM
212 23 zero_gravi
    -- Internal Data memory --
213 44 zero_gravi
    MEM_INT_DMEM_EN              => int_dmem_c,    -- implement processor-internal data memory
214 39 zero_gravi
    MEM_INT_DMEM_SIZE            => dmem_size_c,   -- size of processor-internal data memory in bytes
215 41 zero_gravi
    -- Internal Cache memory --
216 44 zero_gravi
    ICACHE_EN                    => icache_en_c,   -- implement instruction cache
217 41 zero_gravi
    ICACHE_NUM_BLOCKS            => 8,             -- i-cache: number of blocks (min 2), has to be a power of 2
218
    ICACHE_BLOCK_SIZE            => 64,            -- i-cache: block size in bytes (min 4), has to be a power of 2
219 45 zero_gravi
    ICACHE_ASSOCIATIVITY         => 2,             -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
220 23 zero_gravi
    -- External memory interface --
221 44 zero_gravi
    MEM_EXT_EN                   => true,          -- implement external memory bus interface?
222 2 zero_gravi
    -- Processor peripherals --
223 44 zero_gravi
    IO_GPIO_EN                   => true,          -- implement general purpose input/output port unit (GPIO)?
224
    IO_MTIME_EN                  => true,          -- implement machine system timer (MTIME)?
225 50 zero_gravi
    IO_UART0_EN                  => true,          -- implement primary universal asynchronous receiver/transmitter (UART0)?
226
    IO_UART1_EN                  => true,          -- implement secondary universal asynchronous receiver/transmitter (UART1)?
227 44 zero_gravi
    IO_SPI_EN                    => true,          -- implement serial peripheral interface (SPI)?
228
    IO_TWI_EN                    => true,          -- implement two-wire interface (TWI)?
229
    IO_PWM_EN                    => true,          -- implement pulse-width modulation unit (PWM)?
230
    IO_WDT_EN                    => true,          -- implement watch dog timer (WDT)?
231
    IO_TRNG_EN                   => false,         -- trng cannot be simulated
232 47 zero_gravi
    IO_CFS_EN                    => true,          -- implement custom functions subsystem (CFS)?
233 49 zero_gravi
    IO_CFS_CONFIG                => (others => '0'), -- custom CFS configuration generic
234
    IO_NCO_EN                    => true           -- implement numerically-controlled oscillator (NCO)?
235 2 zero_gravi
  )
236
  port map (
237
    -- Global control --
238 34 zero_gravi
    clk_i       => clk_gen,         -- global clock, rising edge
239
    rstn_i      => rst_gen,         -- global reset, low-active, async
240 49 zero_gravi
    -- Wishbone bus interface (available if MEM_EXT_EN = true) --
241 36 zero_gravi
    wb_tag_o    => wb_cpu.tag,      -- tag
242 34 zero_gravi
    wb_adr_o    => wb_cpu.addr,     -- address
243
    wb_dat_i    => wb_cpu.rdata,    -- read data
244
    wb_dat_o    => wb_cpu.wdata,    -- write data
245
    wb_we_o     => wb_cpu.we,       -- read/write
246
    wb_sel_o    => wb_cpu.sel,      -- byte enable
247
    wb_stb_o    => wb_cpu.stb,      -- strobe
248
    wb_cyc_o    => wb_cpu.cyc,      -- valid cycle
249 39 zero_gravi
    wb_lock_o   => wb_cpu.lock,     -- locked/exclusive bus access
250 34 zero_gravi
    wb_ack_i    => wb_cpu.ack,      -- transfer acknowledge
251
    wb_err_i    => wb_cpu.err,      -- transfer error
252 49 zero_gravi
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
253 34 zero_gravi
    fence_o     => open,            -- indicates an executed FENCE operation
254
    fencei_o    => open,            -- indicates an executed FENCEI operation
255 49 zero_gravi
    -- GPIO (available if IO_GPIO_EN = true) --
256 34 zero_gravi
    gpio_o      => gpio,            -- parallel output
257
    gpio_i      => gpio,            -- parallel input
258 50 zero_gravi
    -- primary UART0 (available if IO_UART0_EN = true) --
259
    uart0_txd_o => uart0_txd,       -- UART0 send data
260
    uart0_rxd_i => uart0_txd,       -- UART0 receive data
261
    -- secondary UART1 (available if IO_UART1_EN = true) --
262
    uart1_txd_o => uart1_txd,       -- UART1 send data
263
    uart1_rxd_i => uart1_txd,       -- UART1 receive data
264 49 zero_gravi
    -- SPI (available if IO_SPI_EN = true) --
265 34 zero_gravi
    spi_sck_o   => open,            -- SPI serial clock
266
    spi_sdo_o   => spi_data,        -- controller data out, peripheral data in
267
    spi_sdi_i   => spi_data,        -- controller data in, peripheral data out
268
    spi_csn_o   => open,            -- SPI CS
269 49 zero_gravi
    -- TWI (available if IO_TWI_EN = true) --
270 34 zero_gravi
    twi_sda_io  => twi_sda,         -- twi serial data line
271
    twi_scl_io  => twi_scl,         -- twi serial clock line
272 49 zero_gravi
    -- PWM (available if IO_PWM_EN = true) --
273 34 zero_gravi
    pwm_o       => open,            -- pwm channels
274 47 zero_gravi
    -- Custom Functions Subsystem IO --
275
    cfs_in_i    => (others => '0'), -- custom CFS inputs
276
    cfs_out_o   => open,            -- custom CFS outputs
277 49 zero_gravi
    -- NCO output (available if IO_NCO_EN = true) --
278
    nco_o      => open,             -- numerically-controlled oscillator channels
279 44 zero_gravi
    -- system time input from external MTIME (available if IO_MTIME_EN = false) --
280 40 zero_gravi
    mtime_i     => (others => '0'), -- current system time
281 2 zero_gravi
    -- Interrupts --
282 47 zero_gravi
    soc_firq_i  => soc_firq_ring,   -- fast interrupt channels
283 44 zero_gravi
    mtime_irq_i => '0',             -- machine software interrupt, available if IO_MTIME_EN = false
284 40 zero_gravi
    msw_irq_i   => msi_ring,        -- machine software interrupt
285
    mext_irq_i  => mei_ring         -- machine external interrupt
286 2 zero_gravi
  );
287
 
288 36 zero_gravi
  -- TWI termination (pull-ups) --
289 2 zero_gravi
  twi_scl <= 'H';
290
  twi_sda <= 'H';
291
 
292
 
293 50 zero_gravi
  -- Console UART0 Receiver -----------------------------------------------------------------
294 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
295 50 zero_gravi
  uart0_rx_console: process(clk_gen)
296 3 zero_gravi
    variable i : integer;
297
    variable l : line;
298 2 zero_gravi
  begin
299
    -- "UART" --
300
    if rising_edge(clk_gen) then
301
      -- synchronizer --
302 50 zero_gravi
      uart0_rx_sync <= uart0_rx_sync(3 downto 0) & uart0_txd;
303 2 zero_gravi
      -- arbiter --
304 50 zero_gravi
      if (uart0_rx_busy = '0') then -- idle
305
        uart0_rx_busy     <= '0';
306
        uart0_rx_baud_cnt <= round(0.5 * uart0_baud_val_c);
307
        uart0_rx_bitcnt   <= 9;
308
        if (uart0_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
309
          uart0_rx_busy <= '1';
310 2 zero_gravi
        end if;
311
      else
312 50 zero_gravi
        if (uart0_rx_baud_cnt <= 0.0) then
313
          if (uart0_rx_bitcnt = 1) then
314
            uart0_rx_baud_cnt <= round(0.5 * uart0_baud_val_c);
315 2 zero_gravi
          else
316 50 zero_gravi
            uart0_rx_baud_cnt <= round(uart0_baud_val_c);
317 2 zero_gravi
          end if;
318 50 zero_gravi
          if (uart0_rx_bitcnt = 0) then
319
            uart0_rx_busy <= '0'; -- done
320
            i := to_integer(unsigned(uart0_rx_sreg(8 downto 1)));
321 2 zero_gravi
 
322 3 zero_gravi
            if (i < 32) or (i > 32+95) then -- printable char?
323 50 zero_gravi
              report "NEORV32_TB_UART0.TX: (" & integer'image(i) & ")"; -- print code
324 2 zero_gravi
            else
325 50 zero_gravi
              report "NEORV32_TB_UART0.TX: " & character'val(i); -- print ASCII
326 2 zero_gravi
            end if;
327
 
328
            if (i = 10) then -- Linux line break
329 50 zero_gravi
              writeline(file_uart0_tx_out, l);
330 2 zero_gravi
            elsif (i /= 13) then -- Remove additional carriage return
331 3 zero_gravi
              write(l, character'val(i));
332 2 zero_gravi
            end if;
333
          else
334 50 zero_gravi
            uart0_rx_sreg   <= uart0_rx_sync(4) & uart0_rx_sreg(8 downto 1);
335
            uart0_rx_bitcnt <= uart0_rx_bitcnt - 1;
336 2 zero_gravi
          end if;
337
        else
338 50 zero_gravi
          uart0_rx_baud_cnt <= uart0_rx_baud_cnt - 1.0;
339 2 zero_gravi
        end if;
340
      end if;
341
    end if;
342 50 zero_gravi
  end process uart0_rx_console;
343 2 zero_gravi
 
344
 
345 50 zero_gravi
  -- Console UART1 Receiver -----------------------------------------------------------------
346
  -- -------------------------------------------------------------------------------------------
347
  uart1_rx_console: process(clk_gen)
348
    variable i : integer;
349
    variable l : line;
350
  begin
351
    -- "UART" --
352
    if rising_edge(clk_gen) then
353
      -- synchronizer --
354
      uart1_rx_sync <= uart1_rx_sync(3 downto 0) & uart1_txd;
355
      -- arbiter --
356
      if (uart1_rx_busy = '0') then -- idle
357
        uart1_rx_busy     <= '0';
358
        uart1_rx_baud_cnt <= round(0.5 * uart1_baud_val_c);
359
        uart1_rx_bitcnt   <= 9;
360
        if (uart1_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
361
          uart1_rx_busy <= '1';
362
        end if;
363
      else
364
        if (uart1_rx_baud_cnt <= 0.0) then
365
          if (uart1_rx_bitcnt = 1) then
366
            uart1_rx_baud_cnt <= round(0.5 * uart1_baud_val_c);
367
          else
368
            uart1_rx_baud_cnt <= round(uart1_baud_val_c);
369
          end if;
370
          if (uart1_rx_bitcnt = 0) then
371
            uart1_rx_busy <= '0'; -- done
372
            i := to_integer(unsigned(uart1_rx_sreg(8 downto 1)));
373
 
374
            if (i < 32) or (i > 32+95) then -- printable char?
375
              report "NEORV32_TB_UART1.TX: (" & integer'image(i) & ")"; -- print code
376
            else
377
              report "NEORV32_TB_UART1.TX: " & character'val(i); -- print ASCII
378
            end if;
379
 
380
            if (i = 10) then -- Linux line break
381
              writeline(file_uart1_tx_out, l);
382
            elsif (i /= 13) then -- Remove additional carriage return
383
              write(l, character'val(i));
384
            end if;
385
          else
386
            uart1_rx_sreg   <= uart1_rx_sync(4) & uart1_rx_sreg(8 downto 1);
387
            uart1_rx_bitcnt <= uart1_rx_bitcnt - 1;
388
          end if;
389
        else
390
          uart1_rx_baud_cnt <= uart1_rx_baud_cnt - 1.0;
391
        end if;
392
      end if;
393
    end if;
394
  end process uart1_rx_console;
395
 
396
 
397 38 zero_gravi
  -- Wishbone Fabric ------------------------------------------------------------------------
398 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
399 38 zero_gravi
  -- CPU broadcast signals --
400
  wb_mem_a.addr  <= wb_cpu.addr;
401 39 zero_gravi
  wb_mem_a.wdata <= wb_cpu.wdata;
402
  wb_mem_a.we    <= wb_cpu.we;
403
  wb_mem_a.sel   <= wb_cpu.sel;
404
  wb_mem_a.tag   <= wb_cpu.tag;
405
  wb_mem_a.cyc   <= wb_cpu.cyc;
406
  wb_mem_a.lock  <= wb_cpu.lock;
407
 
408 38 zero_gravi
  wb_mem_b.addr  <= wb_cpu.addr;
409
  wb_mem_b.wdata <= wb_cpu.wdata;
410
  wb_mem_b.we    <= wb_cpu.we;
411
  wb_mem_b.sel   <= wb_cpu.sel;
412
  wb_mem_b.tag   <= wb_cpu.tag;
413
  wb_mem_b.cyc   <= wb_cpu.cyc;
414 39 zero_gravi
  wb_mem_b.lock  <= wb_cpu.lock;
415
 
416
  wb_mem_c.addr  <= wb_cpu.addr;
417
  wb_mem_c.wdata <= wb_cpu.wdata;
418
  wb_mem_c.we    <= wb_cpu.we;
419
  wb_mem_c.sel   <= wb_cpu.sel;
420
  wb_mem_c.tag   <= wb_cpu.tag;
421
  wb_mem_c.cyc   <= wb_cpu.cyc;
422
  wb_mem_c.lock  <= wb_cpu.lock;
423
 
424 47 zero_gravi
  wb_irq.addr    <= wb_cpu.addr;
425
  wb_irq.wdata   <= wb_cpu.wdata;
426
  wb_irq.we      <= wb_cpu.we;
427
  wb_irq.sel     <= wb_cpu.sel;
428
  wb_irq.tag     <= wb_cpu.tag;
429
  wb_irq.cyc     <= wb_cpu.cyc;
430
  wb_irq.lock    <= wb_cpu.lock;
431 40 zero_gravi
 
432 38 zero_gravi
  -- CPU read-back signals (no mux here since peripherals have "output gates") --
433 47 zero_gravi
  wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata;
434
  wb_cpu.ack   <= wb_mem_a.ack   or wb_mem_b.ack   or wb_mem_c.ack   or wb_irq.ack;
435
  wb_cpu.err   <= wb_mem_a.err   or wb_mem_b.err   or wb_mem_c.err   or wb_irq.err;
436 38 zero_gravi
 
437
  -- peripheral select via STROBE signal --
438
  wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
439
  wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
440 39 zero_gravi
  wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
441 47 zero_gravi
  wb_irq.stb   <= wb_cpu.stb when (wb_cpu.addr =  irq_trigger_c) else '0';
442 38 zero_gravi
 
443
 
444 39 zero_gravi
  -- Wishbone Memory A (simulated external IMEM) --------------------------------------------
445 38 zero_gravi
  -- -------------------------------------------------------------------------------------------
446
  ext_mem_a_access: process(clk_gen)
447 23 zero_gravi
  begin
448
    if rising_edge(clk_gen) then
449
      -- control --
450 38 zero_gravi
      ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge
451
 
452 23 zero_gravi
      -- write access --
453 38 zero_gravi
      if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access
454 23 zero_gravi
        for i in 0 to 3 loop
455 38 zero_gravi
          if (wb_mem_a.sel(i) = '1') then
456
            ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_a.wdata(7+i*8 downto 0+i*8);
457 23 zero_gravi
          end if;
458
        end loop; -- i
459 2 zero_gravi
      end if;
460 38 zero_gravi
 
461 23 zero_gravi
      -- read access --
462 38 zero_gravi
      ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned
463 23 zero_gravi
      -- virtual read and ack latency --
464 38 zero_gravi
      if (ext_mem_a_latency_c > 1) then
465
        for i in 1 to ext_mem_a_latency_c-1 loop
466
          ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1);
467
          ext_mem_a.ack(i)   <= ext_mem_a.ack(i-1) and wb_mem_a.cyc;
468 23 zero_gravi
        end loop;
469
      end if;
470 38 zero_gravi
 
471
      -- bus output register --
472
      wb_mem_a.err <= '0';
473
      if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
474
        wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
475
        wb_mem_a.ack   <= '1';
476
      else
477
        wb_mem_a.rdata <= (others => '0');
478
        wb_mem_a.ack   <= '0';
479
      end if;
480 23 zero_gravi
    end if;
481 38 zero_gravi
  end process ext_mem_a_access;
482 2 zero_gravi
 
483
 
484 39 zero_gravi
  -- Wishbone Memory B (simulated external DMEM) --------------------------------------------
485 38 zero_gravi
  -- -------------------------------------------------------------------------------------------
486
  ext_mem_b_access: process(clk_gen)
487
  begin
488
    if rising_edge(clk_gen) then
489
      -- control --
490
      ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge
491 2 zero_gravi
 
492 38 zero_gravi
      -- write access --
493
      if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access
494
        for i in 0 to 3 loop
495
          if (wb_mem_b.sel(i) = '1') then
496
            ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_b.wdata(7+i*8 downto 0+i*8);
497
          end if;
498
        end loop; -- i
499
      end if;
500 3 zero_gravi
 
501 38 zero_gravi
      -- read access --
502
      ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned
503
      -- virtual read and ack latency --
504
      if (ext_mem_b_latency_c > 1) then
505
        for i in 1 to ext_mem_b_latency_c-1 loop
506
          ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1);
507
          ext_mem_b.ack(i)   <= ext_mem_b.ack(i-1) and wb_mem_b.cyc;
508
        end loop;
509
      end if;
510
 
511
      -- bus output register --
512
      wb_mem_b.err <= '0';
513
      if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
514
        wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
515
        wb_mem_b.ack   <= '1';
516
      else
517
        wb_mem_b.rdata <= (others => '0');
518
        wb_mem_b.ack   <= '0';
519
      end if;
520
    end if;
521
  end process ext_mem_b_access;
522
 
523
 
524 39 zero_gravi
  -- Wishbone Memory C (simulated external IO) ----------------------------------------------
525
  -- -------------------------------------------------------------------------------------------
526
  ext_mem_c_access: process(clk_gen)
527
  begin
528
    if rising_edge(clk_gen) then
529
      -- control --
530
      ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge
531
 
532
      -- write access --
533
      if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access
534
        for i in 0 to 3 loop
535
          if (wb_mem_c.sel(i) = '1') then
536
            ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8);
537
          end if;
538
        end loop; -- i
539
      end if;
540
 
541
      -- read access --
542
      ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned
543
      -- virtual read and ack latency --
544
      if (ext_mem_c_latency_c > 1) then
545
        for i in 1 to ext_mem_c_latency_c-1 loop
546
          ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1);
547
          ext_mem_c.ack(i)   <= ext_mem_c.ack(i-1) and wb_mem_c.cyc;
548
        end loop;
549
      end if;
550
 
551
      -- error to simulate interrupted LOCKED/EXCLUSIVE bus access --
552
      wb_mem_c.err <= wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.lock and wb_mem_c.addr(2); -- locked access to odd word-addresses will fail
553
 
554
      -- bus output register --
555
      if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') then
556
        wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
557
        wb_mem_c.ack   <= '1';
558
      else
559
        wb_mem_c.rdata <= (others => '0');
560
        wb_mem_c.ack   <= '0';
561
      end if;
562
    end if;
563
  end process ext_mem_c_access;
564
 
565
 
566 40 zero_gravi
  -- Wishbone IRQ Triggers ------------------------------------------------------------------
567
  -- -------------------------------------------------------------------------------------------
568 45 zero_gravi
  irq_trigger: process(clk_gen)
569 40 zero_gravi
  begin
570
    if rising_edge(clk_gen) then
571 47 zero_gravi
      -- bus interface --
572
      wb_irq.rdata  <= (others => '0');
573 48 zero_gravi
      wb_irq.ack    <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel);
574 47 zero_gravi
      wb_irq.err    <= '0';
575
      -- trigger IRQ using CSR.MIE bit layout --
576
      msi_ring      <= '0';
577
      mei_ring      <= '0';
578
      soc_firq_ring <= (others => '0');
579 48 zero_gravi
      if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
580 47 zero_gravi
        msi_ring         <= wb_irq.wdata(03); -- machine software interrupt
581
        mei_ring         <= wb_irq.wdata(11); -- machine software interrupt
582 50 zero_gravi
        --
583
        soc_firq_ring(0) <= wb_irq.wdata(26); -- fast interrupt SoC channel 0 (-> FIRQ channel 10)
584
        soc_firq_ring(1) <= wb_irq.wdata(27); -- fast interrupt SoC channel 1 (-> FIRQ channel 11)
585
        soc_firq_ring(2) <= wb_irq.wdata(28); -- fast interrupt SoC channel 2 (-> FIRQ channel 12)
586
        soc_firq_ring(3) <= wb_irq.wdata(29); -- fast interrupt SoC channel 3 (-> FIRQ channel 13)
587
        soc_firq_ring(4) <= wb_irq.wdata(30); -- fast interrupt SoC channel 4 (-> FIRQ channel 14)
588
        soc_firq_ring(5) <= wb_irq.wdata(31); -- fast interrupt SoC channel 5 (-> FIRQ channel 15)
589 40 zero_gravi
      end if;
590
    end if;
591 45 zero_gravi
  end process irq_trigger;
592 40 zero_gravi
 
593
 
594 2 zero_gravi
end neorv32_tb_rtl;

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