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1 2 zero_gravi
-- #################################################################################################
2 59 zero_gravi
-- # << NEORV32 - Default Processor Testbench >>                                                   #
3 2 zero_gravi
-- # ********************************************************************************************* #
4 45 zero_gravi
-- # The processor is configured to use a maximum of functional units (for testing purpose).       #
5
-- # Use the "User Configuration" section to configure the testbench according to your needs.      #
6 59 zero_gravi
-- # See NEORV32 data sheet for more information.                                                  #
7 3 zero_gravi
-- # ********************************************************************************************* #
8 2 zero_gravi
-- # BSD 3-Clause License                                                                          #
9
-- #                                                                                               #
10 42 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
11 2 zero_gravi
-- #                                                                                               #
12
-- # Redistribution and use in source and binary forms, with or without modification, are          #
13
-- # permitted provided that the following conditions are met:                                     #
14
-- #                                                                                               #
15
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
16
-- #    conditions and the following disclaimer.                                                   #
17
-- #                                                                                               #
18
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
19
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
20
-- #    provided with the distribution.                                                            #
21
-- #                                                                                               #
22
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
23
-- #    endorse or promote products derived from this software without specific prior written      #
24
-- #    permission.                                                                                #
25
-- #                                                                                               #
26
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
27
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
28
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
29
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
30
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
31
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
32
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
33
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
34
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
35
-- # ********************************************************************************************* #
36
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
37
-- #################################################################################################
38
 
39 61 zero_gravi
library vunit_lib;
40
context vunit_lib.vunit_context;
41
context vunit_lib.com_context;
42
context vunit_lib.vc_context;
43
 
44 2 zero_gravi
library ieee;
45
use ieee.std_logic_1164.all;
46
use ieee.numeric_std.all;
47
use ieee.math_real.all;
48
 
49
library neorv32;
50
use neorv32.neorv32_package.all;
51 30 zero_gravi
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
52 2 zero_gravi
use std.textio.all;
53
 
54 61 zero_gravi
library osvvm;
55
use osvvm.RandomPkg.all;
56
 
57
use work.uart_rx_pkg.all;
58
 
59 2 zero_gravi
entity neorv32_tb is
60 61 zero_gravi
  generic (runner_cfg : string := runner_cfg_default;
61
           ci_mode : boolean := false);
62 2 zero_gravi
end neorv32_tb;
63
 
64
architecture neorv32_tb_rtl of neorv32_tb is
65
 
66
  -- User Configuration ---------------------------------------------------------------------
67
  -- -------------------------------------------------------------------------------------------
68 38 zero_gravi
  -- general --
69 61 zero_gravi
  constant ext_imem_c              : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A)
70
  constant ext_dmem_c              : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B)
71
  constant imem_size_c             : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A
72
  constant dmem_size_c             : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B
73
  constant f_clock_c               : natural := 100000000; -- main clock in Hz
74
  constant baud0_rate_c            : natural := 19200; -- simulation UART0 (primary UART) baud rate
75
  constant baud1_rate_c            : natural := 19200; -- simulation UART1 (secondary UART) baud rate
76 38 zero_gravi
  -- simulated external Wishbone memory A (can be used as external IMEM) --
77 61 zero_gravi
  constant ext_mem_a_base_addr_c   : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
78
  constant ext_mem_a_size_c        : natural := imem_size_c; -- wishbone memory size in bytes
79
  constant ext_mem_a_latency_c     : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
80 39 zero_gravi
  -- simulated external Wishbone memory B (can be used as external DMEM) --
81 61 zero_gravi
  constant ext_mem_b_base_addr_c   : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base)
82
  constant ext_mem_b_size_c        : natural := dmem_size_c; -- wishbone memory size in bytes
83
  constant ext_mem_b_latency_c     : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
84 56 zero_gravi
  -- simulated external Wishbone memory C (can be used to simulate external IO access) --
85 61 zero_gravi
  constant ext_mem_c_base_addr_c   : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
86
  constant ext_mem_c_size_c        : natural := 64; -- wishbone memory size in bytes
87
  constant ext_mem_c_latency_c     : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
88 47 zero_gravi
  -- simulation interrupt trigger --
89 61 zero_gravi
  constant irq_trigger_base_addr_c : std_ulogic_vector(31 downto 0) := x"FF000000";
90 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
91
 
92 38 zero_gravi
  -- internals - hands off! --
93 50 zero_gravi
  constant int_imem_c       : boolean := not ext_imem_c;
94
  constant int_dmem_c       : boolean := not ext_dmem_c;
95
  constant uart0_baud_val_c : real := real(f_clock_c) / real(baud0_rate_c);
96
  constant uart1_baud_val_c : real := real(f_clock_c) / real(baud1_rate_c);
97
  constant t_clock_c        : time := (1 sec) / f_clock_c;
98 38 zero_gravi
 
99 2 zero_gravi
  -- generators --
100
  signal clk_gen, rst_gen : std_ulogic := '0';
101
 
102 61 zero_gravi
  -- uart --
103
  signal uart0_txd : std_ulogic; -- local loop-back
104
  signal uart0_cts : std_ulogic; -- local loop-back
105
  signal uart1_txd : std_ulogic; -- local loop-back
106
  signal uart1_cts : std_ulogic; -- local loop-back
107 2 zero_gravi
 
108
  -- gpio --
109 61 zero_gravi
  signal gpio : std_ulogic_vector(63 downto 0);
110 2 zero_gravi
 
111
  -- twi --
112
  signal twi_scl, twi_sda : std_logic;
113
 
114
  -- spi --
115 40 zero_gravi
  signal spi_data : std_ulogic;
116 2 zero_gravi
 
117 40 zero_gravi
  -- irq --
118 64 zero_gravi
  signal msi_ring, mei_ring : std_ulogic;
119 40 zero_gravi
 
120 2 zero_gravi
  -- Wishbone bus --
121
  type wishbone_t is record
122
    addr  : std_ulogic_vector(31 downto 0); -- address
123
    wdata : std_ulogic_vector(31 downto 0); -- master write data
124
    rdata : std_ulogic_vector(31 downto 0); -- master read data
125
    we    : std_ulogic; -- write enable
126
    sel   : std_ulogic_vector(03 downto 0); -- byte enable
127
    stb   : std_ulogic; -- strobe
128
    cyc   : std_ulogic; -- valid cycle
129
    ack   : std_ulogic; -- transfer acknowledge
130
    err   : std_ulogic; -- transfer error
131 57 zero_gravi
    tag   : std_ulogic_vector(02 downto 0); -- request tag
132
    lock  : std_ulogic; -- exclusive access request
133 2 zero_gravi
  end record;
134 47 zero_gravi
  signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
135 2 zero_gravi
 
136 61 zero_gravi
  -- Wishbone access latency type --
137 38 zero_gravi
  type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
138 30 zero_gravi
 
139 53 zero_gravi
  -- exclusive access / reservation --
140
  signal ext_mem_c_atomic_reservation : std_ulogic := '0';
141
 
142 61 zero_gravi
  -- simulated external memory c (IO) --
143
  signal ext_ram_c : mem32_t(0 to ext_mem_c_size_c/4-1); -- uninitialized, used to simulate external IO
144 30 zero_gravi
 
145 61 zero_gravi
  -- simulated external memory bus feedback type --
146 38 zero_gravi
  type ext_mem_t is record
147
    rdata  : ext_mem_read_latency_t;
148 23 zero_gravi
    acc_en : std_ulogic;
149 38 zero_gravi
    ack    : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0);
150 23 zero_gravi
  end record;
151 39 zero_gravi
  signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t;
152 2 zero_gravi
 
153 61 zero_gravi
  -- stream link interface - local echo --
154
  signal slink_dat : sdata_8x32_t;
155
  signal slink_val : std_ulogic_vector(7 downto 0);
156
  signal slink_rdy : std_ulogic_vector(7 downto 0);
157
 
158
  signal slink_transmitter_dat, slink_receiver_dat : sdata_8x32_t;
159
  signal slink_transmitter_val, slink_receiver_val : std_ulogic_vector(7 downto 0);
160
  signal slink_transmitter_rdy, slink_receiver_rdy : std_ulogic_vector(7 downto 0);
161
 
162
  constant uart0_rx_logger : logger_t := get_logger("UART0.RX");
163
  constant uart1_rx_logger : logger_t := get_logger("UART1.RX");
164
  constant uart0_rx_handle : uart_rx_t := new_uart_rx(uart0_baud_val_c, uart0_rx_logger);
165
  constant uart1_rx_handle : uart_rx_t := new_uart_rx(uart1_baud_val_c, uart1_rx_logger);
166
 
167
  type axi_stream_master_vec_t is array(integer range <>) of axi_stream_master_t;
168
  type axi_stream_slave_vec_t is array(integer range <>) of axi_stream_slave_t;
169
 
170
  impure function init_slink_transmitters return axi_stream_master_vec_t is
171
    variable result : axi_stream_master_vec_t(slink_transmitter_val'range);
172
  begin
173
    for idx in result'range loop
174
      result(idx) := new_axi_stream_master(
175
        data_length => slink_transmitter_dat(idx)'length,
176
        stall_config => new_stall_config(0.05, 1, 10)
177
      );
178
    end loop;
179
 
180
    return result;
181
  end;
182
 
183
  impure function init_slink_receivers return axi_stream_slave_vec_t is
184
    variable result : axi_stream_slave_vec_t(slink_receiver_val'range);
185
  begin
186
    for idx in result'range loop
187
      result(idx) := new_axi_stream_slave(
188
        data_length => slink_receiver_dat(idx)'length,
189
        stall_config => new_stall_config(0.05, 1, 10)
190
      );
191
    end loop;
192
 
193
    return result;
194
  end;
195
 
196
  constant slink_transmitters : axi_stream_master_vec_t := init_slink_transmitters;
197
  constant slink_receivers : axi_stream_slave_vec_t := init_slink_receivers;
198
 
199 2 zero_gravi
begin
200 61 zero_gravi
  test_runner : process
201
    variable msg : msg_t;
202
    variable rnd : RandomPType;
203
    variable value : std_logic_vector(slink_transmitter_dat(0)'range);
204
  begin
205
    test_runner_setup(runner, runner_cfg);
206 2 zero_gravi
 
207 61 zero_gravi
    rnd.InitSeed(test_runner'path_name);
208
 
209
    -- Show passing checks for UART0 on the display (stdout)
210
    show(uart0_rx_logger, display_handler, pass);
211
    show(uart1_rx_logger, display_handler, pass);
212
 
213
    if ci_mode then
214
      check_uart(net, uart0_rx_handle, nul & nul);
215
    else
216
      check_uart(net, uart0_rx_handle, "Blinking LED demo program" & cr & lf);
217
    end if;
218
 
219
    if ci_mode then
220
      -- No need to send the full expectation in one big chunk
221
      check_uart(net, uart1_rx_handle, nul & nul);
222 63 zero_gravi
      check_uart(net, uart1_rx_handle, "0/46" & cr & lf);
223 61 zero_gravi
    end if;
224
 
225
    -- Apply some random data on each SLINK inputs and expect it to
226
    -- be echoed by the CPU. No blocking. Let the SLINK transmitters
227
    -- and receivers do this work in parallel.
228
    for idx in slink_transmitters'range loop
229
      for iter in 1 to 100 loop
230
        value := rnd.RandSlv(value'length);
231
 
232
        -- SLINK is AXI Stream compatible so the SLINK transmitters and
233
        -- and receivers are AXI Stream master and slave verification components (VCs).
234
        -- The full-featured AXI Stream verification component interface (VCI) is used
235
        -- but the AXI stream VCs also implements the basic stream VCI which also works
236
        -- for simple transactions like these. To use that interface for pushing data
237
        -- the AXI Steam VC must be "cast" to a basic stream VC using "as_stream"
238
        --
239
        -- push_stream(net, as_stream(slink_transmitters(idx)), value);
240
 
241
        push_axi_stream(net, slink_transmitters(idx), value);
242
        check_axi_stream(net, slink_receivers(idx), value, blocking => false);
243
      end loop;
244
    end loop;
245
 
246
    -- Wait until all expected data has been received
247
    --
248
    -- wait_until_idle can take the VC actor as argument but
249
    -- the more abstract view is that wait_until_idle is part
250
    -- of the sync VCI and to use it a VC must be cast
251
    -- to a sync VC
252
    wait_until_idle(net, as_sync(uart0_rx_handle));
253
    wait_until_idle(net, as_sync(uart1_rx_handle));
254
    for idx in slink_receivers'range loop
255
      wait_until_idle(net, as_sync(slink_receivers(idx)));
256
    end loop;
257
 
258
    -- Wait a bit more if some extra unexpected data is produced. If so,
259
    -- uart_rx will fail
260 63 zero_gravi
    wait for (20 * (1e9 / baud0_rate_c)) * ns;
261 61 zero_gravi
 
262
    test_runner_cleanup(runner);
263
  end process;
264
 
265
  -- In case we get stuck waiting there is a watchdog timeout to terminate and fail the
266
  -- testbench
267
  test_runner_watchdog(runner, 50 ms);
268
 
269 2 zero_gravi
  -- Clock/Reset Generator ------------------------------------------------------------------
270
  -- -------------------------------------------------------------------------------------------
271
  clk_gen <= not clk_gen after (t_clock_c/2);
272
  rst_gen <= '0', '1' after 60*(t_clock_c/2);
273
 
274
 
275 48 zero_gravi
  -- The Core of the Problem ----------------------------------------------------------------
276 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
277
  neorv32_top_inst: neorv32_top
278
  generic map (
279
    -- General --
280 38 zero_gravi
    CLOCK_FREQUENCY              => f_clock_c,     -- clock frequency of clk_i in Hz
281 49 zero_gravi
    HW_THREAD_ID                 => 0,             -- hardware thread id (hartid) (32-bit)
282 61 zero_gravi
    INT_BOOTLOADER_EN            => false,         -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
283 59 zero_gravi
    -- On-Chip Debugger (OCD) --
284
    ON_CHIP_DEBUGGER_EN          => true,          -- implement on-chip debugger
285 2 zero_gravi
    -- RISC-V CPU Extensions --
286 39 zero_gravi
    CPU_EXTENSION_RISCV_A        => true,          -- implement atomic extension?
287 8 zero_gravi
    CPU_EXTENSION_RISCV_C        => true,          -- implement compressed extension?
288
    CPU_EXTENSION_RISCV_E        => false,         -- implement embedded RF extension?
289
    CPU_EXTENSION_RISCV_M        => true,          -- implement muld/div extension?
290 15 zero_gravi
    CPU_EXTENSION_RISCV_U        => true,          -- implement user mode extension?
291 63 zero_gravi
    CPU_EXTENSION_RISCV_Zbb      => true,          -- implement basic bit-manipulation sub-extension?
292 55 zero_gravi
    CPU_EXTENSION_RISCV_Zfinx    => true,          -- implement 32-bit floating-point extension (using INT reg!)
293 8 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    => true,          -- implement CSR system?
294
    CPU_EXTENSION_RISCV_Zifencei => true,          -- implement instruction stream sync.?
295 19 zero_gravi
    -- Extension Options --
296
    FAST_MUL_EN                  => false,         -- use DSPs for M extension's multiplier
297 34 zero_gravi
    FAST_SHIFT_EN                => false,         -- use barrel shifter for shift operations
298 56 zero_gravi
    CPU_CNT_WIDTH                => 64,            -- total width of CPU cycle and instret counters (0..64)
299 15 zero_gravi
    -- Physical Memory Protection (PMP) --
300 64 zero_gravi
    PMP_NUM_REGIONS              => 8,             -- number of regions (0..64)
301 42 zero_gravi
    PMP_MIN_GRANULARITY          => 64*1024,       -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
302
    -- Hardware Performance Monitors (HPM) --
303 58 zero_gravi
    HPM_NUM_CNTS                 => 12,            -- number of implemented HPM counters (0..29)
304 60 zero_gravi
    HPM_CNT_WIDTH                => 40,            -- total size of HPM counters (0..64)
305 23 zero_gravi
    -- Internal Instruction memory --
306 44 zero_gravi
    MEM_INT_IMEM_EN              => int_imem_c ,   -- implement processor-internal instruction memory
307 38 zero_gravi
    MEM_INT_IMEM_SIZE            => imem_size_c,   -- size of processor-internal instruction memory in bytes
308 23 zero_gravi
    -- Internal Data memory --
309 44 zero_gravi
    MEM_INT_DMEM_EN              => int_dmem_c,    -- implement processor-internal data memory
310 39 zero_gravi
    MEM_INT_DMEM_SIZE            => dmem_size_c,   -- size of processor-internal data memory in bytes
311 41 zero_gravi
    -- Internal Cache memory --
312 61 zero_gravi
    ICACHE_EN                    => true,          -- implement instruction cache
313 41 zero_gravi
    ICACHE_NUM_BLOCKS            => 8,             -- i-cache: number of blocks (min 2), has to be a power of 2
314
    ICACHE_BLOCK_SIZE            => 64,            -- i-cache: block size in bytes (min 4), has to be a power of 2
315 45 zero_gravi
    ICACHE_ASSOCIATIVITY         => 2,             -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
316 23 zero_gravi
    -- External memory interface --
317 44 zero_gravi
    MEM_EXT_EN                   => true,          -- implement external memory bus interface?
318 57 zero_gravi
    MEM_EXT_TIMEOUT              => 255,           -- cycles after a pending bus access auto-terminates (0 = disabled)
319 61 zero_gravi
    -- Stream link interface --
320
    SLINK_NUM_TX                 => 8,             -- number of TX links (0..8)
321
    SLINK_NUM_RX                 => 8,             -- number of TX links (0..8)
322
    SLINK_TX_FIFO                => 4,             -- TX fifo depth, has to be a power of two
323
    SLINK_RX_FIFO                => 1,             -- RX fifo depth, has to be a power of two
324
    -- External Interrupts Controller (XIRQ) --
325
    XIRQ_NUM_CH                  => 32,            -- number of external IRQ channels (0..32)
326
    XIRQ_TRIGGER_TYPE            => (others => '1'), -- trigger type: 0=level, 1=edge
327
    XIRQ_TRIGGER_POLARITY        => (others => '1'), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge 
328 2 zero_gravi
    -- Processor peripherals --
329 44 zero_gravi
    IO_GPIO_EN                   => true,          -- implement general purpose input/output port unit (GPIO)?
330
    IO_MTIME_EN                  => true,          -- implement machine system timer (MTIME)?
331 50 zero_gravi
    IO_UART0_EN                  => true,          -- implement primary universal asynchronous receiver/transmitter (UART0)?
332
    IO_UART1_EN                  => true,          -- implement secondary universal asynchronous receiver/transmitter (UART1)?
333 44 zero_gravi
    IO_SPI_EN                    => true,          -- implement serial peripheral interface (SPI)?
334
    IO_TWI_EN                    => true,          -- implement two-wire interface (TWI)?
335 60 zero_gravi
    IO_PWM_NUM_CH                => 30,            -- number of PWM channels to implement (0..60); 0 = disabled
336 44 zero_gravi
    IO_WDT_EN                    => true,          -- implement watch dog timer (WDT)?
337
    IO_TRNG_EN                   => false,         -- trng cannot be simulated
338 47 zero_gravi
    IO_CFS_EN                    => true,          -- implement custom functions subsystem (CFS)?
339 49 zero_gravi
    IO_CFS_CONFIG                => (others => '0'), -- custom CFS configuration generic
340 52 zero_gravi
    IO_CFS_IN_SIZE               => 32,            -- size of CFS input conduit in bits
341
    IO_CFS_OUT_SIZE              => 32,            -- size of CFS output conduit in bits
342
    IO_NEOLED_EN                 => true           -- implement NeoPixel-compatible smart LED interface (NEOLED)?
343 2 zero_gravi
  )
344
  port map (
345
    -- Global control --
346 61 zero_gravi
    clk_i          => clk_gen,         -- global clock, rising edge
347
    rstn_i         => rst_gen,         -- global reset, low-active, async
348 59 zero_gravi
    -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
349 61 zero_gravi
    jtag_trst_i    => '1',             -- low-active TAP reset (optional)
350
    jtag_tck_i     => '0',             -- serial clock
351
    jtag_tdi_i     => '0',             -- serial data input
352
    jtag_tdo_o     => open,            -- serial data output
353
    jtag_tms_i     => '0',             -- mode select
354 49 zero_gravi
    -- Wishbone bus interface (available if MEM_EXT_EN = true) --
355 61 zero_gravi
    wb_tag_o       => wb_cpu.tag,      -- request tag
356
    wb_adr_o       => wb_cpu.addr,     -- address
357
    wb_dat_i       => wb_cpu.rdata,    -- read data
358
    wb_dat_o       => wb_cpu.wdata,    -- write data
359
    wb_we_o        => wb_cpu.we,       -- read/write
360
    wb_sel_o       => wb_cpu.sel,      -- byte enable
361
    wb_stb_o       => wb_cpu.stb,      -- strobe
362
    wb_cyc_o       => wb_cpu.cyc,      -- valid cycle
363
    wb_lock_o      => wb_cpu.lock,     -- exclusive access request
364
    wb_ack_i       => wb_cpu.ack,      -- transfer acknowledge
365
    wb_err_i       => wb_cpu.err,      -- transfer error
366 49 zero_gravi
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
367 61 zero_gravi
    fence_o        => open,            -- indicates an executed FENCE operation
368
    fencei_o       => open,            -- indicates an executed FENCEI operation
369
    -- TX stream interfaces (available if SLINK_NUM_TX > 0) --
370
    slink_tx_dat_o => slink_dat,       -- output data
371
    slink_tx_val_o => slink_val,       -- valid output
372
    slink_tx_rdy_i => slink_rdy,       -- ready to send
373
    -- RX stream interfaces (available if SLINK_NUM_RX > 0) --
374
    slink_rx_dat_i => slink_dat,       -- input data
375
    slink_rx_val_i => slink_val,       -- valid input
376
    slink_rx_rdy_o => slink_rdy,       -- ready to receive
377 49 zero_gravi
    -- GPIO (available if IO_GPIO_EN = true) --
378 61 zero_gravi
    gpio_o         => gpio,            -- parallel output
379
    gpio_i         => gpio,            -- parallel input
380 50 zero_gravi
    -- primary UART0 (available if IO_UART0_EN = true) --
381 61 zero_gravi
    uart0_txd_o    => uart0_txd,       -- UART0 send data
382
    uart0_rxd_i    => uart0_txd,       -- UART0 receive data
383
    uart0_rts_o    => uart0_cts,       -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
384
    uart0_cts_i    => uart0_cts,       -- hw flow control: UART0.TX allowed to transmit, low-active, optional
385 50 zero_gravi
    -- secondary UART1 (available if IO_UART1_EN = true) --
386 61 zero_gravi
    uart1_txd_o    => uart1_txd,       -- UART1 send data
387
    uart1_rxd_i    => uart1_txd,       -- UART1 receive data
388
    uart1_rts_o    => uart1_cts,       -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
389
    uart1_cts_i    => uart1_cts,       -- hw flow control: UART1.TX allowed to transmit, low-active, optional
390 49 zero_gravi
    -- SPI (available if IO_SPI_EN = true) --
391 61 zero_gravi
    spi_sck_o      => open,            -- SPI serial clock
392
    spi_sdo_o      => spi_data,        -- controller data out, peripheral data in
393
    spi_sdi_i      => spi_data,        -- controller data in, peripheral data out
394
    spi_csn_o      => open,            -- SPI CS
395 49 zero_gravi
    -- TWI (available if IO_TWI_EN = true) --
396 61 zero_gravi
    twi_sda_io     => twi_sda,         -- twi serial data line
397
    twi_scl_io     => twi_scl,         -- twi serial clock line
398 60 zero_gravi
    -- PWM (available if IO_PWM_NUM_CH > 0) --
399 61 zero_gravi
    pwm_o          => open,            -- pwm channels
400 47 zero_gravi
    -- Custom Functions Subsystem IO --
401 61 zero_gravi
    cfs_in_i       => (others => '0'), -- custom CFS inputs
402
    cfs_out_o      => open,            -- custom CFS outputs
403 52 zero_gravi
    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
404 61 zero_gravi
    neoled_o       => open,            -- async serial data line
405 59 zero_gravi
    -- System time --
406 61 zero_gravi
    mtime_i        => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false)
407
    mtime_o        => open,            -- current system time from int. MTIME (if IO_MTIME_EN = true)
408
    -- External platform interrupts (available if XIRQ_NUM_CH > 0) --
409
    xirq_i         => gpio(31 downto 0), -- IRQ channels
410
    -- CPU Interrupts --
411
    mtime_irq_i    => '0',             -- machine software interrupt, available if IO_MTIME_EN = false
412
    msw_irq_i      => msi_ring,        -- machine software interrupt
413
    mext_irq_i     => mei_ring         -- machine external interrupt
414 2 zero_gravi
  );
415
 
416 36 zero_gravi
  -- TWI termination (pull-ups) --
417 2 zero_gravi
  twi_scl <= 'H';
418
  twi_sda <= 'H';
419
 
420 61 zero_gravi
  uart0_checker: entity work.uart_rx
421
    generic map (uart0_rx_handle)
422
    port map (
423
      clk => clk_gen,
424
      uart_txd => uart0_txd);
425 2 zero_gravi
 
426 61 zero_gravi
  uart1_checker: entity work.uart_rx
427
    generic map (uart1_rx_handle)
428
    port map (
429
      clk => clk_gen,
430
      uart_txd => uart1_txd);
431 2 zero_gravi
 
432 61 zero_gravi
  slink_transmitters_gen: for idx in slink_transmitters'range generate
433
    slink_transmitter : entity vunit_lib.axi_stream_master
434
      generic map(
435
        master => slink_transmitters(idx)
436
      )
437
      port map(
438
        aclk => clk_gen,
439
        tvalid => slink_transmitter_val(idx),
440
        tready => slink_transmitter_rdy(idx),
441
        std_ulogic_vector(tdata) => slink_transmitter_dat(idx)
442
      );
443
  end generate;
444 2 zero_gravi
 
445 61 zero_gravi
  slink_receivers_gen: for idx in slink_receivers'range generate
446 50 zero_gravi
  begin
447 61 zero_gravi
    slink_receiver : entity vunit_lib.axi_stream_slave
448
      generic map(
449
        slave => slink_receivers(idx)
450
      )
451
      port map(
452
        aclk => clk_gen,
453
        tvalid => slink_receiver_val(idx),
454
        tready => slink_receiver_rdy(idx),
455
        tdata => std_logic_vector(slink_receiver_dat(idx))
456
      );
457
  end generate;
458 50 zero_gravi
 
459 61 zero_gravi
  -- TODO: connect these to the CPU SLINK interface once the
460
  -- loopback SW has been implemented
461
  temporary_connection : for idx in slink_transmitters'range generate
462
    slink_receiver_val(idx) <= slink_transmitter_val(idx);
463
    slink_transmitter_rdy(idx) <= slink_receiver_rdy(idx);
464
    slink_receiver_dat(idx) <= slink_transmitter_dat(idx);
465
  end generate;
466 50 zero_gravi
 
467
 
468 38 zero_gravi
  -- Wishbone Fabric ------------------------------------------------------------------------
469 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
470 38 zero_gravi
  -- CPU broadcast signals --
471
  wb_mem_a.addr  <= wb_cpu.addr;
472 39 zero_gravi
  wb_mem_a.wdata <= wb_cpu.wdata;
473
  wb_mem_a.we    <= wb_cpu.we;
474
  wb_mem_a.sel   <= wb_cpu.sel;
475
  wb_mem_a.tag   <= wb_cpu.tag;
476
  wb_mem_a.cyc   <= wb_cpu.cyc;
477
 
478 38 zero_gravi
  wb_mem_b.addr  <= wb_cpu.addr;
479
  wb_mem_b.wdata <= wb_cpu.wdata;
480
  wb_mem_b.we    <= wb_cpu.we;
481
  wb_mem_b.sel   <= wb_cpu.sel;
482
  wb_mem_b.tag   <= wb_cpu.tag;
483
  wb_mem_b.cyc   <= wb_cpu.cyc;
484 39 zero_gravi
 
485
  wb_mem_c.addr  <= wb_cpu.addr;
486
  wb_mem_c.wdata <= wb_cpu.wdata;
487
  wb_mem_c.we    <= wb_cpu.we;
488
  wb_mem_c.sel   <= wb_cpu.sel;
489
  wb_mem_c.tag   <= wb_cpu.tag;
490
  wb_mem_c.cyc   <= wb_cpu.cyc;
491
 
492 47 zero_gravi
  wb_irq.addr    <= wb_cpu.addr;
493
  wb_irq.wdata   <= wb_cpu.wdata;
494
  wb_irq.we      <= wb_cpu.we;
495
  wb_irq.sel     <= wb_cpu.sel;
496
  wb_irq.tag     <= wb_cpu.tag;
497
  wb_irq.cyc     <= wb_cpu.cyc;
498 40 zero_gravi
 
499 38 zero_gravi
  -- CPU read-back signals (no mux here since peripherals have "output gates") --
500 47 zero_gravi
  wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata;
501
  wb_cpu.ack   <= wb_mem_a.ack   or wb_mem_b.ack   or wb_mem_c.ack   or wb_irq.ack;
502
  wb_cpu.err   <= wb_mem_a.err   or wb_mem_b.err   or wb_mem_c.err   or wb_irq.err;
503 38 zero_gravi
 
504
  -- peripheral select via STROBE signal --
505
  wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
506
  wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
507 39 zero_gravi
  wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
508 61 zero_gravi
  wb_irq.stb   <= wb_cpu.stb when (wb_cpu.addr =  irq_trigger_base_addr_c) else '0';
509 38 zero_gravi
 
510
 
511 39 zero_gravi
  -- Wishbone Memory A (simulated external IMEM) --------------------------------------------
512 38 zero_gravi
  -- -------------------------------------------------------------------------------------------
513 61 zero_gravi
  generate_ext_imem:
514
  if ext_imem_c generate
515
    ext_mem_a_access: process(clk_gen)
516
      variable ext_ram_a : mem32_t(0 to ext_mem_a_size_c/4-1) := mem32_init_f(application_init_image, ext_mem_a_size_c/4); -- initialized, used to simulate external IMEM
517
    begin
518
      if rising_edge(clk_gen) then
519
        -- control --
520
        ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge
521 38 zero_gravi
 
522 61 zero_gravi
        -- write access --
523
        if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access
524
          for i in 0 to 3 loop
525
            if (wb_mem_a.sel(i) = '1') then
526
              ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_a.wdata(7+i*8 downto 0+i*8);
527
            end if;
528
          end loop; -- i
529
        end if;
530 38 zero_gravi
 
531 61 zero_gravi
        -- read access --
532
        ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned
533
        -- virtual read and ack latency --
534
        if (ext_mem_a_latency_c > 1) then
535
          for i in 1 to ext_mem_a_latency_c-1 loop
536
            ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1);
537
            ext_mem_a.ack(i)   <= ext_mem_a.ack(i-1) and wb_mem_a.cyc;
538
          end loop;
539
        end if;
540 38 zero_gravi
 
541 61 zero_gravi
        -- bus output register --
542
        wb_mem_a.err <= '0';
543 64 zero_gravi
        if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_a.cyc = '1') and (wb_mem_a.ack = '0') then
544 61 zero_gravi
          wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
545
          wb_mem_a.ack   <= '1';
546
        else
547
          wb_mem_a.rdata <= (others => '0');
548
          wb_mem_a.ack   <= '0';
549
        end if;
550 38 zero_gravi
      end if;
551 61 zero_gravi
    end process ext_mem_a_access;
552
  end generate;
553 2 zero_gravi
 
554 61 zero_gravi
  generate_ext_imem_false:
555
  if (ext_imem_c = false) generate
556
    wb_mem_a.rdata <= (others => '0');
557
    wb_mem_a.ack   <= '0';
558 62 zero_gravi
    wb_mem_a.err   <= '0';
559 61 zero_gravi
  end generate;
560 2 zero_gravi
 
561 61 zero_gravi
 
562 39 zero_gravi
  -- Wishbone Memory B (simulated external DMEM) --------------------------------------------
563 38 zero_gravi
  -- -------------------------------------------------------------------------------------------
564
  ext_mem_b_access: process(clk_gen)
565 61 zero_gravi
    variable ext_ram_b : mem32_t(0 to ext_mem_b_size_c/4-1) := (others => (others => '0')); -- zero, used to simulate external DMEM
566 38 zero_gravi
  begin
567
    if rising_edge(clk_gen) then
568
      -- control --
569
      ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge
570 2 zero_gravi
 
571 38 zero_gravi
      -- write access --
572
      if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access
573
        for i in 0 to 3 loop
574
          if (wb_mem_b.sel(i) = '1') then
575 61 zero_gravi
            ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_b.wdata(7+i*8 downto 0+i*8);
576 38 zero_gravi
          end if;
577
        end loop; -- i
578
      end if;
579 3 zero_gravi
 
580 38 zero_gravi
      -- read access --
581
      ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned
582
      -- virtual read and ack latency --
583
      if (ext_mem_b_latency_c > 1) then
584
        for i in 1 to ext_mem_b_latency_c-1 loop
585
          ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1);
586
          ext_mem_b.ack(i)   <= ext_mem_b.ack(i-1) and wb_mem_b.cyc;
587
        end loop;
588
      end if;
589
 
590
      -- bus output register --
591 57 zero_gravi
      wb_mem_b.err <= '0';
592 53 zero_gravi
      if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_b.ack = '0') then
593 38 zero_gravi
        wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
594
        wb_mem_b.ack   <= '1';
595
      else
596
        wb_mem_b.rdata <= (others => '0');
597
        wb_mem_b.ack   <= '0';
598
      end if;
599
    end if;
600
  end process ext_mem_b_access;
601
 
602
 
603 39 zero_gravi
  -- Wishbone Memory C (simulated external IO) ----------------------------------------------
604
  -- -------------------------------------------------------------------------------------------
605
  ext_mem_c_access: process(clk_gen)
606
  begin
607
    if rising_edge(clk_gen) then
608
      -- control --
609
      ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge
610
 
611
      -- write access --
612
      if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access
613
        for i in 0 to 3 loop
614
          if (wb_mem_c.sel(i) = '1') then
615
            ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8);
616
          end if;
617
        end loop; -- i
618
      end if;
619
 
620
      -- read access --
621
      ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned
622
      -- virtual read and ack latency --
623
      if (ext_mem_c_latency_c > 1) then
624
        for i in 1 to ext_mem_c_latency_c-1 loop
625
          ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1);
626
          ext_mem_c.ack(i)   <= ext_mem_c.ack(i-1) and wb_mem_c.cyc;
627
        end loop;
628
      end if;
629
 
630 53 zero_gravi
      -- EXCLUSIVE bus access -----------------------------------------------------
631
      -- -----------------------------------------------------------------------------
632 57 zero_gravi
      -- Since there is only one CPU in this design, the exclusive access reservation in THIS memory CANNOT fail.
633
      -- However, this memory module is used to simulated failing LR/SC accesses.
634
      if ((wb_mem_c.cyc and wb_mem_c.stb) = '1') then -- valid access
635
        ext_mem_c_atomic_reservation <= wb_mem_c.lock; -- make reservation
636 53 zero_gravi
      end if;
637
      -- -----------------------------------------------------------------------------
638 39 zero_gravi
 
639
      -- bus output register --
640 53 zero_gravi
      if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') and (wb_mem_c.ack = '0') then
641 39 zero_gravi
        wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
642
        wb_mem_c.ack   <= '1';
643 57 zero_gravi
        wb_mem_c.err   <= ext_mem_c_atomic_reservation; -- issue a bus error if there is an exclusive access request
644 39 zero_gravi
      else
645
        wb_mem_c.rdata <= (others => '0');
646
        wb_mem_c.ack   <= '0';
647 57 zero_gravi
        wb_mem_c.err   <= '0';
648 39 zero_gravi
      end if;
649
    end if;
650
  end process ext_mem_c_access;
651
 
652
 
653 40 zero_gravi
  -- Wishbone IRQ Triggers ------------------------------------------------------------------
654
  -- -------------------------------------------------------------------------------------------
655 64 zero_gravi
  irq_trigger: process(rst_gen, clk_gen)
656 40 zero_gravi
  begin
657 64 zero_gravi
    if (rst_gen = '0') then
658
      msi_ring <= '0';
659
      mei_ring <= '0';
660
    elsif rising_edge(clk_gen) then
661 47 zero_gravi
      -- bus interface --
662 57 zero_gravi
      wb_irq.rdata <= (others => '0');
663 60 zero_gravi
      wb_irq.ack   <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel);
664 57 zero_gravi
      wb_irq.err   <= '0';
665 64 zero_gravi
      -- trigger RISC-V platform IRQs --
666 60 zero_gravi
      if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel)) = '1') then
667 61 zero_gravi
        msi_ring <= wb_irq.wdata(03); -- machine software interrupt
668
        mei_ring <= wb_irq.wdata(11); -- machine software interrupt
669 40 zero_gravi
      end if;
670
    end if;
671 45 zero_gravi
  end process irq_trigger;
672 40 zero_gravi
 
673
 
674 2 zero_gravi
end neorv32_tb_rtl;

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