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[/] [neorv32/] [trunk/] [sim/] [neorv32_tb.vhd] - Blame information for rev 8

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1 2 zero_gravi
-- #################################################################################################
2 3 zero_gravi
-- # << NEORV32 - Simple Testbench >>                                                              #
3 2 zero_gravi
-- # ********************************************************************************************* #
4 3 zero_gravi
-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o       #
5
-- # signals. The received chars are shown in the simulator console and also written to a file     #
6
-- # ("neorv32.testbench_uart.out").                                                               #
7
-- # Futhermore, this testbench provides a simple RAM connected to the external Wishbone bus.      #
8
-- # ********************************************************************************************* #
9 2 zero_gravi
-- # BSD 3-Clause License                                                                          #
10
-- #                                                                                               #
11
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
12
-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
14
-- # permitted provided that the following conditions are met:                                     #
15
-- #                                                                                               #
16
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
17
-- #    conditions and the following disclaimer.                                                   #
18
-- #                                                                                               #
19
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
20
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
21
-- #    provided with the distribution.                                                            #
22
-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
24
-- #    endorse or promote products derived from this software without specific prior written      #
25
-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
28
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
29
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
30
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
31
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
32
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
33
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
34
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
35
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
37
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
38
-- #################################################################################################
39
 
40
library ieee;
41
use ieee.std_logic_1164.all;
42
use ieee.numeric_std.all;
43
use ieee.math_real.all;
44
 
45
library neorv32;
46
use neorv32.neorv32_package.all;
47
use std.textio.all;
48
 
49
entity neorv32_tb is
50
end neorv32_tb;
51
 
52
architecture neorv32_tb_rtl of neorv32_tb is
53
 
54
  -- User Configuration ---------------------------------------------------------------------
55
  -- -------------------------------------------------------------------------------------------
56
  constant t_clock_c          : time := 10 ns; -- main clock period
57
  constant f_clock_c          : real := 100000000.0; -- main clock in Hz
58
  constant f_clock_nat_c      : natural := 100000000; -- main clock in Hz
59
  constant baud_rate_c        : real := 19200.0; -- standard UART baudrate
60 3 zero_gravi
  constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address
61 2 zero_gravi
  constant wb_mem_size_c      : natural := 256; -- wishbone memory size in bytes
62
  -- -------------------------------------------------------------------------------------------
63
 
64 3 zero_gravi
  -- text.io --
65
  file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
66 2 zero_gravi
 
67
  -- internal configuration --
68
  constant baud_val_c : real    := f_clock_c / baud_rate_c;
69
  constant f_clk_c    : natural := natural(f_clock_c);
70
 
71
  -- generators --
72
  signal clk_gen, rst_gen : std_ulogic := '0';
73
 
74
  -- simulation uart receiver --
75
  signal uart_txd         : std_ulogic;
76
  signal uart_rx_sync     : std_ulogic_vector(04 downto 0) := (others => '1');
77
  signal uart_rx_busy     : std_ulogic := '0';
78
  signal uart_rx_sreg     : std_ulogic_vector(08 downto 0) := (others => '0');
79
  signal uart_rx_baud_cnt : real;
80
  signal uart_rx_bitcnt   : natural;
81
 
82
  -- gpio --
83
  signal gpio : std_ulogic_vector(15 downto 0);
84
 
85
  -- twi --
86
  signal twi_scl, twi_sda : std_logic;
87
 
88
  -- spi --
89
  signal spi_data : std_logic;
90
 
91
  -- Wishbone bus --
92
  type wishbone_t is record
93
    addr  : std_ulogic_vector(31 downto 0); -- address
94
    wdata : std_ulogic_vector(31 downto 0); -- master write data
95
    rdata : std_ulogic_vector(31 downto 0); -- master read data
96
    we    : std_ulogic; -- write enable
97
    sel   : std_ulogic_vector(03 downto 0); -- byte enable
98
    stb   : std_ulogic; -- strobe
99
    cyc   : std_ulogic; -- valid cycle
100
    ack   : std_ulogic; -- transfer acknowledge
101
    err   : std_ulogic; -- transfer error
102
  end record;
103
  signal wb_cpu : wishbone_t;
104
 
105
 
106 3 zero_gravi
  -- Wishbone memory, SimCom --
107 2 zero_gravi
  type wb_mem_file_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
108 3 zero_gravi
  signal wb_mem_file  : wb_mem_file_t := (others => (others => '0'));
109
  signal rb_en        : std_ulogic;
110
  signal r_data       : std_ulogic_vector(31 downto 0);
111
  signal wb_acc_en    : std_ulogic;
112
  signal wb_mem_rdata : std_ulogic_vector(31 downto 0);
113
  signal wb_mem_ack   : std_ulogic;
114 2 zero_gravi
 
115
begin
116
 
117
  -- Clock/Reset Generator ------------------------------------------------------------------
118
  -- -------------------------------------------------------------------------------------------
119
  clk_gen <= not clk_gen after (t_clock_c/2);
120
  rst_gen <= '0', '1' after 60*(t_clock_c/2);
121
 
122
 
123
  -- CPU Core -------------------------------------------------------------------------------
124
  -- -------------------------------------------------------------------------------------------
125
  neorv32_top_inst: neorv32_top
126
  generic map (
127
    -- General --
128 8 zero_gravi
    CLOCK_FREQUENCY              => f_clock_nat_c, -- clock frequency of clk_i in Hz
129
    HART_ID                      => x"00000000",   -- custom hardware thread ID
130
    BOOTLOADER_USE               => false,         -- implement processor-internal bootloader?
131
    CSR_COUNTERS_USE             => true,          -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
132 2 zero_gravi
    -- RISC-V CPU Extensions --
133 8 zero_gravi
    CPU_EXTENSION_RISCV_C        => true,          -- implement compressed extension?
134
    CPU_EXTENSION_RISCV_E        => false,         -- implement embedded RF extension?
135
    CPU_EXTENSION_RISCV_M        => true,          -- implement muld/div extension?
136
    CPU_EXTENSION_RISCV_Zicsr    => true,          -- implement CSR system?
137
    CPU_EXTENSION_RISCV_Zifencei => true,          -- implement instruction stream sync.?
138 2 zero_gravi
    -- Memory configuration: Instruction memory --
139 8 zero_gravi
    MEM_ISPACE_BASE              => x"00000000",   -- base address of instruction memory space
140
    MEM_ISPACE_SIZE              => 16*1024,       -- total size of instruction memory space in byte
141
    MEM_INT_IMEM_USE             => true,          -- implement processor-internal instruction memory
142
    MEM_INT_IMEM_SIZE            => 16*1024,       -- size of processor-internal instruction memory in bytes
143
    MEM_INT_IMEM_ROM             => false,         -- implement processor-internal instruction memory as ROM
144 2 zero_gravi
    -- Memory configuration: Data memory --
145 8 zero_gravi
    MEM_DSPACE_BASE              => x"80000000",   -- base address of data memory space
146
    MEM_DSPACE_SIZE              => 8*1024,        -- total size of data memory space in byte
147
    MEM_INT_DMEM_USE             => true,          -- implement processor-internal data memory
148
    MEM_INT_DMEM_SIZE            => 8*1024,        -- size of processor-internal data memory in bytes
149 2 zero_gravi
    -- Memory configuration: External memory interface --
150 8 zero_gravi
    MEM_EXT_USE                  => true,          -- implement external memory bus interface?
151
    MEM_EXT_REG_STAGES           => 2,             -- number of interface register stages (0,1,2)
152
    MEM_EXT_TIMEOUT              => 15,            -- cycles after which a valid bus access will timeout
153 2 zero_gravi
    -- Processor peripherals --
154 8 zero_gravi
    IO_GPIO_USE                  => true,          -- implement general purpose input/output port unit (GPIO)?
155
    IO_MTIME_USE                 => true,          -- implement machine system timer (MTIME)?
156
    IO_UART_USE                  => true,          -- implement universal asynchronous receiver/transmitter (UART)?
157
    IO_SPI_USE                   => true,          -- implement serial peripheral interface (SPI)?
158
    IO_TWI_USE                   => true,          -- implement two-wire interface (TWI)?
159
    IO_PWM_USE                   => true,          -- implement pulse-width modulation unit (PWM)?
160
    IO_WDT_USE                   => true,          -- implement watch dog timer (WDT)?
161
    IO_CLIC_USE                  => true,          -- implement core local interrupt controller (CLIC)?
162
    IO_TRNG_USE                  => false,         -- implement true random number generator (TRNG)?
163
    IO_DEVNULL_USE               => true           -- implement dummy device (DEVNULL)?
164 2 zero_gravi
  )
165
  port map (
166
    -- Global control --
167
    clk_i      => clk_gen,         -- global clock, rising edge
168
    rstn_i     => rst_gen,         -- global reset, low-active, async
169
    -- Wishbone bus interface --
170
    wb_adr_o   => wb_cpu.addr,     -- address
171
    wb_dat_i   => wb_cpu.rdata,    -- read data
172
    wb_dat_o   => wb_cpu.wdata,    -- write data
173
    wb_we_o    => wb_cpu.we,       -- read/write
174
    wb_sel_o   => wb_cpu.sel,      -- byte enable
175
    wb_stb_o   => wb_cpu.stb,      -- strobe
176
    wb_cyc_o   => wb_cpu.cyc,      -- valid cycle
177
    wb_ack_i   => wb_cpu.ack,      -- transfer acknowledge
178
    wb_err_i   => wb_cpu.err,      -- transfer error
179
    -- GPIO --
180
    gpio_o     => gpio,            -- parallel output
181
    gpio_i     => gpio,            -- parallel input
182
    -- UART --
183
    uart_txd_o => uart_txd,        -- UART send data
184
    uart_rxd_i => uart_txd,        -- UART receive data
185
    -- SPI --
186 6 zero_gravi
    spi_sck_o  => open,            -- SPI serial clock
187
    spi_sdo_o  => spi_data,        -- controller data out, peripheral data in
188
    spi_sdi_i  => spi_data,        -- controller data in, peripheral data out
189 2 zero_gravi
    spi_csn_o  => open,            -- SPI CS
190
    -- TWI --
191
    twi_sda_io => twi_sda,         -- twi serial data line
192
    twi_scl_io => twi_scl,         -- twi serial clock line
193
    -- PWM --
194
    pwm_o      => open,            -- pwm channels
195
    -- Interrupts --
196
    ext_irq_i  => (others => '0'), -- external interrupt request
197
    ext_ack_o  => open             -- external interrupt request acknowledge
198
  );
199
 
200 3 zero_gravi
  -- TWI termination --
201 2 zero_gravi
  twi_scl <= 'H';
202
  twi_sda <= 'H';
203
 
204 3 zero_gravi
  -- Wishbone read-back --
205
  wb_cpu.rdata <= wb_mem_rdata;
206
  wb_cpu.ack   <= wb_mem_ack;
207
  wb_cpu.err   <= '0';
208 2 zero_gravi
 
209 3 zero_gravi
 
210 2 zero_gravi
  -- Console UART Receiver ------------------------------------------------------------------
211
  -- -------------------------------------------------------------------------------------------
212
  uart_rx_console: process(clk_gen)
213 3 zero_gravi
    variable i : integer;
214
    variable l : line;
215 2 zero_gravi
  begin
216
    -- "UART" --
217
    if rising_edge(clk_gen) then
218
      -- synchronizer --
219
      uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
220
      -- arbiter --
221
      if (uart_rx_busy = '0') then -- idle
222
        uart_rx_busy     <= '0';
223
        uart_rx_baud_cnt <= round(0.5 * baud_val_c);
224
        uart_rx_bitcnt   <= 9;
225
        if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
226
          uart_rx_busy <= '1';
227
        end if;
228
      else
229
        if (uart_rx_baud_cnt = 0.0) then
230
          if (uart_rx_bitcnt = 1) then
231
            uart_rx_baud_cnt <= round(0.5 * baud_val_c);
232
          else
233
            uart_rx_baud_cnt <= round(baud_val_c);
234
          end if;
235
          if (uart_rx_bitcnt = 0) then
236
            uart_rx_busy <= '0'; -- done
237
            i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
238
 
239 3 zero_gravi
            if (i < 32) or (i > 32+95) then -- printable char?
240
              report "SIM_UART TX: (" & integer'image(i) & ")"; -- print code
241 2 zero_gravi
            else
242 3 zero_gravi
              report "SIM_UART TX: " & character'val(i); -- print ASCII
243 2 zero_gravi
            end if;
244
 
245
            if (i = 10) then -- Linux line break
246 3 zero_gravi
              writeline(file_uart_tx_out, l);
247 2 zero_gravi
            elsif (i /= 13) then -- Remove additional carriage return
248 3 zero_gravi
              write(l, character'val(i));
249 2 zero_gravi
            end if;
250
          else
251
            uart_rx_sreg   <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
252
            uart_rx_bitcnt <= uart_rx_bitcnt - 1;
253
          end if;
254
        else
255
          uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
256
        end if;
257
      end if;
258
    end if;
259
  end process uart_rx_console;
260
 
261
 
262
  -- Wishbone Memory ------------------------------------------------------------------------
263
  -- -------------------------------------------------------------------------------------------
264
    wb_mem_file_access: process(clk_gen)
265
    begin
266
      if rising_edge(clk_gen) then
267
        rb_en <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en and (not wb_cpu.we); -- read-back control
268 3 zero_gravi
        wb_mem_ack <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en; -- wishbone acknowledge
269 2 zero_gravi
        if ((wb_cpu.cyc and wb_cpu.stb and wb_acc_en and wb_cpu.we) = '1') then -- valid write access
270
          for i in 0 to 3 loop
271
            if (wb_cpu.sel(i) = '1') then
272
              wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8);
273
            end if;
274
          end loop; -- i
275
        end if;
276
        r_data <= wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
277
      end if;
278
    end process wb_mem_file_access;
279
 
280
  -- wb mem access --
281
  wb_acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
282
 
283
  -- output gate --
284 3 zero_gravi
  wb_mem_rdata <= r_data when (rb_en = '1') else (others=> '0');
285 2 zero_gravi
 
286 3 zero_gravi
 
287 2 zero_gravi
end neorv32_tb_rtl;

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