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1 64 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - Default Processor Testbench >>                                                   #
3
-- # ********************************************************************************************* #
4
-- # The processor is configured to use a maximum of functional units (for testing purpose).       #
5
-- # Use the "User Configuration" section to configure the testbench according to your needs.      #
6
-- # See NEORV32 data sheet for more information.                                                  #
7
-- # ********************************************************************************************* #
8
-- # BSD 3-Clause License                                                                          #
9
-- #                                                                                               #
10
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
11
-- #                                                                                               #
12
-- # Redistribution and use in source and binary forms, with or without modification, are          #
13
-- # permitted provided that the following conditions are met:                                     #
14
-- #                                                                                               #
15
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
16
-- #    conditions and the following disclaimer.                                                   #
17
-- #                                                                                               #
18
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
19
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
20
-- #    provided with the distribution.                                                            #
21
-- #                                                                                               #
22
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
23
-- #    endorse or promote products derived from this software without specific prior written      #
24
-- #    permission.                                                                                #
25
-- #                                                                                               #
26
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
27
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
28
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
29
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
30
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
31
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
32
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
33
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
34
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
35
-- # ********************************************************************************************* #
36
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
37
-- #################################################################################################
38
 
39
library ieee;
40
use ieee.std_logic_1164.all;
41
use ieee.numeric_std.all;
42
use ieee.math_real.all;
43
 
44
library neorv32;
45
use neorv32.neorv32_package.all;
46
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
47
use std.textio.all;
48
 
49
entity neorv32_tb_simple is
50
  generic (
51
    CPU_EXTENSION_RISCV_A        : boolean := true;
52 66 zero_gravi
    CPU_EXTENSION_RISCV_B        : boolean := true;
53 64 zero_gravi
    CPU_EXTENSION_RISCV_C        : boolean := true;
54
    CPU_EXTENSION_RISCV_E        : boolean := false;
55
    CPU_EXTENSION_RISCV_M        : boolean := true;
56
    CPU_EXTENSION_RISCV_U        : boolean := true;
57
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;
58
    CPU_EXTENSION_RISCV_Zifencei : boolean := true;
59
    EXT_IMEM_C                   : boolean := false;   -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A)
60
    MEM_INT_IMEM_SIZE            : natural := 16*1024  -- size in bytes of processor-internal IMEM / external mem A
61
  );
62
end neorv32_tb_simple;
63
 
64
architecture neorv32_tb_simple_rtl of neorv32_tb_simple is
65
 
66
  -- User Configuration ---------------------------------------------------------------------
67
  -- -------------------------------------------------------------------------------------------
68
  -- general --
69
  constant ext_dmem_c              : boolean := false;     -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B)
70
  constant dmem_size_c             : natural := 8*1024;    -- size in bytes of processor-internal DMEM / external mem B
71
  constant f_clock_c               : natural := 100000000; -- main clock in Hz
72
  constant baud0_rate_c            : natural := 19200; -- simulation UART0 (primary UART) baud rate
73
  constant baud1_rate_c            : natural := 19200; -- simulation UART1 (secondary UART) baud rate
74
  -- simulated external Wishbone memory A (can be used as external IMEM) --
75
  constant ext_mem_a_base_addr_c   : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
76
  constant ext_mem_a_size_c        : natural := MEM_INT_IMEM_SIZE; -- wishbone memory size in bytes
77
  constant ext_mem_a_latency_c     : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
78
  -- simulated external Wishbone memory B (can be used as external DMEM) --
79
  constant ext_mem_b_base_addr_c   : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base)
80
  constant ext_mem_b_size_c        : natural := dmem_size_c; -- wishbone memory size in bytes
81
  constant ext_mem_b_latency_c     : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
82
  -- simulated external Wishbone memory C (can be used to simulate external IO access) --
83
  constant ext_mem_c_base_addr_c   : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
84
  constant ext_mem_c_size_c        : natural := 64; -- wishbone memory size in bytes
85
  constant ext_mem_c_latency_c     : natural := 3;  -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
86
  -- simulation interrupt trigger --
87
  constant irq_trigger_base_addr_c : std_ulogic_vector(31 downto 0) := x"FF000000";
88
  -- -------------------------------------------------------------------------------------------
89
 
90
  -- internals - hands off! --
91
  constant int_imem_c       : boolean := not EXT_IMEM_C;
92
  constant int_dmem_c       : boolean := not ext_dmem_c;
93
  constant uart0_baud_val_c : real := real(f_clock_c) / real(baud0_rate_c);
94
  constant uart1_baud_val_c : real := real(f_clock_c) / real(baud1_rate_c);
95
  constant t_clock_c        : time := (1 sec) / f_clock_c;
96
 
97
  -- generators --
98
  signal clk_gen, rst_gen : std_ulogic := '0';
99
 
100
  -- text.io --
101
  file file_uart0_tx_out : text open write_mode is "neorv32.testbench_uart0.out";
102
 
103
  -- uart --
104
  signal uart0_txd : std_ulogic; -- local loop-back
105
  signal uart0_cts : std_ulogic; -- local loop-back
106
  signal uart1_txd : std_ulogic; -- local loop-back
107
  signal uart1_cts : std_ulogic; -- local loop-back
108
 
109
  -- gpio --
110
  signal gpio : std_ulogic_vector(63 downto 0);
111
 
112
  -- twi --
113
  signal twi_scl, twi_sda : std_logic;
114
 
115
  -- spi --
116
  signal spi_data : std_ulogic;
117
 
118
  -- irq --
119
  signal msi_ring, mei_ring : std_ulogic;
120
 
121
  -- Wishbone bus --
122
  type wishbone_t is record
123
    addr  : std_ulogic_vector(31 downto 0); -- address
124
    wdata : std_ulogic_vector(31 downto 0); -- master write data
125
    rdata : std_ulogic_vector(31 downto 0); -- master read data
126
    we    : std_ulogic; -- write enable
127
    sel   : std_ulogic_vector(03 downto 0); -- byte enable
128
    stb   : std_ulogic; -- strobe
129
    cyc   : std_ulogic; -- valid cycle
130
    ack   : std_ulogic; -- transfer acknowledge
131
    err   : std_ulogic; -- transfer error
132
    tag   : std_ulogic_vector(02 downto 0); -- request tag
133
    lock  : std_ulogic; -- exclusive access request
134
  end record;
135
  signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
136
 
137
  -- Wishbone access latency type --
138
  type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
139
 
140
  -- exclusive access / reservation --
141
  signal ext_mem_c_atomic_reservation : std_ulogic := '0';
142
 
143
  -- simulated external memory c (IO) --
144
  signal ext_ram_c : mem32_t(0 to ext_mem_c_size_c/4-1); -- uninitialized, used to simulate external IO
145
 
146
  -- simulated external memory bus feedback type --
147
  type ext_mem_t is record
148
    rdata  : ext_mem_read_latency_t;
149
    acc_en : std_ulogic;
150
    ack    : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0);
151
  end record;
152
  signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t;
153
 
154
  -- stream link interface - local echo --
155
  signal slink_dat : sdata_8x32_t;
156
  signal slink_val : std_ulogic_vector(7 downto 0);
157
  signal slink_rdy : std_ulogic_vector(7 downto 0);
158
 
159
begin
160
 
161
  -- Clock/Reset Generator ------------------------------------------------------------------
162
  -- -------------------------------------------------------------------------------------------
163
  clk_gen <= not clk_gen after (t_clock_c/2);
164
  rst_gen <= '0', '1' after 60*(t_clock_c/2);
165
 
166
 
167
  -- The Core of the Problem ----------------------------------------------------------------
168
  -- -------------------------------------------------------------------------------------------
169
  neorv32_top_inst: neorv32_top
170
  generic map (
171
    -- General --
172
    CLOCK_FREQUENCY              => f_clock_c,     -- clock frequency of clk_i in Hz
173
    HW_THREAD_ID                 => 0,             -- hardware thread id (hartid) (32-bit)
174
    INT_BOOTLOADER_EN            => false,         -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
175
    -- On-Chip Debugger (OCD) --
176
    ON_CHIP_DEBUGGER_EN          => true,          -- implement on-chip debugger
177
    -- RISC-V CPU Extensions --
178
    CPU_EXTENSION_RISCV_A        => CPU_EXTENSION_RISCV_A,  -- implement atomic extension?
179 66 zero_gravi
    CPU_EXTENSION_RISCV_B        => CPU_EXTENSION_RISCV_B,  -- implement bit-manipulation extension?
180 64 zero_gravi
    CPU_EXTENSION_RISCV_C        => CPU_EXTENSION_RISCV_C,  -- implement compressed extension?
181
    CPU_EXTENSION_RISCV_E        => CPU_EXTENSION_RISCV_E,  -- implement embedded RF extension?
182
    CPU_EXTENSION_RISCV_M        => CPU_EXTENSION_RISCV_M,  -- implement muld/div extension?
183
    CPU_EXTENSION_RISCV_U        => CPU_EXTENSION_RISCV_U,  -- implement user mode extension?
184
    CPU_EXTENSION_RISCV_Zfinx    => true,          -- implement 32-bit floating-point extension (using INT reg!)
185
    CPU_EXTENSION_RISCV_Zicsr    => CPU_EXTENSION_RISCV_Zicsr,     -- implement CSR system?
186 66 zero_gravi
    CPU_EXTENSION_RISCV_Zicntr   => true,          -- implement base counters?
187
    CPU_EXTENSION_RISCV_Zihpm    => true,          -- implement hardware performance monitors?
188 64 zero_gravi
    CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei,  -- implement instruction stream sync.?
189
    CPU_EXTENSION_RISCV_Zmmul    => false,         -- implement multiply-only M sub-extension?
190
    -- Extension Options --
191
    FAST_MUL_EN                  => false,         -- use DSPs for M extension's multiplier
192
    FAST_SHIFT_EN                => false,         -- use barrel shifter for shift operations
193
    CPU_CNT_WIDTH                => 64,            -- total width of CPU cycle and instret counters (0..64)
194
    -- Physical Memory Protection (PMP) --
195
    PMP_NUM_REGIONS              => 8,             -- number of regions (0..64)
196
    PMP_MIN_GRANULARITY          => 64*1024,       -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
197
    -- Hardware Performance Monitors (HPM) --
198
    HPM_NUM_CNTS                 => 12,            -- number of implemented HPM counters (0..29)
199
    HPM_CNT_WIDTH                => 40,            -- total size of HPM counters (0..64)
200
    -- Internal Instruction memory --
201
    MEM_INT_IMEM_EN              => int_imem_c ,   -- implement processor-internal instruction memory
202
    MEM_INT_IMEM_SIZE            => MEM_INT_IMEM_SIZE,   -- size of processor-internal instruction memory in bytes
203
    -- Internal Data memory --
204
    MEM_INT_DMEM_EN              => int_dmem_c,    -- implement processor-internal data memory
205
    MEM_INT_DMEM_SIZE            => dmem_size_c,   -- size of processor-internal data memory in bytes
206
    -- Internal Cache memory --
207
    ICACHE_EN                    => true,          -- implement instruction cache
208
    ICACHE_NUM_BLOCKS            => 8,             -- i-cache: number of blocks (min 2), has to be a power of 2
209
    ICACHE_BLOCK_SIZE            => 64,            -- i-cache: block size in bytes (min 4), has to be a power of 2
210
    ICACHE_ASSOCIATIVITY         => 2,             -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
211
    -- External memory interface --
212
    MEM_EXT_EN                   => true,          -- implement external memory bus interface?
213
    MEM_EXT_TIMEOUT              => 255,           -- cycles after a pending bus access auto-terminates (0 = disabled)
214
    -- Stream link interface --
215
    SLINK_NUM_TX                 => 8,             -- number of TX links (0..8)
216
    SLINK_NUM_RX                 => 8,             -- number of TX links (0..8)
217
    SLINK_TX_FIFO                => 4,             -- TX fifo depth, has to be a power of two
218
    SLINK_RX_FIFO                => 1,             -- RX fifo depth, has to be a power of two
219
    -- External Interrupts Controller (XIRQ) --
220
    XIRQ_NUM_CH                  => 32,            -- number of external IRQ channels (0..32)
221
    XIRQ_TRIGGER_TYPE            => (others => '1'), -- trigger type: 0=level, 1=edge
222
    XIRQ_TRIGGER_POLARITY        => (others => '1'), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
223
    -- Processor peripherals --
224
    IO_GPIO_EN                   => true,          -- implement general purpose input/output port unit (GPIO)?
225
    IO_MTIME_EN                  => true,          -- implement machine system timer (MTIME)?
226
    IO_UART0_EN                  => true,          -- implement primary universal asynchronous receiver/transmitter (UART0)?
227 65 zero_gravi
    IO_UART0_RX_FIFO             => 32,            -- RX fifo depth, has to be a power of two, min 1
228
    IO_UART0_TX_FIFO             => 32,            -- TX fifo depth, has to be a power of two, min 1
229 64 zero_gravi
    IO_UART1_EN                  => true,          -- implement secondary universal asynchronous receiver/transmitter (UART1)?
230 65 zero_gravi
    IO_UART1_RX_FIFO             => 1,             -- RX fifo depth, has to be a power of two, min 1
231
    IO_UART1_TX_FIFO             => 1,             -- TX fifo depth, has to be a power of two, min 1
232 64 zero_gravi
    IO_SPI_EN                    => true,          -- implement serial peripheral interface (SPI)?
233
    IO_TWI_EN                    => true,          -- implement two-wire interface (TWI)?
234
    IO_PWM_NUM_CH                => 30,            -- number of PWM channels to implement (0..60); 0 = disabled
235
    IO_WDT_EN                    => true,          -- implement watch dog timer (WDT)?
236
    IO_TRNG_EN                   => false,         -- trng cannot be simulated
237
    IO_CFS_EN                    => true,          -- implement custom functions subsystem (CFS)?
238
    IO_CFS_CONFIG                => (others => '0'), -- custom CFS configuration generic
239
    IO_CFS_IN_SIZE               => 32,            -- size of CFS input conduit in bits
240
    IO_CFS_OUT_SIZE              => 32,            -- size of CFS output conduit in bits
241 65 zero_gravi
    IO_NEOLED_EN                 => true,          -- implement NeoPixel-compatible smart LED interface (NEOLED)?
242 67 zero_gravi
    IO_NEOLED_TX_FIFO            => 8,             -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
243
    IO_GPTMR_EN                  => true           -- implement general purpose timer (GPTMR)?
244 64 zero_gravi
  )
245
  port map (
246
    -- Global control --
247
    clk_i          => clk_gen,         -- global clock, rising edge
248
    rstn_i         => rst_gen,         -- global reset, low-active, async
249
    -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
250
    jtag_trst_i    => '1',             -- low-active TAP reset (optional)
251
    jtag_tck_i     => '0',             -- serial clock
252
    jtag_tdi_i     => '0',             -- serial data input
253
    jtag_tdo_o     => open,            -- serial data output
254
    jtag_tms_i     => '0',             -- mode select
255
    -- Wishbone bus interface (available if MEM_EXT_EN = true) --
256
    wb_tag_o       => wb_cpu.tag,      -- request tag
257
    wb_adr_o       => wb_cpu.addr,     -- address
258
    wb_dat_i       => wb_cpu.rdata,    -- read data
259
    wb_dat_o       => wb_cpu.wdata,    -- write data
260
    wb_we_o        => wb_cpu.we,       -- read/write
261
    wb_sel_o       => wb_cpu.sel,      -- byte enable
262
    wb_stb_o       => wb_cpu.stb,      -- strobe
263
    wb_cyc_o       => wb_cpu.cyc,      -- valid cycle
264
    wb_lock_o      => wb_cpu.lock,     -- exclusive access request
265
    wb_ack_i       => wb_cpu.ack,      -- transfer acknowledge
266
    wb_err_i       => wb_cpu.err,      -- transfer error
267
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
268
    fence_o        => open,            -- indicates an executed FENCE operation
269
    fencei_o       => open,            -- indicates an executed FENCEI operation
270
    -- TX stream interfaces (available if SLINK_NUM_TX > 0) --
271
    slink_tx_dat_o => slink_dat,       -- output data
272
    slink_tx_val_o => slink_val,       -- valid output
273
    slink_tx_rdy_i => slink_rdy,       -- ready to send
274
    -- RX stream interfaces (available if SLINK_NUM_RX > 0) --
275
    slink_rx_dat_i => slink_dat,       -- input data
276
    slink_rx_val_i => slink_val,       -- valid input
277
    slink_rx_rdy_o => slink_rdy,       -- ready to receive
278
    -- GPIO (available if IO_GPIO_EN = true) --
279
    gpio_o         => gpio,            -- parallel output
280
    gpio_i         => gpio,            -- parallel input
281
    -- primary UART0 (available if IO_UART0_EN = true) --
282
    uart0_txd_o    => uart0_txd,       -- UART0 send data
283
    uart0_rxd_i    => uart0_txd,       -- UART0 receive data
284
    uart0_rts_o    => uart0_cts,       -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
285
    uart0_cts_i    => uart0_cts,       -- hw flow control: UART0.TX allowed to transmit, low-active, optional
286
    -- secondary UART1 (available if IO_UART1_EN = true) --
287
    uart1_txd_o    => uart1_txd,       -- UART1 send data
288
    uart1_rxd_i    => uart1_txd,       -- UART1 receive data
289
    uart1_rts_o    => uart1_cts,       -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
290
    uart1_cts_i    => uart1_cts,       -- hw flow control: UART1.TX allowed to transmit, low-active, optional
291
    -- SPI (available if IO_SPI_EN = true) --
292
    spi_sck_o      => open,            -- SPI serial clock
293
    spi_sdo_o      => spi_data,        -- controller data out, peripheral data in
294
    spi_sdi_i      => spi_data,        -- controller data in, peripheral data out
295
    spi_csn_o      => open,            -- SPI CS
296
    -- TWI (available if IO_TWI_EN = true) --
297
    twi_sda_io     => twi_sda,         -- twi serial data line
298
    twi_scl_io     => twi_scl,         -- twi serial clock line
299
    -- PWM (available if IO_PWM_NUM_CH > 0) --
300
    pwm_o          => open,            -- pwm channels
301
    -- Custom Functions Subsystem IO --
302
    cfs_in_i       => (others => '0'), -- custom CFS inputs
303
    cfs_out_o      => open,            -- custom CFS outputs
304
    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
305
    neoled_o       => open,            -- async serial data line
306
    -- System time --
307
    mtime_i        => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false)
308
    mtime_o        => open,            -- current system time from int. MTIME (if IO_MTIME_EN = true)
309
    -- External platform interrupts (available if XIRQ_NUM_CH > 0) --
310
    xirq_i         => gpio(31 downto 0), -- IRQ channels
311
    -- CPU Interrupts --
312
    mtime_irq_i    => '0',             -- machine software interrupt, available if IO_MTIME_EN = false
313
    msw_irq_i      => msi_ring,        -- machine software interrupt
314
    mext_irq_i     => mei_ring         -- machine external interrupt
315
  );
316
 
317
  -- TWI termination (pull-ups) --
318
  twi_scl <= 'H';
319
  twi_sda <= 'H';
320
 
321
 
322
  -- UART Simulation Receiver ---------------------------------------------------------------
323
  -- -------------------------------------------------------------------------------------------
324
  uart0_checker: entity work.uart_rx_simple
325
  generic map (
326
    name => "uart0",
327
    uart_baud_val_c => uart0_baud_val_c
328
  )
329
  port map (
330
    clk => clk_gen,
331
    uart_txd => uart0_txd
332
  );
333
 
334
  uart1_checker: entity work.uart_rx_simple
335
  generic map (
336
    name => "uart1",
337
    uart_baud_val_c => uart1_baud_val_c
338
  )
339
  port map (
340
    clk => clk_gen,
341
    uart_txd => uart1_txd
342
  );
343
 
344
 
345
  -- Wishbone Fabric ------------------------------------------------------------------------
346
  -- -------------------------------------------------------------------------------------------
347
  -- CPU broadcast signals --
348
  wb_mem_a.addr  <= wb_cpu.addr;
349
  wb_mem_a.wdata <= wb_cpu.wdata;
350
  wb_mem_a.we    <= wb_cpu.we;
351
  wb_mem_a.sel   <= wb_cpu.sel;
352
  wb_mem_a.tag   <= wb_cpu.tag;
353
  wb_mem_a.cyc   <= wb_cpu.cyc;
354
 
355
  wb_mem_b.addr  <= wb_cpu.addr;
356
  wb_mem_b.wdata <= wb_cpu.wdata;
357
  wb_mem_b.we    <= wb_cpu.we;
358
  wb_mem_b.sel   <= wb_cpu.sel;
359
  wb_mem_b.tag   <= wb_cpu.tag;
360
  wb_mem_b.cyc   <= wb_cpu.cyc;
361
 
362
  wb_mem_c.addr  <= wb_cpu.addr;
363
  wb_mem_c.wdata <= wb_cpu.wdata;
364
  wb_mem_c.we    <= wb_cpu.we;
365
  wb_mem_c.sel   <= wb_cpu.sel;
366
  wb_mem_c.tag   <= wb_cpu.tag;
367
  wb_mem_c.cyc   <= wb_cpu.cyc;
368
 
369
  wb_irq.addr    <= wb_cpu.addr;
370
  wb_irq.wdata   <= wb_cpu.wdata;
371
  wb_irq.we      <= wb_cpu.we;
372
  wb_irq.sel     <= wb_cpu.sel;
373
  wb_irq.tag     <= wb_cpu.tag;
374
  wb_irq.cyc     <= wb_cpu.cyc;
375
 
376
  -- CPU read-back signals (no mux here since peripherals have "output gates") --
377
  wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata;
378
  wb_cpu.ack   <= wb_mem_a.ack   or wb_mem_b.ack   or wb_mem_c.ack   or wb_irq.ack;
379
  wb_cpu.err   <= wb_mem_a.err   or wb_mem_b.err   or wb_mem_c.err   or wb_irq.err;
380
 
381
  -- peripheral select via STROBE signal --
382
  wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
383
  wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
384
  wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
385
  wb_irq.stb   <= wb_cpu.stb when (wb_cpu.addr =  irq_trigger_base_addr_c) else '0';
386
 
387
 
388
  -- Wishbone Memory A (simulated external IMEM) --------------------------------------------
389
  -- -------------------------------------------------------------------------------------------
390
  generate_ext_imem:
391
  if (EXT_IMEM_C = true) generate
392
    ext_mem_a_access: process(clk_gen)
393
      variable ext_ram_a : mem32_t(0 to ext_mem_a_size_c/4-1) := mem32_init_f(application_init_image, ext_mem_a_size_c/4); -- initialized, used to simulate external IMEM
394
    begin
395
      if rising_edge(clk_gen) then
396
        -- control --
397
        ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge
398
 
399
        -- write access --
400
        if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access
401
          for i in 0 to 3 loop
402
            if (wb_mem_a.sel(i) = '1') then
403
              ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_a.wdata(7+i*8 downto 0+i*8);
404
            end if;
405
          end loop; -- i
406
        end if;
407
 
408
        -- read access --
409
        ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned
410
        -- virtual read and ack latency --
411
        if (ext_mem_a_latency_c > 1) then
412
          for i in 1 to ext_mem_a_latency_c-1 loop
413
            ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1);
414
            ext_mem_a.ack(i)   <= ext_mem_a.ack(i-1) and wb_mem_a.cyc;
415
          end loop;
416
        end if;
417
 
418
        -- bus output register --
419
        wb_mem_a.err <= '0';
420
        if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_a.cyc = '1') and (wb_mem_a.ack = '0') then
421
          wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
422
          wb_mem_a.ack   <= '1';
423
        else
424
          wb_mem_a.rdata <= (others => '0');
425
          wb_mem_a.ack   <= '0';
426
        end if;
427
      end if;
428
    end process ext_mem_a_access;
429
  end generate;
430
 
431
  generate_ext_imem_false:
432
  if (EXT_IMEM_C = false) generate
433
    wb_mem_a.rdata <= (others => '0');
434
    wb_mem_a.ack   <= '0';
435
    wb_mem_a.err   <= '0';
436
  end generate;
437
 
438
 
439
  -- Wishbone Memory B (simulated external DMEM) --------------------------------------------
440
  -- -------------------------------------------------------------------------------------------
441
  ext_mem_b_access: process(clk_gen)
442
    variable ext_ram_b : mem32_t(0 to ext_mem_b_size_c/4-1) := (others => (others => '0')); -- zero, used to simulate external DMEM
443
  begin
444
    if rising_edge(clk_gen) then
445
      -- control --
446
      ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge
447
 
448
      -- write access --
449
      if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access
450
        for i in 0 to 3 loop
451
          if (wb_mem_b.sel(i) = '1') then
452
            ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_b.wdata(7+i*8 downto 0+i*8);
453
          end if;
454
        end loop; -- i
455
      end if;
456
 
457
      -- read access --
458
      ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned
459
      -- virtual read and ack latency --
460
      if (ext_mem_b_latency_c > 1) then
461
        for i in 1 to ext_mem_b_latency_c-1 loop
462
          ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1);
463
          ext_mem_b.ack(i)   <= ext_mem_b.ack(i-1) and wb_mem_b.cyc;
464
        end loop;
465
      end if;
466
 
467
      -- bus output register --
468
      wb_mem_b.err <= '0';
469
      if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_b.ack = '0') then
470
        wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
471
        wb_mem_b.ack   <= '1';
472
      else
473
        wb_mem_b.rdata <= (others => '0');
474
        wb_mem_b.ack   <= '0';
475
      end if;
476
    end if;
477
  end process ext_mem_b_access;
478
 
479
 
480
  -- Wishbone Memory C (simulated external IO) ----------------------------------------------
481
  -- -------------------------------------------------------------------------------------------
482
  ext_mem_c_access: process(clk_gen)
483
  begin
484
    if rising_edge(clk_gen) then
485
      -- control --
486
      ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge
487
 
488
      -- write access --
489
      if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access
490
        for i in 0 to 3 loop
491
          if (wb_mem_c.sel(i) = '1') then
492
            ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8);
493
          end if;
494
        end loop; -- i
495
      end if;
496
 
497
      -- read access --
498
      ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned
499
      -- virtual read and ack latency --
500
      if (ext_mem_c_latency_c > 1) then
501
        for i in 1 to ext_mem_c_latency_c-1 loop
502
          ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1);
503
          ext_mem_c.ack(i)   <= ext_mem_c.ack(i-1) and wb_mem_c.cyc;
504
        end loop;
505
      end if;
506
 
507
      -- EXCLUSIVE bus access -----------------------------------------------------
508
      -- -----------------------------------------------------------------------------
509
      -- Since there is only one CPU in this design, the exclusive access reservation in THIS memory CANNOT fail.
510
      -- However, this memory module is used to simulated failing LR/SC accesses.
511
      if ((wb_mem_c.cyc and wb_mem_c.stb) = '1') then -- valid access
512
        ext_mem_c_atomic_reservation <= wb_mem_c.lock; -- make reservation
513
      end if;
514
      -- -----------------------------------------------------------------------------
515
 
516
      -- bus output register --
517
      if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') and (wb_mem_c.ack = '0') then
518
        wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
519
        wb_mem_c.ack   <= '1';
520
        wb_mem_c.err   <= ext_mem_c_atomic_reservation; -- issue a bus error if there is an exclusive access request
521
      else
522
        wb_mem_c.rdata <= (others => '0');
523
        wb_mem_c.ack   <= '0';
524
        wb_mem_c.err   <= '0';
525
      end if;
526
    end if;
527
  end process ext_mem_c_access;
528
 
529
 
530
  -- Wishbone IRQ Triggers ------------------------------------------------------------------
531
  -- -------------------------------------------------------------------------------------------
532
  irq_trigger: process(rst_gen, clk_gen)
533
  begin
534
    if (rst_gen = '0') then
535
      msi_ring <= '0';
536
      mei_ring <= '0';
537
    elsif rising_edge(clk_gen) then
538
      -- bus interface --
539
      wb_irq.rdata <= (others => '0');
540
      wb_irq.ack   <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel);
541
      wb_irq.err   <= '0';
542
      -- trigger RISC-V platform IRQs --
543
      if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel)) = '1') then
544
        msi_ring <= wb_irq.wdata(03); -- machine software interrupt
545
        mei_ring <= wb_irq.wdata(11); -- machine software interrupt
546
      end if;
547
    end if;
548
  end process irq_trigger;
549
 
550
 
551
end neorv32_tb_simple_rtl;

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