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[/] [neorv32/] [trunk/] [sw/] [bootloader/] [bootloader.c] - Blame information for rev 23

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1 2 zero_gravi
// #################################################################################################
2
// # << NEORV32 - Bootloader >>                                                                    #
3
// # ********************************************************************************************* #
4
// # THE BOOTLOADER SHOULD BE COMPILED USING THE BASE ISA ONLY (rv32i or rv32e)!                   #
5
// # ********************************************************************************************* #
6
// # Boot from (internal) instruction memory, UART or SPI Flash.                                   #
7
// #                                                                                               #
8
// # UART configuration: 8N1 at 19200 baud                                                         #
9
// # Boot Flash: 8-bit SPI, 24-bit addresses (like Micron N25Q032A) @ neorv32.spi_csn_o(0)         #
10
// # neorv32.gpio_o(0) is used as high-active status LED.                                          #
11
// #                                                                                               #
12
// # Auto boot sequence after timeout:                                                             #
13
// #  -> Try booting from SPI flash at spi_csn_o(0).                                               #
14
// #  -> Permanently light up status led and freeze if SPI flash booting attempt fails.            #
15
// # ********************************************************************************************* #
16
// # BSD 3-Clause License                                                                          #
17
// #                                                                                               #
18
// # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
19
// #                                                                                               #
20
// # Redistribution and use in source and binary forms, with or without modification, are          #
21
// # permitted provided that the following conditions are met:                                     #
22
// #                                                                                               #
23
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
24
// #    conditions and the following disclaimer.                                                   #
25
// #                                                                                               #
26
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
27
// #    conditions and the following disclaimer in the documentation and/or other materials        #
28
// #    provided with the distribution.                                                            #
29
// #                                                                                               #
30
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
31
// #    endorse or promote products derived from this software without specific prior written      #
32
// #    permission.                                                                                #
33
// #                                                                                               #
34
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
35
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
36
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
37
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
38
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
39
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
40
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
41
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
42
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
43
// # ********************************************************************************************* #
44
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
45
// #################################################################################################
46
 
47
 
48
/**********************************************************************//**
49
 * @file bootloader.c
50
 * @author Stephan Nolting
51
 * @brief Default NEORV32 bootloader. Compile only for rv32i or rv32e (better).
52
 **************************************************************************/
53
 
54
// Libraries
55
#include <stdint.h>
56
#include <neorv32.h>
57
 
58
 
59
/**********************************************************************//**
60
 * @name User configuration
61
 **************************************************************************/
62
/**@{*/
63
/** UART BAUD rate */
64
#define BAUD_RATE              (19200)
65
/** Time until the auto-boot sequence starts (in seconds) */
66 9 zero_gravi
#define AUTOBOOT_TIMEOUT       8
67 22 zero_gravi
/** Set to 0 to disable bootloader status LED */
68
#define STATUS_LED_EN          (1)
69
/** Bootloader status LED at GPIO output port */
70 2 zero_gravi
#define STATUS_LED             (0)
71
/** SPI flash boot image base address */
72 11 zero_gravi
#define SPI_FLASH_BOOT_ADR     (0x00800000)
73 2 zero_gravi
/** SPI flash chip select at spi_csn_o */
74
#define SPI_FLASH_CS           (0)
75
/** Default SPI flash clock prescaler for serial peripheral interface */
76
#define SPI_FLASH_CLK_PRSC     (CLK_PRSC_8)
77
/** SPI flash sector size in bytes */
78
#define SPI_FLASH_SECTOR_SIZE  (64*1024)
79
/**@}*/
80
 
81
 
82
/**********************************************************************//**
83
  Executable stream source select
84
 **************************************************************************/
85
enum EXE_STREAM_SOURCE {
86
  EXE_STREAM_UART  = 0, /**< Get executable via UART */
87
  EXE_STREAM_FLASH = 1  /**< Get executable via SPI flash */
88
};
89
 
90
 
91
/**********************************************************************//**
92
 * Error codes
93
 **************************************************************************/
94
enum ERROR_CODES {
95
  ERROR_SIGNATURE = 0, /**< 0: Wrong signature in executable */
96
  ERROR_SIZE      = 1, /**< 1: Insufficient instruction memory capacity */
97
  ERROR_CHECKSUM  = 2, /**< 2: Checksum error in executable */
98
  ERROR_FLASH     = 3, /**< 3: SPI flash access error */
99
  ERROR_ROM       = 4, /**< 4: Instruction memory is marked as read-only */
100
  ERROR_SYSTEM    = 5  /**< 5: System exception */
101
};
102
 
103
 
104
/**********************************************************************//**
105
 * SPI flash commands
106
 **************************************************************************/
107
enum SPI_FLASH_CMD {
108
  SPI_FLASH_CMD_PAGE_PROGRAM = 0x02, /**< Program page */
109
  SPI_FLASH_CMD_READ         = 0x03, /**< Read data */
110
  SPI_FLASH_CMD_READ_STATUS  = 0x05, /**< Get status register */
111
  SPI_FLASH_CMD_WRITE_ENABLE = 0x06, /**< Allow write access */
112
  SPI_FLASH_CMD_READ_ID      = 0x9E, /**< Read manufacturer ID */
113
  SPI_FLASH_CMD_SECTOR_ERASE = 0xD8  /**< Erase complete sector */
114
};
115
 
116
 
117
/**********************************************************************//**
118
 * NEORV32 executable
119
 **************************************************************************/
120
enum NEORV32_EXECUTABLE {
121
  EXE_OFFSET_SIGNATURE =  0, /**< Offset in bytes from start to signature (32-bit) */
122
  EXE_OFFSET_SIZE      =  4, /**< Offset in bytes from start to size (32-bit) */
123
  EXE_OFFSET_CHECKSUM  =  8, /**< Offset in bytes from start to checksum (32-bit) */
124
  EXE_OFFSET_DATA      = 12, /**< Offset in bytes from start to data (32-bit) */
125
};
126
 
127
 
128
/**********************************************************************//**
129
 * Valid executable identification signature.
130
 **************************************************************************/
131
#define EXE_SIGNATURE 0x4788CAFE
132
 
133
 
134
/**********************************************************************//**
135
 * String output helper macros.
136
 **************************************************************************/
137
/**@{*/
138
/* Actual define-to-string helper */
139
#define xstr(a) str(a)
140
/* Internal helper macro */
141
#define str(a) #a
142
/**@}*/
143
 
144
 
145 22 zero_gravi
/**********************************************************************//**
146
 * This global variable keeps the size of the available executable in bytes.
147
 * If =0 no executable is available (yet).
148
 **************************************************************************/
149
uint32_t exe_available = 0;
150
 
151
 
152 2 zero_gravi
// Function prototypes
153 22 zero_gravi
void __attribute__((__interrupt__)) bootloader_trap_handler(void);
154 2 zero_gravi
void print_help(void);
155
void start_app(void);
156
void get_exe(int src);
157
void save_exe(void);
158
uint32_t get_exe_word(int src, uint32_t addr);
159
void system_error(uint8_t err_code);
160
void print_hex_word(uint32_t num);
161
 
162
// SPI flash access
163
uint8_t spi_flash_read_byte(uint32_t addr);
164
void spi_flash_write_byte(uint32_t addr, uint8_t wdata);
165
void spi_flash_write_word(uint32_t addr, uint32_t wdata);
166
void spi_flash_erase_sector(uint32_t addr);
167
uint8_t spi_flash_read_status(void);
168
uint8_t spi_flash_read_1st_id(void);
169 4 zero_gravi
void spi_flash_write_enable(void);
170
void spi_flash_write_addr(uint32_t addr);
171 2 zero_gravi
 
172
 
173
/**********************************************************************//**
174
 * Bootloader main.
175
 **************************************************************************/
176
int main(void) {
177
 
178
  // ------------------------------------------------
179
  // Processor hardware initialization
180 22 zero_gravi
  // - all IO devices are reset and disabled by the crt0 code
181 2 zero_gravi
  // ------------------------------------------------
182
 
183
  // get clock speed (in Hz)
184 12 zero_gravi
  uint32_t clock_speed = SYSINFO_CLK;
185 2 zero_gravi
 
186
  // init SPI for 8-bit, clock-mode 0, MSB-first, no interrupt
187
  if (clock_speed < 40000000) {
188
    neorv32_spi_setup(SPI_FLASH_CLK_PRSC, 0, 0, 0, 0);
189
  }
190
  else {
191
    neorv32_spi_setup(CLK_PRSC_128, 0, 0, 0, 0);
192
  }
193
 
194
  // init UART (no interrupts)
195
  neorv32_uart_setup(BAUD_RATE, 0, 0);
196
 
197
  // Configure machine system timer interrupt for ~2Hz
198
  neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (clock_speed/4));
199
 
200 22 zero_gravi
  // confiure trap handler (bare-metal, no neorv32 rte available)
201
  neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&bootloader_trap_handler));
202
 
203 2 zero_gravi
  neorv32_cpu_csr_write(CSR_MIE, 1 << CPU_MIE_MTIE); // activate MTIME IRQ source
204
  neorv32_cpu_eint(); // enable global interrupts
205
 
206 22 zero_gravi
  if (STATUS_LED_EN == 1) {
207
    // activate status LED, clear all others
208
    neorv32_gpio_port_set(1 << STATUS_LED);
209
  }
210 2 zero_gravi
 
211 22 zero_gravi
  // global variable to executable size; 0 means there is no exe available
212
  exe_available = 0;
213 2 zero_gravi
 
214
 
215
  // ------------------------------------------------
216
  // Show bootloader intro and system info
217
  // ------------------------------------------------
218
  neorv32_uart_print("\n\n\n\n<< NEORV32 Bootloader >>\n\n"
219
                     "BLDV: "__DATE__"\nHWV:  ");
220 12 zero_gravi
  neorv32_rte_print_hw_version();
221 2 zero_gravi
  neorv32_uart_print("\nCLK:  ");
222 12 zero_gravi
  print_hex_word(SYSINFO_CLK);
223
  neorv32_uart_print(" Hz\nUSER: ");
224
  print_hex_word(SYSINFO_USER_CODE);
225 6 zero_gravi
  neorv32_uart_print("\nMISA: ");
226 2 zero_gravi
  print_hex_word(neorv32_cpu_csr_read(CSR_MISA));
227
  neorv32_uart_print("\nCONF: ");
228 12 zero_gravi
  print_hex_word(SYSINFO_FEATURES);
229 2 zero_gravi
  neorv32_uart_print("\nIMEM: ");
230 23 zero_gravi
  print_hex_word(SYSINFO_IMEM_SIZE);
231 2 zero_gravi
  neorv32_uart_print(" bytes @ ");
232 12 zero_gravi
  print_hex_word(SYSINFO_ISPACE_BASE);
233 2 zero_gravi
  neorv32_uart_print("\nDMEM: ");
234 23 zero_gravi
  print_hex_word(SYSINFO_DMEM_SIZE);
235 2 zero_gravi
  neorv32_uart_print(" bytes @ ");
236 12 zero_gravi
  print_hex_word(SYSINFO_DSPACE_BASE);
237 2 zero_gravi
 
238
 
239
  // ------------------------------------------------
240
  // Auto boot sequence
241
  // ------------------------------------------------
242
  neorv32_uart_print("\n\nAutoboot in "xstr(AUTOBOOT_TIMEOUT)"s. Press key to abort.\n");
243
 
244 13 zero_gravi
  uint64_t timeout_time = neorv32_mtime_get_time() + (uint64_t)(AUTOBOOT_TIMEOUT * clock_speed);
245
 
246 22 zero_gravi
  while ((UART_DATA & (1 << UART_DATA_AVAIL)) == 0) { // wait for any key to be pressed
247 2 zero_gravi
 
248
    if (neorv32_mtime_get_time() >= timeout_time) { // timeout? start auto boot sequence
249
      get_exe(EXE_STREAM_FLASH); // try loading from spi flash
250
      neorv32_uart_print("\n");
251
      start_app();
252
    }
253
  }
254
  neorv32_uart_print("Aborted.\n\n");
255
  print_help();
256
 
257
 
258
  // ------------------------------------------------
259
  // Bootloader console
260
  // ------------------------------------------------
261
  while (1) {
262
 
263
    neorv32_uart_print("\nCMD:> ");
264
    char c = neorv32_uart_getc();
265
    neorv32_uart_putc(c); // echo
266
    neorv32_uart_print("\n");
267
 
268
    if (c == 'r') { // restart bootloader
269 12 zero_gravi
      neorv32_cpu_dint(); // disable global interrupts
270 22 zero_gravi
      asm volatile ("li t0, %[input_i]; jr t0" :  : [input_i] "i" (BOOTLOADER_BASE_ADDRESS)); // jump to beginning of boot ROM
271 12 zero_gravi
      while(1); // just for the compiler
272 2 zero_gravi
    }
273
    else if (c == 'h') { // help menu
274
      print_help();
275
    }
276
    else if (c == 'u') { // get executable via UART
277
      get_exe(EXE_STREAM_UART);
278
    }
279
    else if (c == 's') { // program EEPROM from RAM
280
      save_exe();
281
    }
282
    else if (c == 'l') { // get executable from flash
283
      get_exe(EXE_STREAM_FLASH);
284
    }
285
    else if (c == 'e') { // start application program
286
      start_app();
287
    }
288 22 zero_gravi
    else if (c == '?') {
289 2 zero_gravi
      neorv32_uart_print("by Stephan Nolting");
290
    }
291
    else { // unknown command
292
      neorv32_uart_print("Invalid CMD");
293
    }
294
  }
295
 
296 12 zero_gravi
  return 0; // bootloader should never return
297 2 zero_gravi
}
298
 
299
 
300
/**********************************************************************//**
301
 * Print help menu.
302
 **************************************************************************/
303
void print_help(void) {
304
 
305
  neorv32_uart_print("Available CMDs:\n"
306
                     " h: Help\n"
307
                     " r: Restart\n"
308
                     " u: Upload\n"
309
                     " s: Store to flash\n"
310
                     " l: Load from flash\n"
311
                     " e: Execute");
312
}
313
 
314
 
315
/**********************************************************************//**
316
 * Start application program at the beginning of instruction space.
317
 **************************************************************************/
318
void start_app(void) {
319
 
320 4 zero_gravi
  // executable available?
321 22 zero_gravi
  if (exe_available == 0) {
322 4 zero_gravi
    neorv32_uart_print("No executable available.");
323
    return;
324
  }
325
 
326 23 zero_gravi
  // no need to shut down or reset the used peripherals
327
  // no need to disable interrupt sources
328 2 zero_gravi
  // -> this will be done by application's crt0
329
 
330 23 zero_gravi
  // deactivate global IRQs
331 2 zero_gravi
  neorv32_cpu_dint();
332
 
333
  neorv32_uart_print("Booting...\n\n");
334
 
335
  // wait for UART to finish transmitting
336
  while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0);
337
 
338 12 zero_gravi
  // reset performance counters (to benchmark actual application)
339 23 zero_gravi
  asm volatile ("csrw mcycle,    zero"); // also clears 'cycle'
340
  asm volatile ("csrw mcycleh,   zero"); // also clears 'cycleh'
341
  asm volatile ("csrw minstret,  zero"); // also clears 'instret'
342
  asm volatile ("csrw minstreth, zero"); // also clears 'instreth'
343 12 zero_gravi
 
344 2 zero_gravi
  // start app at instruction space base address
345 14 zero_gravi
  register uint32_t app_base = SYSINFO_ISPACE_BASE;
346
  asm volatile ("jalr zero, %0" : : "r" (app_base));
347
  while (1);
348 2 zero_gravi
}
349
 
350
 
351
/**********************************************************************//**
352 23 zero_gravi
 * Bootloader trap handler. Used for the MTIME tick and to capture any other traps.
353 2 zero_gravi
 * @warning Since we have no runtime environment, we have to use the interrupt attribute here. Here, and only here!
354
 **************************************************************************/
355 22 zero_gravi
void __attribute__((__interrupt__)) bootloader_trap_handler(void) {
356 2 zero_gravi
 
357
  // make sure this was caused by MTIME IRQ
358
  uint32_t cause = neorv32_cpu_csr_read(CSR_MCAUSE);
359 23 zero_gravi
  if (cause == TRAP_CODE_MTI) { // raw exception code for MTI
360 22 zero_gravi
    if (STATUS_LED_EN == 1) {
361
      // toggle status LED
362
      neorv32_gpio_pin_toggle(STATUS_LED);
363
    }
364 2 zero_gravi
    // set time for next IRQ
365 12 zero_gravi
    neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (SYSINFO_CLK/4));
366 2 zero_gravi
  }
367 23 zero_gravi
 
368
  else if (cause == TRAP_CODE_S_ACCESS) { // seems like executable is too large
369
    system_error(ERROR_SIZE);
370
  }
371
 
372
  else {
373
    neorv32_uart_print("\n\nEXCEPTION (");
374
    print_hex_word(cause);
375
    neorv32_uart_print(") @ 0x");
376
    print_hex_word(neorv32_cpu_csr_read(CSR_MEPC));
377
    system_error(ERROR_SYSTEM);
378
  }
379 2 zero_gravi
}
380
 
381
 
382
/**********************************************************************//**
383
 * Get executable stream.
384
 *
385
 * @param src Source of executable stream data. See #EXE_STREAM_SOURCE.
386
 **************************************************************************/
387
void get_exe(int src) {
388
 
389 22 zero_gravi
  // is instruction memory (IMEM) read-only?
390 12 zero_gravi
  if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM)) {
391 2 zero_gravi
    system_error(ERROR_ROM);
392
  }
393
 
394
  // flash image base address
395
  uint32_t addr = SPI_FLASH_BOOT_ADR;
396
 
397
  // get image from flash?
398
  if (src == EXE_STREAM_UART) {
399
    neorv32_uart_print("Awaiting neorv32_exe.bin... ");
400
  }
401
  else {
402
    neorv32_uart_print("Loading... ");
403
 
404
    // check if flash ready (or available at all)
405
    if (spi_flash_read_1st_id() == 0x00) { // manufacturer ID
406
      system_error(ERROR_FLASH);
407
    }
408
  }
409
 
410
  // check if valid image
411
  uint32_t signature = get_exe_word(src, addr + EXE_OFFSET_SIGNATURE);
412
  if (signature != EXE_SIGNATURE) { // signature
413
    system_error(ERROR_SIGNATURE);
414
  }
415
 
416
  // image size and checksum
417
  uint32_t size  = get_exe_word(src, addr + EXE_OFFSET_SIZE); // size in bytes
418
  uint32_t check = get_exe_word(src, addr + EXE_OFFSET_CHECKSUM); // complement sum checksum
419
 
420
  // transfer program data
421 12 zero_gravi
  uint32_t *pnt = (uint32_t*)SYSINFO_ISPACE_BASE;
422 2 zero_gravi
  uint32_t checksum = 0;
423
  uint32_t d = 0, i = 0;
424
  addr = addr + EXE_OFFSET_DATA;
425
  while (i < (size/4)) { // in words
426
    d = get_exe_word(src, addr);
427
    checksum += d;
428
    pnt[i++] = d;
429
    addr += 4;
430
  }
431
 
432
  // error during transfer?
433
  if ((checksum + check) != 0) {
434
    system_error(ERROR_CHECKSUM);
435
  }
436
  else {
437
    neorv32_uart_print("OK");
438 22 zero_gravi
    exe_available = size; // store exe size
439 2 zero_gravi
  }
440
}
441
 
442
 
443
/**********************************************************************//**
444
 * Store content of instruction memory to SPI flash.
445
 **************************************************************************/
446
void save_exe(void) {
447
 
448
  // size of last uploaded executable
449 22 zero_gravi
  uint32_t size = exe_available;
450 2 zero_gravi
 
451
  if (size == 0) {
452
    neorv32_uart_print("No executable available.");
453
    return;
454
  }
455
 
456
  uint32_t addr = SPI_FLASH_BOOT_ADR;
457
 
458
  // info and prompt
459
  neorv32_uart_print("Write 0x");
460
  print_hex_word(size);
461
  neorv32_uart_print(" bytes to SPI flash @ 0x");
462
  print_hex_word(addr);
463
  neorv32_uart_print("? (y/n) ");
464
 
465
  char c = neorv32_uart_getc();
466
  neorv32_uart_putc(c);
467
  if (c != 'y') {
468
    return;
469
  }
470
 
471
  // check if flash ready (or available at all)
472
  if (spi_flash_read_1st_id() == 0x00) { // manufacturer ID
473
    system_error(ERROR_FLASH);
474
  }
475
 
476
  neorv32_uart_print("\nFlashing... ");
477
 
478
  // clear memory before writing
479
  uint32_t num_sectors = (size / SPI_FLASH_SECTOR_SIZE) + 1; // clear at least 1 sector
480
  uint32_t sector = SPI_FLASH_BOOT_ADR;
481
  while (num_sectors--) {
482
    spi_flash_erase_sector(sector);
483
    sector += SPI_FLASH_SECTOR_SIZE;
484
  }
485
 
486
  // write EXE signature
487
  spi_flash_write_word(addr + EXE_OFFSET_SIGNATURE, EXE_SIGNATURE);
488
 
489
  // write size
490
  spi_flash_write_word(addr + EXE_OFFSET_SIZE, size);
491
 
492
  // store data from instruction memory and update checksum
493
  uint32_t checksum = 0;
494 12 zero_gravi
  uint32_t *pnt = (uint32_t*)SYSINFO_ISPACE_BASE;
495 2 zero_gravi
  addr = addr + EXE_OFFSET_DATA;
496
  uint32_t i = 0;
497
  while (i < (size/4)) { // in words
498
    uint32_t d = (uint32_t)*pnt++;
499
    checksum += d;
500
    spi_flash_write_word(addr, d);
501
    addr += 4;
502
    i++;
503
  }
504
 
505
  // write checksum (sum complement)
506
  checksum = (~checksum) + 1;
507
  spi_flash_write_word(SPI_FLASH_BOOT_ADR + EXE_OFFSET_CHECKSUM, checksum);
508
 
509
  neorv32_uart_print("OK");
510
}
511
 
512
 
513
/**********************************************************************//**
514
 * Get word from executable stream
515
 *
516
 * @param src Source of executable stream data. See #EXE_STREAM_SOURCE.
517
 * @param addr Address when accessing SPI flash.
518
 * @return 32-bit data word from stream.
519
 **************************************************************************/
520
uint32_t get_exe_word(int src, uint32_t addr) {
521
 
522
  union {
523
    uint32_t uint32;
524
    uint8_t  uint8[sizeof(uint32_t)];
525
  } data;
526
 
527
  uint32_t i;
528
  for (i=0; i<4; i++) {
529
    if (src == EXE_STREAM_UART) {
530
      data.uint8[3-i] = (uint8_t)neorv32_uart_getc();
531
    }
532
    else {
533
      data.uint8[3-i] = spi_flash_read_byte(addr + i);
534
    }
535
  }
536
 
537
  return data.uint32;
538
}
539
 
540
 
541
/**********************************************************************//**
542
 * Output system error ID and stall.
543
 *
544
 * @param[in] err_code Error code. See #ERROR_CODES.
545
 **************************************************************************/
546
void system_error(uint8_t err_code) {
547
 
548 23 zero_gravi
  neorv32_uart_print("\a\nERROR_"); // output error code with annoying bell sound
549 22 zero_gravi
  neorv32_uart_putc('0' + ((char)err_code)); // FIXME err_code should/must be below 10
550 2 zero_gravi
 
551
  neorv32_cpu_dint(); // deactivate IRQs
552 22 zero_gravi
  if (STATUS_LED_EN == 1) {
553
    neorv32_gpio_port_set(1 << STATUS_LED); // permanently light up status LED
554
  }
555 2 zero_gravi
 
556 13 zero_gravi
  asm volatile ("wfi"); // power-down
557 2 zero_gravi
  while(1); // freeze
558
}
559
 
560
 
561
/**********************************************************************//**
562
 * Print 32-bit number as 8-digit hexadecimal value (with "0x" suffix).
563
 *
564
 * @param[in] num Number to print as hexadecimal.
565
 **************************************************************************/
566
void print_hex_word(uint32_t num) {
567
 
568
  static const char hex_symbols[16] = "0123456789ABCDEF";
569
 
570
  neorv32_uart_print("0x");
571
 
572
  int i;
573
  for (i=0; i<8; i++) {
574
    uint32_t index = (num >> (28 - 4*i)) & 0xF;
575
    neorv32_uart_putc(hex_symbols[index]);
576
  }
577
}
578
 
579
 
580
 
581
// -------------------------------------------------------------------------------------
582
// SPI flash functions
583
// -------------------------------------------------------------------------------------
584
 
585
/**********************************************************************//**
586
 * Read byte from SPI flash.
587
 *
588
 * @param[in] addr Flash read address.
589
 * @return Read byte from SPI flash.
590
 **************************************************************************/
591
uint8_t spi_flash_read_byte(uint32_t addr) {
592
 
593
  neorv32_spi_cs_en(SPI_FLASH_CS);
594
 
595
  neorv32_spi_trans(SPI_FLASH_CMD_READ);
596 4 zero_gravi
  spi_flash_write_addr(addr);
597 2 zero_gravi
  uint8_t rdata = (uint8_t)neorv32_spi_trans(0);
598
 
599
  neorv32_spi_cs_dis(SPI_FLASH_CS);
600
 
601
  return rdata;
602
}
603
 
604
 
605
/**********************************************************************//**
606
 * Write byte to SPI flash.
607
 *
608
 * @param[in] addr SPI flash read address.
609
 * @param[in] wdata SPI flash read data.
610
 **************************************************************************/
611
void spi_flash_write_byte(uint32_t addr, uint8_t wdata) {
612
 
613 4 zero_gravi
  spi_flash_write_enable(); // allow write-access
614 2 zero_gravi
 
615
  neorv32_spi_cs_en(SPI_FLASH_CS);
616
 
617
  neorv32_spi_trans(SPI_FLASH_CMD_PAGE_PROGRAM);
618 4 zero_gravi
  spi_flash_write_addr(addr);
619 2 zero_gravi
  neorv32_spi_trans(wdata);
620
 
621
  neorv32_spi_cs_dis(SPI_FLASH_CS);
622
 
623
  while (1) {
624
    uint8_t tmp = spi_flash_read_status();
625
    if ((tmp & 0x01) == 0) { // write in progress flag cleared?
626
      break;
627
    }
628
  }
629
}
630
 
631
 
632
/**********************************************************************//**
633
 * Write word to SPI flash.
634
 *
635
 * @param addr SPI flash write address.
636
 * @param wdata SPI flash write data.
637
 **************************************************************************/
638
void spi_flash_write_word(uint32_t addr, uint32_t wdata) {
639
 
640
  union {
641
    uint32_t uint32;
642
    uint8_t  uint8[sizeof(uint32_t)];
643
  } data;
644
 
645
  data.uint32 = wdata;
646
 
647
  uint32_t i;
648
  for (i=0; i<4; i++) {
649
    spi_flash_write_byte(addr + i, data.uint8[3-i]);
650
  }
651
}
652
 
653
 
654
/**********************************************************************//**
655
 * Erase sector (64kB) at base adress.
656
 *
657
 * @param[in] addr Base address of sector to erase.
658
 **************************************************************************/
659
void spi_flash_erase_sector(uint32_t addr) {
660
 
661 4 zero_gravi
  spi_flash_write_enable(); // allow write-access
662 2 zero_gravi
 
663
  neorv32_spi_cs_en(SPI_FLASH_CS);
664
 
665
  neorv32_spi_trans(SPI_FLASH_CMD_SECTOR_ERASE);
666 4 zero_gravi
  spi_flash_write_addr(addr);
667 2 zero_gravi
 
668
  neorv32_spi_cs_dis(SPI_FLASH_CS);
669
 
670
  while (1) {
671
    uint8_t tmp = spi_flash_read_status();
672
    if ((tmp & 0x01) == 0) { // write in progress flag cleared?
673
      break;
674
    }
675
  }
676
}
677
 
678
 
679
/**********************************************************************//**
680
 * Read status register.
681
 *
682
 * @return Status register.
683
 **************************************************************************/
684
uint8_t spi_flash_read_status(void) {
685
 
686
  neorv32_spi_cs_en(SPI_FLASH_CS);
687
 
688
  neorv32_spi_trans(SPI_FLASH_CMD_READ_STATUS);
689
  uint8_t status = (uint8_t)neorv32_spi_trans(0);
690
 
691
  neorv32_spi_cs_dis(SPI_FLASH_CS);
692
 
693
  return status;
694
}
695
 
696
 
697
/**********************************************************************//**
698
 * Read first byte of ID (manufacturer ID), should be != 0x00.
699
 *
700
 * @note The first bit of the manufacturer ID is used to detect if a Flash is connected at all.
701
 *
702
 * @return First byte of ID.
703
 **************************************************************************/
704
uint8_t spi_flash_read_1st_id(void) {
705
 
706
  neorv32_spi_cs_en(SPI_FLASH_CS);
707
 
708
  neorv32_spi_trans(SPI_FLASH_CMD_READ_ID);
709
  uint8_t id = (uint8_t)neorv32_spi_trans(0);
710
 
711
  neorv32_spi_cs_dis(SPI_FLASH_CS);
712
 
713
  return id;
714
}
715
 
716
 
717
/**********************************************************************//**
718 4 zero_gravi
 * Enable flash write access.
719 2 zero_gravi
 **************************************************************************/
720 4 zero_gravi
void spi_flash_write_enable(void) {
721 2 zero_gravi
 
722
  neorv32_spi_cs_en(SPI_FLASH_CS);
723 4 zero_gravi
  neorv32_spi_trans(SPI_FLASH_CMD_WRITE_ENABLE);
724
  neorv32_spi_cs_dis(SPI_FLASH_CS);
725
}
726 2 zero_gravi
 
727
 
728 4 zero_gravi
/**********************************************************************//**
729
 * Send address word to flash.
730
 *
731
 * @param[in] addr Address word.
732
 **************************************************************************/
733
void spi_flash_write_addr(uint32_t addr) {
734
 
735
  union {
736
    uint32_t uint32;
737
    uint8_t  uint8[sizeof(uint32_t)];
738
  } address;
739
 
740
  address.uint32 = addr;
741
 
742
  neorv32_spi_trans(address.uint8[2]);
743
  neorv32_spi_trans(address.uint8[1]);
744
  neorv32_spi_trans(address.uint8[0]);
745 2 zero_gravi
}
746
 

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