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[/] [neorv32/] [trunk/] [sw/] [bootloader/] [bootloader.c] - Blame information for rev 61

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1 2 zero_gravi
// #################################################################################################
2
// # << NEORV32 - Bootloader >>                                                                    #
3
// # ********************************************************************************************* #
4
// # BSD 3-Clause License                                                                          #
5
// #                                                                                               #
6 55 zero_gravi
// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi
// #                                                                                               #
8
// # Redistribution and use in source and binary forms, with or without modification, are          #
9
// # permitted provided that the following conditions are met:                                     #
10
// #                                                                                               #
11
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12
// #    conditions and the following disclaimer.                                                   #
13
// #                                                                                               #
14
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15
// #    conditions and the following disclaimer in the documentation and/or other materials        #
16
// #    provided with the distribution.                                                            #
17
// #                                                                                               #
18
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19
// #    endorse or promote products derived from this software without specific prior written      #
20
// #    permission.                                                                                #
21
// #                                                                                               #
22
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
31
// # ********************************************************************************************* #
32 61 zero_gravi
// # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32       (c) Stephan Nolting #
33 2 zero_gravi
// #################################################################################################
34
 
35
 
36
/**********************************************************************//**
37
 * @file bootloader.c
38
 * @author Stephan Nolting
39 61 zero_gravi
 * @brief NEORV32 bootloader.
40 2 zero_gravi
 **************************************************************************/
41
 
42
// Libraries
43
#include <stdint.h>
44
#include <neorv32.h>
45
 
46
 
47
/**********************************************************************//**
48 61 zero_gravi
 * @name Bootloader configuration (override via console to customize)
49
 * default values are used if not explicitly customized
50 2 zero_gravi
 **************************************************************************/
51
/**@{*/
52 61 zero_gravi
 
53
/* ---- UART interface configuration ---- */
54
 
55
/** Set to 0 to disable UART interface */
56
#ifndef UART_EN
57
  #define UART_EN 1
58
#endif
59
 
60
/** UART BAUD rate for serial interface */
61
#ifndef UART_BAUD
62
  #define UART_BAUD 19200
63
#endif
64
 
65
/* ---- Status LED ---- */
66
 
67
/** Set to 0 to disable bootloader status LED (heart beat) at GPIO.gpio_o(STATUS_LED_PIN) */
68
#ifndef STATUS_LED_EN
69
  #define STATUS_LED_EN 1
70
#endif
71
 
72
/** GPIO output pin for high-active bootloader status LED (heart beat) */
73
#ifndef STATUS_LED_PIN
74
  #define STATUS_LED_PIN 0
75
#endif
76
 
77
/* ---- Boot configuration ---- */
78
 
79
/** Set to 1 to enable automatic (after reset) boot from external SPI flash at address SPI_BOOT_BASE_ADDR */
80
#ifndef AUTO_BOOT_SPI_EN
81
  #define AUTO_BOOT_SPI_EN 0
82
#endif
83
 
84
/** Set to 1 to enable boot via on-chip debugger (keep CPU in halt loop until OCD takes over control) */
85
#ifndef AUTO_BOOT_OCD_EN
86
  #define AUTO_BOOT_OCD_EN 0
87
#endif
88
 
89
/** Time until the auto-boot sequence starts (in seconds); 0 = disabled */
90
#ifndef AUTO_BOOT_TIMEOUT
91
  #define AUTO_BOOT_TIMEOUT 8
92
#endif
93
 
94
/* ---- SPI configuration ---- */
95
 
96
/** SPI flash chip select (low-active) at SPI.spi_csn_o(SPI_FLASH_CS) */
97
#ifndef SPI_FLASH_CS
98
  #define SPI_FLASH_CS 0
99
#endif
100
 
101
/** SPI flash sector size in bytes */
102
#ifndef SPI_FLASH_SECTOR_SIZE
103
  #define SPI_FLASH_SECTOR_SIZE 65536 // default = 64kB
104
#endif
105
 
106
/** SPI flash clock pre-scaler; see #NEORV32_TWI_CT_enum */
107
#ifndef SPI_FLASH_CLK_PRSC
108
  #define SPI_FLASH_CLK_PRSC CLK_PRSC_8
109
#endif
110
 
111
/** SPI flash boot base address */
112
#ifndef SPI_BOOT_BASE_ADDR
113
  #define SPI_BOOT_BASE_ADDR 0x08000000
114
#endif
115 2 zero_gravi
/**@}*/
116
 
117
 
118
/**********************************************************************//**
119
  Executable stream source select
120
 **************************************************************************/
121
enum EXE_STREAM_SOURCE {
122
  EXE_STREAM_UART  = 0, /**< Get executable via UART */
123
  EXE_STREAM_FLASH = 1  /**< Get executable via SPI flash */
124
};
125
 
126
 
127
/**********************************************************************//**
128
 * Error codes
129
 **************************************************************************/
130
enum ERROR_CODES {
131
  ERROR_SIGNATURE = 0, /**< 0: Wrong signature in executable */
132
  ERROR_SIZE      = 1, /**< 1: Insufficient instruction memory capacity */
133
  ERROR_CHECKSUM  = 2, /**< 2: Checksum error in executable */
134 61 zero_gravi
  ERROR_FLASH     = 3  /**< 3: SPI flash access error */
135 2 zero_gravi
};
136
 
137
 
138
/**********************************************************************//**
139
 * SPI flash commands
140
 **************************************************************************/
141
enum SPI_FLASH_CMD {
142
  SPI_FLASH_CMD_PAGE_PROGRAM = 0x02, /**< Program page */
143
  SPI_FLASH_CMD_READ         = 0x03, /**< Read data */
144
  SPI_FLASH_CMD_READ_STATUS  = 0x05, /**< Get status register */
145
  SPI_FLASH_CMD_WRITE_ENABLE = 0x06, /**< Allow write access */
146
  SPI_FLASH_CMD_READ_ID      = 0x9E, /**< Read manufacturer ID */
147
  SPI_FLASH_CMD_SECTOR_ERASE = 0xD8  /**< Erase complete sector */
148
};
149
 
150
 
151
/**********************************************************************//**
152
 * NEORV32 executable
153
 **************************************************************************/
154
enum NEORV32_EXECUTABLE {
155
  EXE_OFFSET_SIGNATURE =  0, /**< Offset in bytes from start to signature (32-bit) */
156
  EXE_OFFSET_SIZE      =  4, /**< Offset in bytes from start to size (32-bit) */
157
  EXE_OFFSET_CHECKSUM  =  8, /**< Offset in bytes from start to checksum (32-bit) */
158
  EXE_OFFSET_DATA      = 12, /**< Offset in bytes from start to data (32-bit) */
159
};
160
 
161
 
162
/**********************************************************************//**
163
 * Valid executable identification signature.
164
 **************************************************************************/
165
#define EXE_SIGNATURE 0x4788CAFE
166
 
167
 
168
/**********************************************************************//**
169 61 zero_gravi
 * Helper macros
170 2 zero_gravi
 **************************************************************************/
171
/**@{*/
172 61 zero_gravi
/** Actual define-to-string helper */
173 2 zero_gravi
#define xstr(a) str(a)
174 61 zero_gravi
/** Internal helper macro */
175 2 zero_gravi
#define str(a) #a
176 61 zero_gravi
/** Print to UART 0 */
177
#if (UART_EN != 0)
178
  #define PRINT_TEXT(...) neorv32_uart0_print(__VA_ARGS__)
179
  #define PRINT_XNUM(a) print_hex_word(a)
180
  #define PRINT_GETC(a) neorv32_uart0_getc()
181
  #define PRINT_PUTC(a) neorv32_uart0_putc(a)
182
#else
183
  #define PRINT_TEXT(...)
184
  #define PRINT_XNUM(a)
185
  #define PRINT_GETC(a) 0
186
  #define PRINT_PUTC(a)
187
#endif
188 2 zero_gravi
/**@}*/
189
 
190
 
191 22 zero_gravi
/**********************************************************************//**
192
 * This global variable keeps the size of the available executable in bytes.
193
 * If =0 no executable is available (yet).
194
 **************************************************************************/
195 47 zero_gravi
volatile uint32_t exe_available = 0;
196 22 zero_gravi
 
197
 
198 47 zero_gravi
/**********************************************************************//**
199 61 zero_gravi
 * Only set during executable fetch (required for capturing STORE BUS-TIMOUT exception).
200 47 zero_gravi
 **************************************************************************/
201
volatile uint32_t getting_exe = 0;
202
 
203
 
204 2 zero_gravi
// Function prototypes
205 22 zero_gravi
void __attribute__((__interrupt__)) bootloader_trap_handler(void);
206 2 zero_gravi
void print_help(void);
207
void start_app(void);
208
void get_exe(int src);
209
void save_exe(void);
210
uint32_t get_exe_word(int src, uint32_t addr);
211
void system_error(uint8_t err_code);
212
void print_hex_word(uint32_t num);
213
 
214 37 zero_gravi
// SPI flash driver functions
215 2 zero_gravi
uint8_t spi_flash_read_byte(uint32_t addr);
216
void spi_flash_write_byte(uint32_t addr, uint8_t wdata);
217
void spi_flash_write_word(uint32_t addr, uint32_t wdata);
218
void spi_flash_erase_sector(uint32_t addr);
219
uint8_t spi_flash_read_1st_id(void);
220 37 zero_gravi
void spi_flash_write_wait(void);
221 4 zero_gravi
void spi_flash_write_enable(void);
222
void spi_flash_write_addr(uint32_t addr);
223 2 zero_gravi
 
224
 
225
/**********************************************************************//**
226 61 zero_gravi
 * Sanity check: Base ISA only!
227
 **************************************************************************/
228
#if defined __riscv_atomic || defined __riscv_a || __riscv_b || __riscv_compressed || defined __riscv_c || defined __riscv_mul || defined __riscv_m
229
  #warning In order to allow the bootloader to run on *any* CPU configuration it should be compiled using the base ISA only.
230
#endif
231
 
232
 
233
/**********************************************************************//**
234 2 zero_gravi
 * Bootloader main.
235
 **************************************************************************/
236
int main(void) {
237
 
238 61 zero_gravi
  // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
239
  // AUTO BOOT: OCD
240
  // Stay in endless loop until the on-chip debugger
241
  // takes over CPU control
242
  // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
243
#if (AUTO_BOOT_OCD_EN != 0)
244
  #warning Boot configuration: Boot via on-chip debugger.
245
  while(1) {
246
    asm volatile ("nop");
247
  }
248
  return 0; // should never be reached
249 39 zero_gravi
#endif
250
 
251
 
252 61 zero_gravi
  // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
253
  // AUTO BOOT: SPI flash
254
  // Bootloader will directly boot and execute image from SPI flash
255
  // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
256
#if (AUTO_BOOT_SPI_EN != 0)
257
  #warning Boot configuration: Auto boot from external SPI flash.
258 39 zero_gravi
 
259 61 zero_gravi
  PRINT_TEXT("\nNEORV32 bootloader\nLoading from SPI flash at ");
260
  PRINT_XNUM((uint32_t)SPI_BOOT_BASE_ADDR);
261
  PRINT_TEXT("...\n");
262 2 zero_gravi
 
263 61 zero_gravi
  get_exe(EXE_STREAM_FLASH);
264
  PRINT_TEXT("\n");
265
  start_app();
266 2 zero_gravi
 
267 61 zero_gravi
  return 0; // bootloader should never return
268 56 zero_gravi
#endif
269 39 zero_gravi
 
270 2 zero_gravi
 
271 61 zero_gravi
  // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
272
  // AUTO BOOT: Default
273
  // User UART to upload new executable and optionally store it to SPI flash
274
  // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
275 2 zero_gravi
 
276 61 zero_gravi
  exe_available = 0; // global variable for executable size; 0 means there is no exe available
277
  getting_exe   = 0; // we are not trying to get an executable yet
278
 
279
 
280 60 zero_gravi
  // configure trap handler (bare-metal, no neorv32 rte available)
281 47 zero_gravi
  neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&bootloader_trap_handler));
282
 
283 61 zero_gravi
  // setup SPI for 8-bit, clock-mode 0
284
  neorv32_spi_setup(SPI_FLASH_CLK_PRSC, 0, 0);
285 2 zero_gravi
 
286 61 zero_gravi
#if (STATUS_LED_EN != 0)
287
  if (neorv32_gpio_available()) {
288
    // activate status LED, clear all others
289
    neorv32_gpio_port_set(1 << STATUS_LED_PIN);
290
  }
291
#endif
292 2 zero_gravi
 
293 61 zero_gravi
#if (UART_EN != 0)
294
  // setup UART0 (primary UART, no parity bit, no hardware flow control)
295
  neorv32_uart0_setup(UART_BAUD, PARITY_NONE, FLOW_CONTROL_NONE);
296
#endif
297 2 zero_gravi
 
298 61 zero_gravi
  // Configure machine system timer interrupt for ~2Hz
299
  if (neorv32_mtime_available()) {
300
    neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (SYSINFO_CLK/4));
301
    // active timer IRQ
302
    neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE); // activate MTIME IRQ source only!
303
    neorv32_cpu_eint(); // enable global interrupts
304
  }
305 2 zero_gravi
 
306 39 zero_gravi
 
307 2 zero_gravi
  // ------------------------------------------------
308
  // Show bootloader intro and system info
309
  // ------------------------------------------------
310 61 zero_gravi
  PRINT_TEXT("\n\n\n<< NEORV32 Bootloader >>\n\n"
311 2 zero_gravi
                     "BLDV: "__DATE__"\nHWV:  ");
312 61 zero_gravi
  PRINT_XNUM(neorv32_cpu_csr_read(CSR_MIMPID));
313
  PRINT_TEXT("\nCLK:  ");
314
  PRINT_XNUM(SYSINFO_CLK);
315
  PRINT_TEXT("\nMISA: ");
316
  PRINT_XNUM(neorv32_cpu_csr_read(CSR_MISA));
317
  PRINT_TEXT("\nZEXT: ");
318
  PRINT_XNUM(neorv32_cpu_csr_read(CSR_MZEXT));
319
  PRINT_TEXT("\nPROC: ");
320
  PRINT_XNUM(SYSINFO_FEATURES);
321
  PRINT_TEXT("\nIMEM: ");
322
  PRINT_XNUM(SYSINFO_IMEM_SIZE);
323
  PRINT_TEXT(" bytes @");
324
  PRINT_XNUM(SYSINFO_ISPACE_BASE);
325
  PRINT_TEXT("\nDMEM: ");
326
  PRINT_XNUM(SYSINFO_DMEM_SIZE);
327
  PRINT_TEXT(" bytes @");
328
  PRINT_XNUM(SYSINFO_DSPACE_BASE);
329 2 zero_gravi
 
330
 
331
  // ------------------------------------------------
332
  // Auto boot sequence
333
  // ------------------------------------------------
334 61 zero_gravi
# if (AUTO_BOOT_TIMEOUT != 0)
335
  if (neorv32_mtime_available()) {
336 2 zero_gravi
 
337 61 zero_gravi
    PRINT_TEXT("\n\nAutoboot in "xstr(AUTO_BOOT_TIMEOUT)"s. Press key to abort.\n");
338
    uint64_t timeout_time = neorv32_mtime_get_time() + (uint64_t)(AUTO_BOOT_TIMEOUT * SYSINFO_CLK);
339 13 zero_gravi
 
340 61 zero_gravi
    while(1){
341 2 zero_gravi
 
342 61 zero_gravi
      if (neorv32_uart0_available()) { // wait for any key to be pressed
343
        if (neorv32_uart0_char_received()) {
344
          break;
345
        }
346
      }
347
 
348
      if (neorv32_mtime_get_time() >= timeout_time) { // timeout? start auto boot sequence
349
        get_exe(EXE_STREAM_FLASH); // try booting from flash
350
        PRINT_TEXT("\n");
351
        start_app();
352
        while(1);
353
      }
354
 
355 2 zero_gravi
    }
356 61 zero_gravi
    PRINT_TEXT("Aborted.\n\n");
357 2 zero_gravi
  }
358 24 zero_gravi
#else
359 61 zero_gravi
  PRINT_TEXT("Aborted.\n\n");
360 24 zero_gravi
#endif
361
 
362 2 zero_gravi
  print_help();
363
 
364
 
365
  // ------------------------------------------------
366
  // Bootloader console
367
  // ------------------------------------------------
368
  while (1) {
369
 
370 61 zero_gravi
    PRINT_TEXT("\nCMD:> ");
371
    char c = PRINT_GETC();
372
    PRINT_PUTC(c); // echo
373
    PRINT_TEXT("\n");
374 2 zero_gravi
 
375 61 zero_gravi
    if (c == 'r') { // restart bootloader
376 22 zero_gravi
      asm volatile ("li t0, %[input_i]; jr t0" :  : [input_i] "i" (BOOTLOADER_BASE_ADDRESS)); // jump to beginning of boot ROM
377 2 zero_gravi
    }
378
    else if (c == 'h') { // help menu
379
      print_help();
380
    }
381
    else if (c == 'u') { // get executable via UART
382
      get_exe(EXE_STREAM_UART);
383
    }
384 24 zero_gravi
    else if (c == 's') { // program flash from memory (IMEM)
385 2 zero_gravi
      save_exe();
386
    }
387
    else if (c == 'l') { // get executable from flash
388
      get_exe(EXE_STREAM_FLASH);
389
    }
390 61 zero_gravi
    else if (c == 'e') { // start application program  // executable available?
391
      if (exe_available == 0) {
392
        PRINT_TEXT("No executable available.");
393
      }
394
      else {
395
        start_app();
396
      }
397 2 zero_gravi
    }
398
    else { // unknown command
399 61 zero_gravi
      PRINT_TEXT("Invalid CMD");
400 2 zero_gravi
    }
401
  }
402
 
403 60 zero_gravi
  return 1; // bootloader should never return
404 2 zero_gravi
}
405
 
406
 
407
/**********************************************************************//**
408
 * Print help menu.
409
 **************************************************************************/
410
void print_help(void) {
411
 
412 61 zero_gravi
  PRINT_TEXT("Available CMDs:\n"
413 2 zero_gravi
                     " h: Help\n"
414
                     " r: Restart\n"
415
                     " u: Upload\n"
416
                     " s: Store to flash\n"
417
                     " l: Load from flash\n"
418
                     " e: Execute");
419
}
420
 
421
 
422
/**********************************************************************//**
423
 * Start application program at the beginning of instruction space.
424
 **************************************************************************/
425
void start_app(void) {
426
 
427 23 zero_gravi
  // deactivate global IRQs
428 2 zero_gravi
  neorv32_cpu_dint();
429
 
430 61 zero_gravi
  PRINT_TEXT("Booting...\n\n");
431 2 zero_gravi
 
432
  // wait for UART to finish transmitting
433 61 zero_gravi
  while (neorv32_uart0_tx_busy());
434 2 zero_gravi
 
435
  // start app at instruction space base address
436 14 zero_gravi
  register uint32_t app_base = SYSINFO_ISPACE_BASE;
437
  asm volatile ("jalr zero, %0" : : "r" (app_base));
438
  while (1);
439 2 zero_gravi
}
440
 
441
 
442
/**********************************************************************//**
443 23 zero_gravi
 * Bootloader trap handler. Used for the MTIME tick and to capture any other traps.
444 61 zero_gravi
 *
445
 * @warning Adapt exception PC only for sync exceptions!
446
 *
447
 * @note Since we have no runtime environment, we have to use the interrupt attribute here. Here and only here!
448 2 zero_gravi
 **************************************************************************/
449 22 zero_gravi
void __attribute__((__interrupt__)) bootloader_trap_handler(void) {
450 2 zero_gravi
 
451 47 zero_gravi
  uint32_t cause = neorv32_cpu_csr_read(CSR_MCAUSE);
452
 
453 61 zero_gravi
  // Machine timer interrupt
454 23 zero_gravi
  if (cause == TRAP_CODE_MTI) { // raw exception code for MTI
455 56 zero_gravi
#if (STATUS_LED_EN != 0)
456 61 zero_gravi
    if (neorv32_gpio_available()) {
457
      neorv32_gpio_pin_toggle(STATUS_LED_PIN); // toggle status LED
458
    }
459 56 zero_gravi
#endif
460 2 zero_gravi
    // set time for next IRQ
461 61 zero_gravi
    if (neorv32_mtime_available()) {
462
      neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (SYSINFO_CLK/4));
463
    }
464 2 zero_gravi
  }
465 61 zero_gravi
 
466
  // Bus store access error during get_exe
467
  else if ((cause == TRAP_CODE_S_ACCESS) && (getting_exe)) {
468
    system_error(ERROR_SIZE); // -> seems like executable is too large
469
  }
470
 
471
  // Anything else (that was not expected); output exception notifier and try to resume
472 23 zero_gravi
  else {
473 61 zero_gravi
    uint32_t epc = neorv32_cpu_csr_read(CSR_MEPC);
474
#if (UART_EN != 0)
475
    if (neorv32_uart0_available()) {
476
      PRINT_TEXT("\n[EXC ");
477
      PRINT_XNUM(cause); // MCAUSE
478
      PRINT_PUTC(' ');
479
      PRINT_XNUM(epc); // MEPC
480
      PRINT_PUTC(' ');
481
      PRINT_XNUM(neorv32_cpu_csr_read(CSR_MTVAL)); // MTVAL
482
      PRINT_TEXT("]\n");
483 47 zero_gravi
    }
484 61 zero_gravi
#endif
485
    neorv32_cpu_csr_write(CSR_MEPC, epc + 4); // advance to next instruction
486 23 zero_gravi
  }
487 2 zero_gravi
}
488
 
489
 
490
/**********************************************************************//**
491
 * Get executable stream.
492
 *
493
 * @param src Source of executable stream data. See #EXE_STREAM_SOURCE.
494
 **************************************************************************/
495
void get_exe(int src) {
496
 
497 47 zero_gravi
  getting_exe = 1; // to inform trap handler we were trying to get an executable
498
 
499 2 zero_gravi
  // flash image base address
500 61 zero_gravi
  uint32_t addr = (uint32_t)SPI_BOOT_BASE_ADDR;
501 2 zero_gravi
 
502
  // get image from flash?
503
  if (src == EXE_STREAM_UART) {
504 61 zero_gravi
    PRINT_TEXT("Awaiting neorv32_exe.bin... ");
505 2 zero_gravi
  }
506
  else {
507 61 zero_gravi
    PRINT_TEXT("Loading... ");
508 2 zero_gravi
 
509 61 zero_gravi
    // flash checks
510
    if ((neorv32_spi_available() == 0) ||    // check if SPI is available at all
511
        (spi_flash_read_1st_id() == 0x00)) { // check if flash ready (or available at all)
512 57 zero_gravi
      system_error(ERROR_FLASH);
513
    }
514 2 zero_gravi
  }
515
 
516
  // check if valid image
517
  uint32_t signature = get_exe_word(src, addr + EXE_OFFSET_SIGNATURE);
518
  if (signature != EXE_SIGNATURE) { // signature
519
    system_error(ERROR_SIGNATURE);
520
  }
521
 
522
  // image size and checksum
523
  uint32_t size  = get_exe_word(src, addr + EXE_OFFSET_SIZE); // size in bytes
524
  uint32_t check = get_exe_word(src, addr + EXE_OFFSET_CHECKSUM); // complement sum checksum
525
 
526
  // transfer program data
527 12 zero_gravi
  uint32_t *pnt = (uint32_t*)SYSINFO_ISPACE_BASE;
528 2 zero_gravi
  uint32_t checksum = 0;
529
  uint32_t d = 0, i = 0;
530
  addr = addr + EXE_OFFSET_DATA;
531
  while (i < (size/4)) { // in words
532
    d = get_exe_word(src, addr);
533
    checksum += d;
534
    pnt[i++] = d;
535
    addr += 4;
536
  }
537
 
538
  // error during transfer?
539
  if ((checksum + check) != 0) {
540
    system_error(ERROR_CHECKSUM);
541
  }
542
  else {
543 61 zero_gravi
    PRINT_TEXT("OK");
544 22 zero_gravi
    exe_available = size; // store exe size
545 2 zero_gravi
  }
546 47 zero_gravi
 
547
  getting_exe = 0; // to inform trap handler we are done getting an executable
548 2 zero_gravi
}
549
 
550
 
551
/**********************************************************************//**
552
 * Store content of instruction memory to SPI flash.
553
 **************************************************************************/
554
void save_exe(void) {
555
 
556
  // size of last uploaded executable
557 22 zero_gravi
  uint32_t size = exe_available;
558 2 zero_gravi
 
559
  if (size == 0) {
560 61 zero_gravi
    PRINT_TEXT("No executable available.");
561 2 zero_gravi
    return;
562
  }
563
 
564 61 zero_gravi
  uint32_t addr = (uint32_t)SPI_BOOT_BASE_ADDR;
565 2 zero_gravi
 
566
  // info and prompt
567 61 zero_gravi
  PRINT_TEXT("Write ");
568
  PRINT_XNUM(size);
569
  PRINT_TEXT(" bytes to SPI flash @ ");
570
  PRINT_XNUM(addr);
571
  PRINT_TEXT("? (y/n) ");
572 2 zero_gravi
 
573 61 zero_gravi
  char c = PRINT_GETC();
574
  PRINT_PUTC(c);
575 2 zero_gravi
  if (c != 'y') {
576
    return;
577
  }
578
 
579
  // check if flash ready (or available at all)
580
  if (spi_flash_read_1st_id() == 0x00) { // manufacturer ID
581
    system_error(ERROR_FLASH);
582
  }
583
 
584 61 zero_gravi
  PRINT_TEXT("\nFlashing... ");
585 2 zero_gravi
 
586
  // clear memory before writing
587 61 zero_gravi
  uint32_t num_sectors = (size / (SPI_FLASH_SECTOR_SIZE)) + 1; // clear at least 1 sector
588
  uint32_t sector = (uint32_t)SPI_BOOT_BASE_ADDR;
589 2 zero_gravi
  while (num_sectors--) {
590
    spi_flash_erase_sector(sector);
591
    sector += SPI_FLASH_SECTOR_SIZE;
592
  }
593
 
594
  // write EXE signature
595
  spi_flash_write_word(addr + EXE_OFFSET_SIGNATURE, EXE_SIGNATURE);
596
 
597
  // write size
598
  spi_flash_write_word(addr + EXE_OFFSET_SIZE, size);
599
 
600
  // store data from instruction memory and update checksum
601
  uint32_t checksum = 0;
602 12 zero_gravi
  uint32_t *pnt = (uint32_t*)SYSINFO_ISPACE_BASE;
603 2 zero_gravi
  addr = addr + EXE_OFFSET_DATA;
604
  uint32_t i = 0;
605
  while (i < (size/4)) { // in words
606
    uint32_t d = (uint32_t)*pnt++;
607
    checksum += d;
608
    spi_flash_write_word(addr, d);
609
    addr += 4;
610
    i++;
611
  }
612
 
613
  // write checksum (sum complement)
614
  checksum = (~checksum) + 1;
615 61 zero_gravi
  spi_flash_write_word((uint32_t)SPI_BOOT_BASE_ADDR + EXE_OFFSET_CHECKSUM, checksum);
616 2 zero_gravi
 
617 61 zero_gravi
  PRINT_TEXT("OK");
618 2 zero_gravi
}
619
 
620
 
621
/**********************************************************************//**
622
 * Get word from executable stream
623
 *
624
 * @param src Source of executable stream data. See #EXE_STREAM_SOURCE.
625
 * @param addr Address when accessing SPI flash.
626
 * @return 32-bit data word from stream.
627
 **************************************************************************/
628
uint32_t get_exe_word(int src, uint32_t addr) {
629
 
630
  union {
631
    uint32_t uint32;
632
    uint8_t  uint8[sizeof(uint32_t)];
633
  } data;
634
 
635
  uint32_t i;
636
  for (i=0; i<4; i++) {
637
    if (src == EXE_STREAM_UART) {
638 61 zero_gravi
      data.uint8[i] = (uint8_t)PRINT_GETC();
639 2 zero_gravi
    }
640
    else {
641 60 zero_gravi
      data.uint8[i] = spi_flash_read_byte(addr + i);
642 2 zero_gravi
    }
643
  }
644
 
645
  return data.uint32;
646
}
647
 
648
 
649
/**********************************************************************//**
650
 * Output system error ID and stall.
651
 *
652
 * @param[in] err_code Error code. See #ERROR_CODES.
653
 **************************************************************************/
654
void system_error(uint8_t err_code) {
655
 
656 61 zero_gravi
  PRINT_TEXT("\a\nERROR_"); // output error code with annoying bell sound
657
  PRINT_PUTC('0' + ((char)err_code));
658 2 zero_gravi
 
659
  neorv32_cpu_dint(); // deactivate IRQs
660 61 zero_gravi
#if (STATUS_LED_EN != 0)
661
  if (neorv32_gpio_available()) {
662
    neorv32_gpio_port_set(1 << STATUS_LED_PIN); // permanently light up status LED
663 22 zero_gravi
  }
664 61 zero_gravi
#endif
665 2 zero_gravi
 
666
  while(1); // freeze
667
}
668
 
669
 
670
/**********************************************************************//**
671
 * Print 32-bit number as 8-digit hexadecimal value (with "0x" suffix).
672
 *
673
 * @param[in] num Number to print as hexadecimal.
674
 **************************************************************************/
675
void print_hex_word(uint32_t num) {
676
 
677 61 zero_gravi
#if (UART_EN != 0)
678 56 zero_gravi
  static const char hex_symbols[16] = "0123456789abcdef";
679 2 zero_gravi
 
680 61 zero_gravi
  PRINT_TEXT("0x");
681 2 zero_gravi
 
682
  int i;
683
  for (i=0; i<8; i++) {
684
    uint32_t index = (num >> (28 - 4*i)) & 0xF;
685 61 zero_gravi
    PRINT_PUTC(hex_symbols[index]);
686 2 zero_gravi
  }
687 61 zero_gravi
#endif
688 2 zero_gravi
}
689
 
690
 
691
 
692
// -------------------------------------------------------------------------------------
693 37 zero_gravi
// SPI flash driver functions
694 2 zero_gravi
// -------------------------------------------------------------------------------------
695
 
696
/**********************************************************************//**
697
 * Read byte from SPI flash.
698
 *
699
 * @param[in] addr Flash read address.
700
 * @return Read byte from SPI flash.
701
 **************************************************************************/
702
uint8_t spi_flash_read_byte(uint32_t addr) {
703
 
704
  neorv32_spi_cs_en(SPI_FLASH_CS);
705
 
706
  neorv32_spi_trans(SPI_FLASH_CMD_READ);
707 4 zero_gravi
  spi_flash_write_addr(addr);
708 2 zero_gravi
  uint8_t rdata = (uint8_t)neorv32_spi_trans(0);
709
 
710
  neorv32_spi_cs_dis(SPI_FLASH_CS);
711
 
712
  return rdata;
713
}
714
 
715
 
716
/**********************************************************************//**
717
 * Write byte to SPI flash.
718
 *
719
 * @param[in] addr SPI flash read address.
720
 * @param[in] wdata SPI flash read data.
721
 **************************************************************************/
722
void spi_flash_write_byte(uint32_t addr, uint8_t wdata) {
723
 
724 4 zero_gravi
  spi_flash_write_enable(); // allow write-access
725 2 zero_gravi
 
726
  neorv32_spi_cs_en(SPI_FLASH_CS);
727
 
728
  neorv32_spi_trans(SPI_FLASH_CMD_PAGE_PROGRAM);
729 4 zero_gravi
  spi_flash_write_addr(addr);
730 2 zero_gravi
  neorv32_spi_trans(wdata);
731
 
732
  neorv32_spi_cs_dis(SPI_FLASH_CS);
733
 
734 37 zero_gravi
  spi_flash_write_wait(); // wait for write operation to finish
735 2 zero_gravi
}
736
 
737
 
738
/**********************************************************************//**
739
 * Write word to SPI flash.
740
 *
741
 * @param addr SPI flash write address.
742
 * @param wdata SPI flash write data.
743
 **************************************************************************/
744
void spi_flash_write_word(uint32_t addr, uint32_t wdata) {
745
 
746
  union {
747
    uint32_t uint32;
748
    uint8_t  uint8[sizeof(uint32_t)];
749
  } data;
750
 
751
  data.uint32 = wdata;
752
 
753 39 zero_gravi
  int i;
754 2 zero_gravi
  for (i=0; i<4; i++) {
755 60 zero_gravi
    spi_flash_write_byte(addr + i, data.uint8[i]);
756 2 zero_gravi
  }
757
}
758
 
759
 
760
/**********************************************************************//**
761
 * Erase sector (64kB) at base adress.
762
 *
763
 * @param[in] addr Base address of sector to erase.
764
 **************************************************************************/
765
void spi_flash_erase_sector(uint32_t addr) {
766
 
767 4 zero_gravi
  spi_flash_write_enable(); // allow write-access
768 2 zero_gravi
 
769
  neorv32_spi_cs_en(SPI_FLASH_CS);
770
 
771
  neorv32_spi_trans(SPI_FLASH_CMD_SECTOR_ERASE);
772 4 zero_gravi
  spi_flash_write_addr(addr);
773 2 zero_gravi
 
774
  neorv32_spi_cs_dis(SPI_FLASH_CS);
775
 
776 37 zero_gravi
  spi_flash_write_wait(); // wait for write operation to finish
777 2 zero_gravi
}
778
 
779
 
780
/**********************************************************************//**
781 37 zero_gravi
 * Read first byte of ID (manufacturer ID), should be != 0x00.
782 2 zero_gravi
 *
783 37 zero_gravi
 * @note The first bit of the manufacturer ID is used to detect if a Flash is connected at all.
784
 *
785
 * @return First byte of ID.
786 2 zero_gravi
 **************************************************************************/
787 37 zero_gravi
uint8_t spi_flash_read_1st_id(void) {
788 2 zero_gravi
 
789
  neorv32_spi_cs_en(SPI_FLASH_CS);
790
 
791 37 zero_gravi
  neorv32_spi_trans(SPI_FLASH_CMD_READ_ID);
792
  uint8_t id = (uint8_t)neorv32_spi_trans(0);
793 2 zero_gravi
 
794
  neorv32_spi_cs_dis(SPI_FLASH_CS);
795
 
796 37 zero_gravi
  return id;
797 2 zero_gravi
}
798
 
799
 
800
/**********************************************************************//**
801 37 zero_gravi
 * Wait for flash write operation to finisch.
802 2 zero_gravi
 **************************************************************************/
803 37 zero_gravi
void spi_flash_write_wait(void) {
804 2 zero_gravi
 
805 37 zero_gravi
  while(1) {
806 2 zero_gravi
 
807 37 zero_gravi
    neorv32_spi_cs_en(SPI_FLASH_CS);
808 2 zero_gravi
 
809 37 zero_gravi
    neorv32_spi_trans(SPI_FLASH_CMD_READ_STATUS);
810
    uint8_t status = (uint8_t)neorv32_spi_trans(0);
811 2 zero_gravi
 
812 37 zero_gravi
    neorv32_spi_cs_dis(SPI_FLASH_CS);
813
 
814
    if ((status & 0x01) == 0) { // write in progress flag cleared?
815
      break;
816
    }
817
  }
818 2 zero_gravi
}
819
 
820
 
821
/**********************************************************************//**
822 4 zero_gravi
 * Enable flash write access.
823 2 zero_gravi
 **************************************************************************/
824 4 zero_gravi
void spi_flash_write_enable(void) {
825 2 zero_gravi
 
826
  neorv32_spi_cs_en(SPI_FLASH_CS);
827 4 zero_gravi
  neorv32_spi_trans(SPI_FLASH_CMD_WRITE_ENABLE);
828
  neorv32_spi_cs_dis(SPI_FLASH_CS);
829
}
830 2 zero_gravi
 
831
 
832 4 zero_gravi
/**********************************************************************//**
833
 * Send address word to flash.
834
 *
835
 * @param[in] addr Address word.
836
 **************************************************************************/
837
void spi_flash_write_addr(uint32_t addr) {
838
 
839
  union {
840
    uint32_t uint32;
841
    uint8_t  uint8[sizeof(uint32_t)];
842
  } address;
843
 
844
  address.uint32 = addr;
845
 
846 39 zero_gravi
  int i;
847
  for (i=2; i>=0; i--) {
848
    neorv32_spi_trans(address.uint8[i]);
849
  }
850 2 zero_gravi
}

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