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[/] [neorv32/] [trunk/] [sw/] [common/] [crt0.S] - Blame information for rev 19

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1 2 zero_gravi
/* ################################################################################################# */
2 6 zero_gravi
/* # << NEORV32 - crt0.S - Application Start-Up Code & Minimal Runtime Environment >>              # */
3 2 zero_gravi
/* # ********************************************************************************************* # */
4 6 zero_gravi
/* # The start-up code provides a minimal runtime environment that catches all exceptions and      # */
5 2 zero_gravi
/* # interrupts and delegates them to the handler functions (installed by user via dedicated       # */
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/* # install function from the neorv32 runtime environment library).                               # */
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/* # ********************************************************************************************* # */
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/* # BSD 3-Clause License                                                                          # */
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/* #                                                                                               # */
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/* # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     # */
11
/* #                                                                                               # */
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/* # Redistribution and use in source and binary forms, with or without modification, are          # */
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/* # permitted provided that the following conditions are met:                                     # */
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/* #                                                                                               # */
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/* # 1. Redistributions of source code must retain the above copyright notice, this list of        # */
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/* #    conditions and the following disclaimer.                                                   # */
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/* #                                                                                               # */
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/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     # */
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/* #    conditions and the following disclaimer in the documentation and/or other materials        # */
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/* #    provided with the distribution.                                                            # */
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/* #                                                                                               # */
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/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  # */
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/* #    endorse or promote products derived from this software without specific prior written      # */
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/* #    permission.                                                                                # */
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/* #                                                                                               # */
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/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   # */
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/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               # */
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/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    # */
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/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     # */
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/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
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/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    # */
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/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     # */
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/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  # */
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/* # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            # */
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/* # ********************************************************************************************* # */
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/* # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting # */
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/* ################################################################################################# */
38
 
39
  .file "crt0.S"
40
  .section .text
41
  .balign 4
42
  .global _start
43
 
44
 
45
  // IO region
46 14 zero_gravi
  .equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
47 2 zero_gravi
 
48 12 zero_gravi
  // SYSINFO
49 14 zero_gravi
  .equ SYSINFO_DSPACE_BASE, 0xFFFFFFF4
50
  .equ SYSINFO_DSPACE_SIZE, 0xFFFFFFFC
51 2 zero_gravi
 
52 12 zero_gravi
 
53 2 zero_gravi
_start:
54
  .cfi_startproc
55
  .cfi_undefined ra
56
 
57
// *********************************************************
58
// Clear register file
59
// *********************************************************
60
__crt0_reg_file_clear:
61 14 zero_gravi
//addi  x0,  x0, 0 // hardwired to zero
62 2 zero_gravi
  addi  x1,  x0, 0
63
  addi  x2,  x1, 0
64
  addi  x3,  x2, 0
65
  addi  x4,  x3, 0
66
  addi  x5,  x4, 0
67
  addi  x6,  x5, 0
68
  addi  x7,  x6, 0
69
  addi  x8,  x7, 0
70
  addi  x9,  x8, 0
71 19 zero_gravi
//addi x10,  x9, 0
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//addi x11, x10, 0
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//addi x12, x11, 0
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//addi x13, x12, 0
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//addi x14, x13, 0
76 2 zero_gravi
  addi x15, x14, 0
77
 
78 19 zero_gravi
// since we dont know here if we are compiling for a rv32e architecture
79
// we won't touch registers above x15
80 2 zero_gravi
 
81
 
82
// *********************************************************
83 14 zero_gravi
// TEST AREA / DANGER ZONE
84 2 zero_gravi
// *********************************************************
85
__crt0_tests:
86
  nop
87
 
88
 
89
// *********************************************************
90
// Setup stack pointer
91
// *********************************************************
92
__crt0_stack_pointer_init:
93 12 zero_gravi
  lw    x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address
94
  lw    x12, SYSINFO_DSPACE_SIZE(zero) // data memory space size
95 2 zero_gravi
  add   sp, x11, x12
96
  addi  sp, sp, -4 // stack pointer = last entry
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  addi  fp, sp, 0  // frame pointer = stack pointer
98
 
99
 
100
// *********************************************************
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// Setup global pointer
102
// *********************************************************
103
__crt0_global_pointer_init:
104
  .option push
105
  .option norelax
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  la gp, __global_pointer$
107
  .option pop
108
 
109
 
110
// *********************************************************
111 14 zero_gravi
// Init trap handler base address
112 2 zero_gravi
// *********************************************************
113 14 zero_gravi
__crt0_neorv32_trap_init:
114
  la    x11, __crt0_dummy_trap_handler
115 6 zero_gravi
  csrw  mtvec, x11 // set address of first-level exception handler
116 2 zero_gravi
 
117
 
118
// *********************************************************
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// Reset/deactivate IO/peripheral devices
120
// Devices, that are not implemented, will cause a store access fault
121
// which is captured but actually ignored due to the dummy handler.
122
// *********************************************************
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__crt0_reset_io:
124
  li x11, IO_BEGIN // start of processor-internal IO region
125
 
126
__crt0_reset_io_loop:
127
  sw   zero, 0(x11)
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  addi x11, x11, 4
129
  bne  zero, x11, __crt0_reset_io_loop
130
 
131
 
132
// *********************************************************
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// Clear .bss section (byte-wise)
134
// *********************************************************
135
__crt0_clear_bss:
136
  la x11, __crt0_bss_start
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  la x12, __crt0_bss_end
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139
__crt0_clear_bss_loop:
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  bge  x11, x12, __crt0_clear_bss_loop_end
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  sb   zero, 0(x11)
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  addi x11, x11, 1
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  j    __crt0_clear_bss_loop
144
 
145
__crt0_clear_bss_loop_end:
146
 
147
 
148
// *********************************************************
149
// Copy initialized .data section from ROM to RAM (byte-wise)
150
// *********************************************************
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__crt0_copy_data:
152
  la x11, __crt0_copy_data_src_begin  // start of data area (copy source)
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  la x12, __crt0_copy_data_dst_begin  // start of data area (copy destination)
154
  la x13, __crt0_copy_data_dst_end    // last address of destination data area
155
 
156
__crt0_copy_data_loop:
157
  bge  x12, x13,  __crt0_copy_data_loop_end
158
  lb   x14, 0(x11)
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  sb   x14, 0(x12)
160
  addi x11, x11, 1
161
  addi x12, x12, 1
162
  j    __crt0_copy_data_loop
163
 
164
__crt0_copy_data_loop_end:
165
 
166
 
167
// *********************************************************
168
// Call main function (with argc = argv = 0)
169
// *********************************************************
170
__crt0_main_entry:
171
 
172
  addi x10, zero, 0 // argc = 0
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  addi x11, zero, 0 // argv = 0
174
 
175
  jal ra, main
176
 
177
 
178
// *********************************************************
179
// Go to endless sleep mode if main returns
180
// *********************************************************
181
__crt0_this_is_the_end:
182 11 zero_gravi
  csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)
183 2 zero_gravi
  wfi
184 11 zero_gravi
__crt0_this_is_the_end_end:
185
  j __crt0_this_is_the_end_end // in case Ziscr is not available
186 2 zero_gravi
 
187
 
188
// *********************************************************
189 14 zero_gravi
// dummy trap handler (for exceptions & IRQs)
190
// tries to move on to next instruction
191 2 zero_gravi
// *********************************************************
192 14 zero_gravi
  .global __crt0_dummy_trap_handler
193
  .balign 4
194
__crt0_dummy_trap_handler:
195 2 zero_gravi
 
196 14 zero_gravi
  addi  sp, sp, -8
197
  sw      x8, 0(sp)
198
  sw      x9, 4(sp)
199 2 zero_gravi
 
200 14 zero_gravi
  csrr  x8, mcause
201
  blt   x8, zero, __crt0_dummy_trap_handler_irq  // skip mepc modification if interrupt
202 2 zero_gravi
 
203 14 zero_gravi
__crt0_dummy_trap_handler_compute_return:
204
  csrr  x8, mepc
205 2 zero_gravi
 
206 14 zero_gravi
// is compressed instruction?
207
  lh    x9, 0(x8)   // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
208
  andi  x9, x9, 3   // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
209 2 zero_gravi
 
210 14 zero_gravi
  addi  x8, x8, +2  // only this for compressed instructions
211
  csrw  mepc, x8    // set return address when compressed instruction
212 2 zero_gravi
 
213 14 zero_gravi
  addi  x8, zero, 3
214
  bne   x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
215 7 zero_gravi
 
216 14 zero_gravi
// is uncompressed instruction
217
  csrr  x8, mepc
218
  addi  x8, x8, +2  // add another 2 (making +4) for uncompressed instructions
219
  csrw  mepc, x8
220 2 zero_gravi
 
221 14 zero_gravi
__crt0_dummy_trap_handler_irq:
222 2 zero_gravi
 
223 14 zero_gravi
  lw      x9, 0(sp)
224
  lw      x8, 4(sp)
225
  addi  sp, sp, +8
226 2 zero_gravi
 
227
  mret
228
 
229
  .cfi_endproc
230
  .end

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