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/* ################################################################################################# */
/* # << NEORV32 - crt0.S - Start-Up Code >>                                                        # */
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License                                                                          # */
/* #                                                                                               # */
/* # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     # */
/* #                                                                                               # */
/* # Redistribution and use in source and binary forms, with or without modification, are          # */
/* # permitted provided that the following conditions are met:                                     # */
/* #                                                                                               # */
/* # 1. Redistributions of source code must retain the above copyright notice, this list of        # */
/* #    conditions and the following disclaimer.                                                   # */
/* #                                                                                               # */
/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     # */
/* #    conditions and the following disclaimer in the documentation and/or other materials        # */
/* #    provided with the distribution.                                                            # */
/* #                                                                                               # */
/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  # */
/* #    endorse or promote products derived from this software without specific prior written      # */
/* #    permission.                                                                                # */
/* #                                                                                               # */
/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   # */
/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               # */
/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    # */
/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     # */
/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    # */
/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     # */
/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  # */
/* # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            # */
/* # ********************************************************************************************* # */
/* # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting # */
/* ################################################################################################# */
 
.file   "crt0.S"
.section .text.boot
.balign 4
.global _start
 
 
// IO region
.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
 
 
_start:
.cfi_startproc
.cfi_undefined ra
 
// *********************************************************
// Clear register file
// Assume 'worst case': rv32e
// *********************************************************
__crt0_reg_file_clear:
//addi  x0,  x0, 0 // hardwired to zero
  addi  x1,  x0, 0
  addi  x2,  x0, 0
  addi  x3,  x0, 0
  addi  x4,  x0, 0
  addi  x5,  x0, 0
  addi  x6,  x0, 0
  addi  x7,  x0, 0
  addi  x8,  x0, 0
  addi  x9,  x0, 0
//addi x10,  x0, 0
//addi x11,  x0, 0
//addi x12,  x0, 0
//addi x13,  x0, 0
  addi x14,  x0, 0
  addi x15,  x0, 0
 
 
// *********************************************************
// No interrupts, thanks
// *********************************************************
__crt0_status_init:
  li x10, 0x00001800    // clear mstatus and set mpp(1:0)
  csrrw zero, mstatus, x10
  csrrw zero, mie, zero // clear mie
 
 
// *********************************************************
// Setup pointers using linker script symbol
// *********************************************************
__crt0_pointer_init:
.option push
.option norelax
  la    sp, __crt0_stack_begin
  andi  sp, sp, 0xfffffffc // make sure this is aligned
  addi  fp, sp, 0          // frame pointer = stack pointer
  la gp, __global_pointer$ // global pointer
.option pop
 
 
// *********************************************************
// Init trap handler base address
// *********************************************************
__crt0_neorv32_trap_init:
  la    x11, __crt0_dummy_trap_handler
  csrw  mtvec, x11 // set address of first-level exception handler
 
 
// *********************************************************
// Reset/deactivate IO/peripheral devices
// Devices, that are not implemented, will cause a store access fault
// which is captured but actually ignored due to the dummy handler.
// *********************************************************
__crt0_reset_io:
  li x11, IO_BEGIN // start of processor-internal IO region
 
__crt0_reset_io_loop:
  sw   zero, 0(x11)
  addi x11, x11, 4
  bne  zero, x11, __crt0_reset_io_loop
 
 
// *********************************************************
// Clear .bss section (byte-wise) using linker script symbols
// *********************************************************
__crt0_clear_bss:
  la x11, __crt0_bss_start
  la x12, __crt0_bss_end
 
__crt0_clear_bss_loop:
  bge  x11, x12, __crt0_clear_bss_loop_end
  sb   zero, 0(x11)
  addi x11, x11, 1
  j    __crt0_clear_bss_loop
 
__crt0_clear_bss_loop_end:
 
 
// *********************************************************
// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols
// *********************************************************
__crt0_copy_data:
  la x11, __crt0_copy_data_src_begin  // start of data area (copy source)
  la x12, __crt0_copy_data_dst_begin  // start of data area (copy destination)
  la x13, __crt0_copy_data_dst_end    // last address of destination data area
 
__crt0_copy_data_loop:
  bge  x12, x13,  __crt0_copy_data_loop_end
  lb   x14, 0(x11)
  sb   x14, 0(x12)
  addi x11, x11, 1
  addi x12, x12, 1
  j    __crt0_copy_data_loop
 
__crt0_copy_data_loop_end:
 
 
// *********************************************************
// Call main function (with argc = argv = 0)
// *********************************************************
__crt0_main_entry:
 
  addi x10, zero, 0 // argc = 0
  addi x11, zero, 0 // argv = 0
 
  jal ra, main
 
 
// *********************************************************
// Go to endless sleep mode if main returns
// *********************************************************
__crt0_this_is_the_end:
  csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)
  wfi
  j . // in case WFI is not available
 
 
// *********************************************************
// dummy trap handler (for exceptions & IRQs)
// tries to move on to next instruction
// *********************************************************
.global __crt0_dummy_trap_handler
.balign 4
__crt0_dummy_trap_handler:
 
  addi  sp, sp, -8
  sw      x8, 0(sp)
  sw      x9, 4(sp)
 
  csrr  x8, mcause
  blt   x8, zero, __crt0_dummy_trap_handler_irq  // skip mepc modification if interrupt
 
  csrr  x8, mepc
 
// is compressed instruction?
__crt0_dummy_trap_handler_exc_c_check:
  lh    x9, 0(x8)   // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
  andi  x9, x9, 3   // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
 
  addi  x8, x8, +2  // only this for compressed instructions
  csrw  mepc, x8    // set return address when compressed instruction
 
  addi  x8, zero, 3
  bne   x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
 
// is uncompressed instruction
__crt0_dummy_trap_handler_exc_uncrompressed:
  csrr  x8, mepc
  addi  x8, x8, +2  // add another 2 (making +4) for uncompressed instructions
  csrw  mepc, x8
 
__crt0_dummy_trap_handler_irq:
 
  lw    x9, 0(sp)
  lw    x8, 4(sp)
  addi  sp, sp, +8
 
  mret
 
.cfi_endproc
.end

Line No.	Rev	Author	Line
1	2	zero_gravi	`/* ################################################################################################# */`
2	21	zero_gravi	`/* # << NEORV32 - crt0.S - Start-Up Code >> # */`
3	2	zero_gravi	`/* # ********************************************************************************************* # */`
4			`/* # BSD 3-Clause License # */`
5			`/* # # */`
6			`/* # Copyright (c) 2020, Stephan Nolting. All rights reserved. # */`
7			`/* # # */`
8			`/* # Redistribution and use in source and binary forms, with or without modification, are # */`
9			`/* # permitted provided that the following conditions are met: # */`
10			`/* # # */`
11			`/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */`
12			`/* # conditions and the following disclaimer. # */`
13			`/* # # */`
14			`/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */`
15			`/* # conditions and the following disclaimer in the documentation and/or other materials # */`
16			`/* # provided with the distribution. # */`
17			`/* # # */`
18			`/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */`
19			`/* # endorse or promote products derived from this software without specific prior written # */`
20			`/* # permission. # */`
21			`/* # # */`
22			`/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */`
23			`/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */`
24			`/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */`
25			`/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */`
26			`/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */`
27			`/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */`
28			`/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */`
29			`/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */`
30			`/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */`
31			`/* # ********************************************************************************************* # */`
32			`/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */`
33			`/* ################################################################################################# */`
34
35	21	zero_gravi	`.file "crt0.S"`
36			`.section .text.boot`
37			`.balign 4`
38			`.global _start`
39	2	zero_gravi
40
41	21	zero_gravi	`// IO region`
42			`.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region`
43	2	zero_gravi
44
45			`_start:`
46	21	zero_gravi	`.cfi_startproc`
47			`.cfi_undefined ra`
48	2	zero_gravi
49			`// *********************************************************`
50			`// Clear register file`
51	21	zero_gravi	`// Assume 'worst case': rv32e`
52	2	zero_gravi	`// *********************************************************`
53			`__crt0_reg_file_clear:`
54	14	zero_gravi	`//addi x0, x0, 0 // hardwired to zero`
55	2	zero_gravi	`addi x1, x0, 0`
56	20	zero_gravi	`addi x2, x0, 0`
57			`addi x3, x0, 0`
58			`addi x4, x0, 0`
59			`addi x5, x0, 0`
60			`addi x6, x0, 0`
61			`addi x7, x0, 0`
62			`addi x8, x0, 0`
63			`addi x9, x0, 0`
64			`//addi x10, x0, 0`
65			`//addi x11, x0, 0`
66			`//addi x12, x0, 0`
67	23	zero_gravi	`//addi x13, x0, 0`
68	21	zero_gravi	`addi x14, x0, 0`
69	20	zero_gravi	`addi x15, x0, 0`
70	2	zero_gravi
71
72			`// *********************************************************`
73	23	zero_gravi	`// No interrupts, thanks`
74	2	zero_gravi	`// *********************************************************`
75	23	zero_gravi	`__crt0_status_init:`
76			`li x10, 0x00001800 // clear mstatus and set mpp(1:0)`
77			`csrrw zero, mstatus, x10`
78			`csrrw zero, mie, zero // clear mie`
79	2	zero_gravi
80
81			`// *********************************************************`
82	23	zero_gravi	`// Setup pointers using linker script symbol`
83	2	zero_gravi	`// *********************************************************`
84	23	zero_gravi	`__crt0_pointer_init:`
85	21	zero_gravi	`.option push`
86			`.option norelax`
87	23	zero_gravi	`la sp, __crt0_stack_begin`
88			`andi sp, sp, 0xfffffffc // make sure this is aligned`
89			`addi fp, sp, 0 // frame pointer = stack pointer`
90			`la gp, __global_pointer$ // global pointer`
91	21	zero_gravi	`.option pop`
92	2	zero_gravi
93
94			`// *********************************************************`
95	14	zero_gravi	`// Init trap handler base address`
96	2	zero_gravi	`// *********************************************************`
97	14	zero_gravi	`__crt0_neorv32_trap_init:`
98			`la x11, __crt0_dummy_trap_handler`
99	6	zero_gravi	`csrw mtvec, x11 // set address of first-level exception handler`
100	2	zero_gravi
101
102			`// *********************************************************`
103			`// Reset/deactivate IO/peripheral devices`
104			`// Devices, that are not implemented, will cause a store access fault`
105			`// which is captured but actually ignored due to the dummy handler.`
106			`// *********************************************************`
107			`__crt0_reset_io:`
108			`li x11, IO_BEGIN // start of processor-internal IO region`
109
110			`__crt0_reset_io_loop:`
111			`sw zero, 0(x11)`
112			`addi x11, x11, 4`
113			`bne zero, x11, __crt0_reset_io_loop`
114
115
116			`// *********************************************************`
117	23	zero_gravi	`// Clear .bss section (byte-wise) using linker script symbols`
118	2	zero_gravi	`// *********************************************************`
119			`__crt0_clear_bss:`
120			`la x11, __crt0_bss_start`
121			`la x12, __crt0_bss_end`
122
123			`__crt0_clear_bss_loop:`
124			`bge x11, x12, __crt0_clear_bss_loop_end`
125			`sb zero, 0(x11)`
126			`addi x11, x11, 1`
127			`j __crt0_clear_bss_loop`
128
129			`__crt0_clear_bss_loop_end:`
130
131
132			`// *********************************************************`
133	23	zero_gravi	`// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols`
134	2	zero_gravi	`// *********************************************************`
135			`__crt0_copy_data:`
136			`la x11, __crt0_copy_data_src_begin // start of data area (copy source)`
137			`la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)`
138			`la x13, __crt0_copy_data_dst_end // last address of destination data area`
139
140			`__crt0_copy_data_loop:`
141			`bge x12, x13, __crt0_copy_data_loop_end`
142			`lb x14, 0(x11)`
143			`sb x14, 0(x12)`
144			`addi x11, x11, 1`
145			`addi x12, x12, 1`
146			`j __crt0_copy_data_loop`
147
148			`__crt0_copy_data_loop_end:`
149
150
151			`// *********************************************************`
152			`// Call main function (with argc = argv = 0)`
153			`// *********************************************************`
154			`__crt0_main_entry:`
155
156			`addi x10, zero, 0 // argc = 0`
157			`addi x11, zero, 0 // argv = 0`
158
159			`jal ra, main`
160
161
162			`// *********************************************************`
163			`// Go to endless sleep mode if main returns`
164			`// *********************************************************`
165			`__crt0_this_is_the_end:`
166	11	zero_gravi	`csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)`
167	2	zero_gravi	`wfi`
168	21	zero_gravi	`j . // in case WFI is not available`
169	2	zero_gravi
170
171			`// *********************************************************`
172	14	zero_gravi	`// dummy trap handler (for exceptions & IRQs)`
173			`// tries to move on to next instruction`
174	2	zero_gravi	`// *********************************************************`
175	21	zero_gravi	`.global __crt0_dummy_trap_handler`
176			`.balign 4`
177	14	zero_gravi	`__crt0_dummy_trap_handler:`
178	2	zero_gravi
179	14	zero_gravi	`addi sp, sp, -8`
180			`sw x8, 0(sp)`
181			`sw x9, 4(sp)`
182	2	zero_gravi
183	14	zero_gravi	`csrr x8, mcause`
184			`blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt`
185	2	zero_gravi
186	14	zero_gravi	`csrr x8, mepc`
187	2	zero_gravi
188	14	zero_gravi	`// is compressed instruction?`
189	23	zero_gravi	`__crt0_dummy_trap_handler_exc_c_check:`
190	14	zero_gravi	`lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception`
191			`andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)`
192	2	zero_gravi
193	14	zero_gravi	`addi x8, x8, +2 // only this for compressed instructions`
194			`csrw mepc, x8 // set return address when compressed instruction`
195	2	zero_gravi
196	14	zero_gravi	`addi x8, zero, 3`
197			`bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction`
198	7	zero_gravi
199	14	zero_gravi	`// is uncompressed instruction`
200	23	zero_gravi	`__crt0_dummy_trap_handler_exc_uncrompressed:`
201	14	zero_gravi	`csrr x8, mepc`
202			`addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions`
203			`csrw mepc, x8`
204	2	zero_gravi
205	14	zero_gravi	`__crt0_dummy_trap_handler_irq:`
206	2	zero_gravi
207	23	zero_gravi	`lw x9, 0(sp)`
208			`lw x8, 4(sp)`
209			`addi sp, sp, +8`
210	2	zero_gravi
211			`mret`
212
213	21	zero_gravi	`.cfi_endproc`
214			`.end`

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[/] [neorv32/] [trunk/] [sw/] [common/] [crt0.S] - Blame information for rev 23