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/* ################################################################################################# */
/* # << NEORV32 - crt0.S - Start-Up Code >>                                                        # */
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License                                                                          # */
/* #                                                                                               # */
/* # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     # */
/* #                                                                                               # */
/* # Redistribution and use in source and binary forms, with or without modification, are          # */
/* # permitted provided that the following conditions are met:                                     # */
/* #                                                                                               # */
/* # 1. Redistributions of source code must retain the above copyright notice, this list of        # */
/* #    conditions and the following disclaimer.                                                   # */
/* #                                                                                               # */
/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     # */
/* #    conditions and the following disclaimer in the documentation and/or other materials        # */
/* #    provided with the distribution.                                                            # */
/* #                                                                                               # */
/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  # */
/* #    endorse or promote products derived from this software without specific prior written      # */
/* #    permission.                                                                                # */
/* #                                                                                               # */
/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   # */
/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               # */
/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    # */
/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     # */
/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    # */
/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     # */
/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  # */
/* # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            # */
/* # ********************************************************************************************* # */
/* # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting # */
/* ################################################################################################# */
 
.file   "crt0.S"
.section .text.boot
.balign 4
.global _start
 
 
// IO region
.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
 
 
_start:
.cfi_startproc
.cfi_undefined ra
 
// *********************************************************
// Clear register file (lower half, assume E extension)
// *********************************************************
__crt0_reg_file_clear:
//addi  x0, x0, 0 // hardwired to zero
  addi  x1, x0, 0
  addi  x2, x0, 0
  addi  x3, x0, 0
  addi  x4, x0, 0
  addi  x5, x0, 0
  addi  x6, x0, 0
  addi  x7, x0, 0
  addi  x8, x0, 0
  addi  x9, x0, 0
//addi x10, x0, 0
//addi x11, x0, 0
//addi x12, x0, 0
//addi x13, x0, 0
  addi x14, x0, 0
  addi x15, x0, 0
 
 
// *********************************************************
// Clear register file (upper half, if no E extension)
// *********************************************************
#ifndef __riscv_32e
// save some program space if compiling bootloader
#ifndef make_bootloader
  addi x16, x0, 0
  addi x17, x0, 0
  addi x18, x0, 0
  addi x19, x0, 0
  addi x20, x0, 0
  addi x21, x0, 0
  addi x22, x0, 0
  addi x23, x0, 0
  addi x24, x0, 0
  addi x25, x0, 0
  addi x26, x0, 0
  addi x27, x0, 0
  addi x28, x0, 0
  addi x29, x0, 0
  addi x30, x0, 0
  addi x31, x0, 0
#endif
#endif
 
 
// *********************************************************
// No interrupts, thanks
// *********************************************************
__crt0_status_init:
  li x10, 0x00001800    // clear mstatus and set mpp(1:0)
  csrrw zero, mstatus, x10
  csrrw zero, mie, zero // clear mie
 
 
// *********************************************************
// Setup pointers using linker script symbols
// *********************************************************
__crt0_pointer_init:
.option push
.option norelax
  la    sp, __crt0_stack_begin
  andi  sp, sp, 0xfffffffc // make sure this is aligned
  addi  fp, sp, 0          // frame pointer = stack pointer
  la gp, __global_pointer$ // global pointer
.option pop
 
 
// *********************************************************
// Initialize dummy trap handler base address
// *********************************************************
__crt0_neorv32_trap_init:
  la    x11, __crt0_dummy_trap_handler
  csrw  mtvec, x11 // set address of first-level exception handler
 
 
// *********************************************************
// Reset/deactivate IO/peripheral devices
// Devices, that are not implemented, will cause a store access fault
// which is captured but actually ignored due to the dummy handler.
// *********************************************************
__crt0_reset_io:
  li x11, IO_BEGIN // start of processor-internal IO region
 
__crt0_reset_io_loop:
  sw   zero, 0(x11)
  addi x11, x11, 4
  bne  zero, x11, __crt0_reset_io_loop
 
 
// *********************************************************
// Clear .bss section (byte-wise) using linker script symbols
// *********************************************************
__crt0_clear_bss:
  la x11, __crt0_bss_start
  la x12, __crt0_bss_end
 
__crt0_clear_bss_loop:
  bge  x11, x12, __crt0_clear_bss_loop_end
  sb   zero, 0(x11)
  addi x11, x11, 1
  j    __crt0_clear_bss_loop
 
__crt0_clear_bss_loop_end:
 
 
// *********************************************************
// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols
// *********************************************************
__crt0_copy_data:
  la x11, __crt0_copy_data_src_begin  // start of data area (copy source)
  la x12, __crt0_copy_data_dst_begin  // start of data area (copy destination)
  la x13, __crt0_copy_data_dst_end    // last address of destination data area
 
__crt0_copy_data_loop:
  bge  x12, x13,  __crt0_copy_data_loop_end
  lb   x14, 0(x11)
  sb   x14, 0(x12)
  addi x11, x11, 1
  addi x12, x12, 1
  j    __crt0_copy_data_loop
 
__crt0_copy_data_loop_end:
 
 
// *********************************************************
// Call main function
// *********************************************************
__crt0_main_entry:
 
  // setup arguments for calling main
  addi x10, zero, 0 // argc = 0
  addi x11, zero, 0 // argv = 0
 
  // clear cycle and instruction counters
  csrw mcycle,    zero
  csrw mcycleh,   zero
  csrw minstret,  zero
  csrw minstreth, zero
  // enable read-access from user-mode for cycle[h], time[h] and instret[h]
  csrwi 0x306, 7 // mcounteren
  // enable auto-increment of all counters
  csrw 0x320, x0 // mcountinhibit
 
  // restore mcause reset value (so that 'main' knows we are coming from reset)
  li x12, 0x80000000
  csrw mcause, x12
 
  // call actual app's main function
  jal ra, main
 
 
// *********************************************************
// Go to endless sleep mode if main returns
// *********************************************************
__crt0_this_is_the_end:
  csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)
  nop
  wfi
__crt0_this_is_the_end_my_friend:
  j __crt0_this_is_the_end_my_friend // in case WFI is not available
 
 
// *********************************************************
// dummy trap handler (for exceptions & IRQs)
// tries to move on to next instruction
// *********************************************************
.global __crt0_dummy_trap_handler
.balign 4
__crt0_dummy_trap_handler:
 
  addi  sp, sp, -8
  sw      x8, 0(sp)
  sw      x9, 4(sp)
 
  csrr  x8, mcause
  blt   x8, zero, __crt0_dummy_trap_handler_irq  // skip mepc modification if interrupt
 
  csrr  x8, mepc
 
// is compressed instruction?
__crt0_dummy_trap_handler_exc_c_check:
  lh    x9, 0(x8)   // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
  andi  x9, x9, 3   // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
 
  addi  x8, x8, +2  // only this for compressed instructions
  csrw  mepc, x8    // set return address when compressed instruction
 
  addi  x8, zero, 3
  bne   x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
 
// is uncompressed instruction
__crt0_dummy_trap_handler_exc_uncrompressed:
  csrr  x8, mepc
  addi  x8, x8, +2  // add another 2 (making +4) for uncompressed instructions
  csrw  mepc, x8
 
__crt0_dummy_trap_handler_irq:
 
  lw    x9, 0(sp)
  lw    x8, 4(sp)
  addi  sp, sp, +8
 
  mret
 
.cfi_endproc
.end

Line No.	Rev	Author	Line
1	2	zero_gravi	`/* ################################################################################################# */`
2	21	zero_gravi	`/* # << NEORV32 - crt0.S - Start-Up Code >> # */`
3	2	zero_gravi	`/* # ********************************************************************************************* # */`
4			`/* # BSD 3-Clause License # */`
5			`/* # # */`
6			`/* # Copyright (c) 2020, Stephan Nolting. All rights reserved. # */`
7			`/* # # */`
8			`/* # Redistribution and use in source and binary forms, with or without modification, are # */`
9			`/* # permitted provided that the following conditions are met: # */`
10			`/* # # */`
11			`/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */`
12			`/* # conditions and the following disclaimer. # */`
13			`/* # # */`
14			`/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */`
15			`/* # conditions and the following disclaimer in the documentation and/or other materials # */`
16			`/* # provided with the distribution. # */`
17			`/* # # */`
18			`/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */`
19			`/* # endorse or promote products derived from this software without specific prior written # */`
20			`/* # permission. # */`
21			`/* # # */`
22			`/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */`
23			`/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */`
24			`/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */`
25			`/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */`
26			`/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */`
27			`/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */`
28			`/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */`
29			`/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */`
30			`/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */`
31			`/* # ********************************************************************************************* # */`
32			`/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */`
33			`/* ################################################################################################# */`
34
35	21	zero_gravi	`.file "crt0.S"`
36			`.section .text.boot`
37			`.balign 4`
38			`.global _start`
39	2	zero_gravi
40
41	21	zero_gravi	`// IO region`
42			`.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region`
43	2	zero_gravi
44
45			`_start:`
46	21	zero_gravi	`.cfi_startproc`
47			`.cfi_undefined ra`
48	2	zero_gravi
49			`// *********************************************************`
50	32	zero_gravi	`// Clear register file (lower half, assume E extension)`
51	2	zero_gravi	`// *********************************************************`
52			`__crt0_reg_file_clear:`
53	32	zero_gravi	`//addi x0, x0, 0 // hardwired to zero`
54			`addi x1, x0, 0`
55			`addi x2, x0, 0`
56			`addi x3, x0, 0`
57			`addi x4, x0, 0`
58			`addi x5, x0, 0`
59			`addi x6, x0, 0`
60			`addi x7, x0, 0`
61			`addi x8, x0, 0`
62			`addi x9, x0, 0`
63			`//addi x10, x0, 0`
64			`//addi x11, x0, 0`
65			`//addi x12, x0, 0`
66			`//addi x13, x0, 0`
67			`addi x14, x0, 0`
68			`addi x15, x0, 0`
69	2	zero_gravi
70
71			`// *********************************************************`
72	32	zero_gravi	`// Clear register file (upper half, if no E extension)`
73			`// *********************************************************`
74			`#ifndef __riscv_32e`
75			`// save some program space if compiling bootloader`
76			`#ifndef make_bootloader`
77			`addi x16, x0, 0`
78			`addi x17, x0, 0`
79			`addi x18, x0, 0`
80			`addi x19, x0, 0`
81			`addi x20, x0, 0`
82			`addi x21, x0, 0`
83			`addi x22, x0, 0`
84			`addi x23, x0, 0`
85			`addi x24, x0, 0`
86			`addi x25, x0, 0`
87			`addi x26, x0, 0`
88			`addi x27, x0, 0`
89			`addi x28, x0, 0`
90			`addi x29, x0, 0`
91			`addi x30, x0, 0`
92			`addi x31, x0, 0`
93			`#endif`
94			`#endif`
95
96
97			`// *********************************************************`
98	23	zero_gravi	`// No interrupts, thanks`
99	2	zero_gravi	`// *********************************************************`
100	23	zero_gravi	`__crt0_status_init:`
101			`li x10, 0x00001800 // clear mstatus and set mpp(1:0)`
102			`csrrw zero, mstatus, x10`
103			`csrrw zero, mie, zero // clear mie`
104	2	zero_gravi
105
106			`// *********************************************************`
107	39	zero_gravi	`// Setup pointers using linker script symbols`
108	2	zero_gravi	`// *********************************************************`
109	23	zero_gravi	`__crt0_pointer_init:`
110	21	zero_gravi	`.option push`
111			`.option norelax`
112	23	zero_gravi	`la sp, __crt0_stack_begin`
113			`andi sp, sp, 0xfffffffc // make sure this is aligned`
114			`addi fp, sp, 0 // frame pointer = stack pointer`
115			`la gp, __global_pointer$ // global pointer`
116	21	zero_gravi	`.option pop`
117	2	zero_gravi
118
119			`// *********************************************************`
120	39	zero_gravi	`// Initialize dummy trap handler base address`
121	2	zero_gravi	`// *********************************************************`
122	14	zero_gravi	`__crt0_neorv32_trap_init:`
123			`la x11, __crt0_dummy_trap_handler`
124	6	zero_gravi	`csrw mtvec, x11 // set address of first-level exception handler`
125	2	zero_gravi
126
127			`// *********************************************************`
128			`// Reset/deactivate IO/peripheral devices`
129			`// Devices, that are not implemented, will cause a store access fault`
130			`// which is captured but actually ignored due to the dummy handler.`
131			`// *********************************************************`
132			`__crt0_reset_io:`
133			`li x11, IO_BEGIN // start of processor-internal IO region`
134
135			`__crt0_reset_io_loop:`
136			`sw zero, 0(x11)`
137			`addi x11, x11, 4`
138			`bne zero, x11, __crt0_reset_io_loop`
139
140
141			`// *********************************************************`
142	23	zero_gravi	`// Clear .bss section (byte-wise) using linker script symbols`
143	2	zero_gravi	`// *********************************************************`
144			`__crt0_clear_bss:`
145			`la x11, __crt0_bss_start`
146			`la x12, __crt0_bss_end`
147
148			`__crt0_clear_bss_loop:`
149			`bge x11, x12, __crt0_clear_bss_loop_end`
150			`sb zero, 0(x11)`
151			`addi x11, x11, 1`
152			`j __crt0_clear_bss_loop`
153
154			`__crt0_clear_bss_loop_end:`
155
156
157			`// *********************************************************`
158	23	zero_gravi	`// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols`
159	2	zero_gravi	`// *********************************************************`
160			`__crt0_copy_data:`
161			`la x11, __crt0_copy_data_src_begin // start of data area (copy source)`
162			`la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)`
163			`la x13, __crt0_copy_data_dst_end // last address of destination data area`
164
165			`__crt0_copy_data_loop:`
166			`bge x12, x13, __crt0_copy_data_loop_end`
167			`lb x14, 0(x11)`
168			`sb x14, 0(x12)`
169			`addi x11, x11, 1`
170			`addi x12, x12, 1`
171			`j __crt0_copy_data_loop`
172
173			`__crt0_copy_data_loop_end:`
174
175
176			`// *********************************************************`
177	39	zero_gravi	`// Call main function`
178	2	zero_gravi	`// *********************************************************`
179			`__crt0_main_entry:`
180
181	39	zero_gravi	`// setup arguments for calling main`
182	2	zero_gravi	`addi x10, zero, 0 // argc = 0`
183			`addi x11, zero, 0 // argv = 0`
184
185	39	zero_gravi	`// clear cycle and instruction counters`
186			`csrw mcycle, zero`
187			`csrw mcycleh, zero`
188			`csrw minstret, zero`
189			`csrw minstreth, zero`
190	41	zero_gravi	`// enable read-access from user-mode for cycle[h], time[h] and instret[h]`
191			`csrwi 0x306, 7 // mcounteren`
192			`// enable auto-increment of all counters`
193			`csrw 0x320, x0 // mcountinhibit`
194	39	zero_gravi
195	40	zero_gravi	`// restore mcause reset value (so that 'main' knows we are coming from reset)`
196			`li x12, 0x80000000`
197			`csrw mcause, x12`
198
199			`// call actual app's main function`
200	2	zero_gravi	`jal ra, main`
201
202
203			`// *********************************************************`
204			`// Go to endless sleep mode if main returns`
205			`// *********************************************************`
206			`__crt0_this_is_the_end:`
207	11	zero_gravi	`csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)`
208	39	zero_gravi	`nop`
209	2	zero_gravi	`wfi`
210	39	zero_gravi	`__crt0_this_is_the_end_my_friend:`
211			`j __crt0_this_is_the_end_my_friend // in case WFI is not available`
212	2	zero_gravi
213
214			`// *********************************************************`
215	14	zero_gravi	`// dummy trap handler (for exceptions & IRQs)`
216			`// tries to move on to next instruction`
217	2	zero_gravi	`// *********************************************************`
218	21	zero_gravi	`.global __crt0_dummy_trap_handler`
219			`.balign 4`
220	14	zero_gravi	`__crt0_dummy_trap_handler:`
221	2	zero_gravi
222	14	zero_gravi	`addi sp, sp, -8`
223			`sw x8, 0(sp)`
224			`sw x9, 4(sp)`
225	2	zero_gravi
226	14	zero_gravi	`csrr x8, mcause`
227			`blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt`
228	2	zero_gravi
229	14	zero_gravi	`csrr x8, mepc`
230	2	zero_gravi
231	14	zero_gravi	`// is compressed instruction?`
232	23	zero_gravi	`__crt0_dummy_trap_handler_exc_c_check:`
233	14	zero_gravi	`lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception`
234			`andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)`
235	2	zero_gravi
236	14	zero_gravi	`addi x8, x8, +2 // only this for compressed instructions`
237			`csrw mepc, x8 // set return address when compressed instruction`
238	2	zero_gravi
239	14	zero_gravi	`addi x8, zero, 3`
240			`bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction`
241	7	zero_gravi
242	14	zero_gravi	`// is uncompressed instruction`
243	23	zero_gravi	`__crt0_dummy_trap_handler_exc_uncrompressed:`
244	14	zero_gravi	`csrr x8, mepc`
245			`addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions`
246			`csrw mepc, x8`
247	2	zero_gravi
248	14	zero_gravi	`__crt0_dummy_trap_handler_irq:`
249	2	zero_gravi
250	23	zero_gravi	`lw x9, 0(sp)`
251			`lw x8, 4(sp)`
252			`addi sp, sp, +8`
253	2	zero_gravi
254			`mret`
255
256	21	zero_gravi	`.cfi_endproc`
257			`.end`

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