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[/] [neorv32/] [trunk/] [sw/] [common/] [crt0.S] - Blame information for rev 58

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1 2 zero_gravi
/* ################################################################################################# */
2 21 zero_gravi
/* # << NEORV32 - crt0.S - Start-Up Code >>                                                        # */
3 2 zero_gravi
/* # ********************************************************************************************* # */
4
/* # BSD 3-Clause License                                                                          # */
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/* #                                                                                               # */
6 53 zero_gravi
/* # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     # */
7 2 zero_gravi
/* #                                                                                               # */
8
/* # Redistribution and use in source and binary forms, with or without modification, are          # */
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/* # permitted provided that the following conditions are met:                                     # */
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/* #                                                                                               # */
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/* # 1. Redistributions of source code must retain the above copyright notice, this list of        # */
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/* #    conditions and the following disclaimer.                                                   # */
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/* #                                                                                               # */
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/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     # */
15
/* #    conditions and the following disclaimer in the documentation and/or other materials        # */
16
/* #    provided with the distribution.                                                            # */
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/* #                                                                                               # */
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/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  # */
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/* #    endorse or promote products derived from this software without specific prior written      # */
20
/* #    permission.                                                                                # */
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/* #                                                                                               # */
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/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   # */
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/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               # */
24
/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    # */
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/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     # */
26
/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
27
/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    # */
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/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     # */
29
/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  # */
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/* # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            # */
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/* # ********************************************************************************************* # */
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/* # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting # */
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/* ################################################################################################# */
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35 21 zero_gravi
.file   "crt0.S"
36
.section .text.boot
37
.balign 4
38
.global _start
39 2 zero_gravi
 
40
 
41
_start:
42 21 zero_gravi
.cfi_startproc
43
.cfi_undefined ra
44 2 zero_gravi
 
45
// *********************************************************
46 52 zero_gravi
// Clear integer register file (lower half, assume E extension)
47 2 zero_gravi
// *********************************************************
48
__crt0_reg_file_clear:
49 32 zero_gravi
//addi  x0, x0, 0 // hardwired to zero
50
  addi  x1, x0, 0
51
  addi  x2, x0, 0
52
  addi  x3, x0, 0
53
  addi  x4, x0, 0
54
  addi  x5, x0, 0
55
  addi  x6, x0, 0
56
  addi  x7, x0, 0
57 58 zero_gravi
//addi  x8, x0, 0
58
//addi  x9, x0, 0
59 32 zero_gravi
//addi x10, x0, 0
60
//addi x11, x0, 0
61
//addi x12, x0, 0
62
//addi x13, x0, 0
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  addi x14, x0, 0
64
  addi x15, x0, 0
65 2 zero_gravi
 
66
 
67
// *********************************************************
68 56 zero_gravi
// Setup pointers using linker script symbols
69 32 zero_gravi
// *********************************************************
70 56 zero_gravi
__crt0_pointer_init:
71
.option push
72
.option norelax
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  la    sp, __crt0_stack_begin
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  andi  sp, sp, 0xfffffffc // make sure this is aligned
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  addi  fp, sp, 0          // frame pointer = stack pointer
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  la gp, __global_pointer$ // global pointer
77
.option pop
78 52 zero_gravi
 
79
 
80
// *********************************************************
81 56 zero_gravi
// Setup CPU core CSRs (some of them DO NOT have a dedicated reset and need to be explicitly initialized)
82
// *********************************************************
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__crt0_cpu_csr_init:
84
 
85
  // set address of first-level exception handler
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  la   x10, __crt0_dummy_trap_handler
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  csrw mtvec,  x10
88
  csrw mepc,   x10
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  csrw mtval,  zero
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  csrw mcause, zero
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92
  // no global IRQ enable (is also done by hardware)
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  csrw mstatus, zero
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95
  // absolutely no interrupts, thanks
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  csrw mie, zero
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98
  // no access from less-privileged modes to counter CSRs
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  csrw mcounteren, zero
100
 
101
  // stop all counters except for [m]cycle[h] and [m]instret[h]
102
  li   x11, ~5
103 58 zero_gravi
  csrw 0x320, x11 // mcountinhibit (literal address for lagacy toolchain compatibility)
104 56 zero_gravi
 
105
  // clear cycle counters
106 58 zero_gravi
  csrw mcycle,  zero
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  csrw mcycleh, zero
108 56 zero_gravi
 
109
  // clear instruction counters
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  csrw minstret,  zero
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  csrw minstreth, zero
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113
#if defined(__riscv_flen) && (__riscv_flen != 0)
114
  // clear floating-point CSR (rounding mode & exception flags)
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  csrw fcsr, zero
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#endif
117
 
118
 
119
// *********************************************************
120 52 zero_gravi
// Clear integer register file (upper half, if no E extension)
121
// *********************************************************
122 32 zero_gravi
#ifndef __riscv_32e
123 52 zero_gravi
// DO NOT DO THIS if compiling bootloader (to save some program space)
124 32 zero_gravi
#ifndef make_bootloader
125
  addi x16, x0, 0
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  addi x17, x0, 0
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  addi x18, x0, 0
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  addi x19, x0, 0
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  addi x20, x0, 0
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  addi x21, x0, 0
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  addi x22, x0, 0
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  addi x23, x0, 0
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  addi x24, x0, 0
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  addi x25, x0, 0
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  addi x26, x0, 0
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  addi x27, x0, 0
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  addi x28, x0, 0
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  addi x29, x0, 0
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  addi x30, x0, 0
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  addi x31, x0, 0
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#endif
142
#endif
143
 
144
 
145
// *********************************************************
146 2 zero_gravi
// Reset/deactivate IO/peripheral devices
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// Devices, that are not implemented, will cause a store access fault
148
// which is captured but actually ignored due to the dummy handler.
149
// *********************************************************
150
__crt0_reset_io:
151 58 zero_gravi
  la x8, __ctr0_io_space_begin // start of processor-internal IO region
152
  la x9, __ctr0_io_space_end   // end of processor-internal IO region
153 2 zero_gravi
 
154
__crt0_reset_io_loop:
155 58 zero_gravi
  sw   zero, 0(x8)
156
  addi x8,   x8, 4
157
  bne  x8,   x9, __crt0_reset_io_loop
158 2 zero_gravi
 
159
 
160
// *********************************************************
161 23 zero_gravi
// Clear .bss section (byte-wise) using linker script symbols
162 2 zero_gravi
// *********************************************************
163
__crt0_clear_bss:
164
  la x11, __crt0_bss_start
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  la x12, __crt0_bss_end
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167
__crt0_clear_bss_loop:
168
  bge  x11, x12, __crt0_clear_bss_loop_end
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  sb   zero, 0(x11)
170
  addi x11, x11, 1
171
  j    __crt0_clear_bss_loop
172
 
173
__crt0_clear_bss_loop_end:
174
 
175
 
176
// *********************************************************
177 23 zero_gravi
// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols
178 2 zero_gravi
// *********************************************************
179
__crt0_copy_data:
180
  la x11, __crt0_copy_data_src_begin  // start of data area (copy source)
181
  la x12, __crt0_copy_data_dst_begin  // start of data area (copy destination)
182
  la x13, __crt0_copy_data_dst_end    // last address of destination data area
183
 
184
__crt0_copy_data_loop:
185
  bge  x12, x13,  __crt0_copy_data_loop_end
186
  lb   x14, 0(x11)
187
  sb   x14, 0(x12)
188
  addi x11, x11, 1
189
  addi x12, x12, 1
190
  j    __crt0_copy_data_loop
191
 
192
__crt0_copy_data_loop_end:
193
 
194
 
195
// *********************************************************
196 39 zero_gravi
// Call main function
197 2 zero_gravi
// *********************************************************
198
__crt0_main_entry:
199
 
200 39 zero_gravi
  // setup arguments for calling main
201 2 zero_gravi
  addi x10, zero, 0 // argc = 0
202
  addi x11, zero, 0 // argv = 0
203
 
204 40 zero_gravi
  // call actual app's main function
205 2 zero_gravi
  jal ra, main
206
 
207
 
208
// *********************************************************
209
// Go to endless sleep mode if main returns
210
// *********************************************************
211
__crt0_this_is_the_end:
212 11 zero_gravi
  csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)
213 39 zero_gravi
  nop
214 2 zero_gravi
  wfi
215 39 zero_gravi
__crt0_this_is_the_end_my_friend:
216
  j __crt0_this_is_the_end_my_friend // in case WFI is not available
217 2 zero_gravi
 
218
 
219
// *********************************************************
220 14 zero_gravi
// dummy trap handler (for exceptions & IRQs)
221
// tries to move on to next instruction
222 2 zero_gravi
// *********************************************************
223 21 zero_gravi
.global __crt0_dummy_trap_handler
224
.balign 4
225 14 zero_gravi
__crt0_dummy_trap_handler:
226 2 zero_gravi
 
227 14 zero_gravi
  addi  sp, sp, -8
228
  sw      x8, 0(sp)
229
  sw      x9, 4(sp)
230 2 zero_gravi
 
231 14 zero_gravi
  csrr  x8, mcause
232
  blt   x8, zero, __crt0_dummy_trap_handler_irq  // skip mepc modification if interrupt
233 2 zero_gravi
 
234 14 zero_gravi
  csrr  x8, mepc
235 2 zero_gravi
 
236 14 zero_gravi
// is compressed instruction?
237 23 zero_gravi
__crt0_dummy_trap_handler_exc_c_check:
238 14 zero_gravi
  lh    x9, 0(x8)   // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
239
  andi  x9, x9, 3   // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
240 2 zero_gravi
 
241 14 zero_gravi
  addi  x8, x8, +2  // only this for compressed instructions
242
  csrw  mepc, x8    // set return address when compressed instruction
243 2 zero_gravi
 
244 14 zero_gravi
  addi  x8, zero, 3
245
  bne   x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
246 7 zero_gravi
 
247 14 zero_gravi
// is uncompressed instruction
248 23 zero_gravi
__crt0_dummy_trap_handler_exc_uncrompressed:
249 14 zero_gravi
  csrr  x8, mepc
250
  addi  x8, x8, +2  // add another 2 (making +4) for uncompressed instructions
251
  csrw  mepc, x8
252 2 zero_gravi
 
253 14 zero_gravi
__crt0_dummy_trap_handler_irq:
254 2 zero_gravi
 
255 53 zero_gravi
  lw    x8, 0(sp)
256
  lw    x9, 4(sp)
257 23 zero_gravi
  addi  sp, sp, +8
258 2 zero_gravi
 
259
  mret
260
 
261 21 zero_gravi
.cfi_endproc
262
.end

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