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/* ################################################################################################# */
/* # << NEORV32 - crt0.S - Start-Up Code >>                                                        # */
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License                                                                          # */
/* #                                                                                               # */
/* # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     # */
/* #                                                                                               # */
/* # Redistribution and use in source and binary forms, with or without modification, are          # */
/* # permitted provided that the following conditions are met:                                     # */
/* #                                                                                               # */
/* # 1. Redistributions of source code must retain the above copyright notice, this list of        # */
/* #    conditions and the following disclaimer.                                                   # */
/* #                                                                                               # */
/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     # */
/* #    conditions and the following disclaimer in the documentation and/or other materials        # */
/* #    provided with the distribution.                                                            # */
/* #                                                                                               # */
/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  # */
/* #    endorse or promote products derived from this software without specific prior written      # */
/* #    permission.                                                                                # */
/* #                                                                                               # */
/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   # */
/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               # */
/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    # */
/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     # */
/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    # */
/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     # */
/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  # */
/* # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            # */
/* # ********************************************************************************************* # */
/* # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting # */
/* ################################################################################################# */
 
.file   "crt0.S"
.section .text.boot
.balign 4
.global _start
 
 
_start:
.cfi_startproc
.cfi_undefined ra
 
 
// ************************************************************************************************
// This is the very first instruction that is executed after hardware reset. It ensures that x0 is
// written at least once - the CPU HW will ensure it is always set to zero on any write access.
// ************************************************************************************************
  lui zero, 0 // "dummy" instruction that uses no reg-file input operands at all
 
 
// ************************************************************************************************
// Setup pointers using linker script symbols
// ************************************************************************************************
__crt0_pointer_init:
  .option push
  .option norelax
 
  la sp, __crt0_stack_begin  // stack pointer
  la gp, __global_pointer$   // global pointer
 
  .option pop
 
 
// ************************************************************************************************
// Setup CPU core CSRs (some of them DO NOT have a dedicated
// reset and need to be explicitly initialized)
// ************************************************************************************************
__crt0_cpu_csr_init:
 
  la   x10,   __crt0_dummy_trap_handler // configure early trap handler
  csrw mtvec, x10
  csrw mepc,  x10                       // just to init mepc
 
  csrw mstatus, zero                    // disable global IRQ
 
  csrw mie, zero                        // absolutely no interrupts sources, thanks
 
  csrw mcounteren, zero                 // no access from less-privileged modes to counter CSRs
 
  li   x11,   ~5                        // stop all counters except for [m]cycle[h] and [m]instret[h]
  csrw 0x320, x11                       // = mcountinhibit (literal address for lagacy toolchain compatibility)
 
  csrw mcycle,    zero                  // reset cycle counters
  csrw mcycleh,   zero
  csrw minstret,  zero                  // reset instruction counters
  csrw minstreth, zero
 
 
// ************************************************************************************************
// Initialize integer register file (lower half)
// ************************************************************************************************
__crt0_reg_file_clear:
//addi  x0, x0, 0 // hardwired to zero
  addi  x1, x0, 0
//addi  x2, x0, 0 // stack pointer sp
//addi  x3, x0, 0 // gloabl pointer gp
  addi  x4, x0, 0
  addi  x5, x0, 0
  addi  x6, x0, 0
  addi  x7, x0, 0
//addi  x8, x0, 0 // initialized within crt0
//addi  x9, x0, 0 // initialized within crt0
//addi x10, x0, 0 // initialized within crt0
//addi x11, x0, 0 // initialized within crt0
//addi x12, x0, 0 // initialized within crt0
//addi x13, x0, 0 // initialized within crt0
  addi x14, x0, 0
  addi x15, x0, 0
 
 
// ************************************************************************************************
// Initialize integer register file (upper half, if no E extension)
// ************************************************************************************************
#ifndef __riscv_32e
// do not do this if compiling bootloader (to save some program space)
#ifndef make_bootloader
  addi x16, x0, 0
  addi x17, x0, 0
  addi x18, x0, 0
  addi x19, x0, 0
  addi x20, x0, 0
  addi x21, x0, 0
  addi x22, x0, 0
  addi x23, x0, 0
  addi x24, x0, 0
  addi x25, x0, 0
  addi x26, x0, 0
  addi x27, x0, 0
  addi x28, x0, 0
  addi x29, x0, 0
  addi x30, x0, 0
  addi x31, x0, 0
#endif
#endif
 
 
// ************************************************************************************************
// Reset/deactivate IO/peripheral devices
// Devices, that are not implemented, will cause a store bus access fault
// which is captured (but actually ignored) by the dummy trap handler.
// ************************************************************************************************
__crt0_reset_io:
  la   x8,   __ctr0_io_space_begin         // start of processor-internal IO region
  la   x9,   __ctr0_io_space_end           // end of processor-internal IO region
 
__crt0_reset_io_loop:
  sw   zero, 0(x8)
  addi x8,   x8, 4
  bne  x8,   x9, __crt0_reset_io_loop
 
 
// ************************************************************************************************
// Clear .bss section (byte-wise) using linker script symbols
// ************************************************************************************************
__crt0_clear_bss:
  la   x11,  __crt0_bss_start
  la   x12,  __crt0_bss_end
 
__crt0_clear_bss_loop:
  bge  x11,  x12, __crt0_clear_bss_loop_end
  sb   zero, 0(x11)
  addi x11,  x11, 1
  j    __crt0_clear_bss_loop
 
__crt0_clear_bss_loop_end:
 
 
// ************************************************************************************************
// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols
// ************************************************************************************************
__crt0_copy_data:
  la   x11, __crt0_copy_data_src_begin        // start of data area (copy source)
  la   x12, __crt0_copy_data_dst_begin        // start of data area (copy destination)
  la   x13, __crt0_copy_data_dst_end          // last address of destination data area
 
__crt0_copy_data_loop:
  bge  x12, x13,  __crt0_copy_data_loop_end
  lb   x14, 0(x11)
  sb   x14, 0(x12)
  addi x11, x11, 1
  addi x12, x12, 1
  j    __crt0_copy_data_loop
 
__crt0_copy_data_loop_end:
 
 
// ************************************************************************************************
// Setup arguments and call main function
// ************************************************************************************************
__crt0_main_entry:
  addi x10, zero, 0 // a0 = argc = 0
  addi x11, zero, 0 // a1 = argv = 0
  jal  ra,  main    // call actual app's main function, this "should" not return
 
 
// ************************************************************************************************
// call "after main" handler (if there is any) if main really returns
// ************************************************************************************************
__crt0_main_aftermath:
  csrw  mscratch, a0                 // copy main's return code in mscratch for debugger
 
#ifndef make_bootloader              // after_main handler not supported for bootloader
  .weak __neorv32_crt0_after_main
  la   ra, __neorv32_crt0_after_main
  beqz ra, __crt0_main_aftermath_end // check if an aftermath handler has been specified
  jalr ra                            // execute handler, main's return code in a0
#endif
 
 
// ************************************************************************************************
// go to endless sleep mode
// ************************************************************************************************
__crt0_main_aftermath_end:
  csrci mstatus,  8                  // mstatus: disable global IRQs (mstatus.mie)
__crt0_main_aftermath_end_loop:
  wfi                                // try to go to sleep mode
  j __crt0_main_aftermath_end_loop   // endless loop
 
 
// ************************************************************************************************
// dummy trap handler (for exceptions & IRQs during very early boot stage)
// does nothing but tries to move on to next instruction
// ************************************************************************************************
.balign 4
__crt0_dummy_trap_handler:
 
  addi  sp,   sp, -8
  sw      x8,   0(sp)
  sw      x9,   4(sp)
 
  csrr  x8,   mcause
  blt   x8,   zero, __crt0_dummy_trap_handler_irq  // skip mepc modification if interrupt
 
  csrr  x8,   mepc
 
__crt0_dummy_trap_handler_exc_c_check:             // is compressed instruction?
  lh    x9,   0(x8)                                // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
  andi  x9,   x9, 3                                // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
 
  addi  x8,   x8, +2                               // only this for compressed instructions
  csrw  mepc, x8                                   // set return address when compressed instruction
 
  addi  x8,   zero, 3
  bne   x8,   x9, __crt0_dummy_trap_handler_irq    // jump if compressed instruction
 
__crt0_dummy_trap_handler_exc_uncrompressed:       // is uncompressed instruction!
  csrr  x8,   mepc
  addi  x8,   x8, +2                               // add another 2 (making +4) for uncompressed instructions
  csrw  mepc, x8
 
__crt0_dummy_trap_handler_irq:
  lw    x8,   0(sp)
  lw    x9,   4(sp)
  addi  sp,   sp, +8
 
  mret
 
.cfi_endproc
.end

Line No.	Rev	Author	Line
1	2	zero_gravi	`/* ################################################################################################# */`
2	21	zero_gravi	`/* # << NEORV32 - crt0.S - Start-Up Code >> # */`
3	2	zero_gravi	`/* # ********************************************************************************************* # */`
4			`/* # BSD 3-Clause License # */`
5			`/* # # */`
6	53	zero_gravi	`/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */`
7	2	zero_gravi	`/* # # */`
8			`/* # Redistribution and use in source and binary forms, with or without modification, are # */`
9			`/* # permitted provided that the following conditions are met: # */`
10			`/* # # */`
11			`/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */`
12			`/* # conditions and the following disclaimer. # */`
13			`/* # # */`
14			`/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */`
15			`/* # conditions and the following disclaimer in the documentation and/or other materials # */`
16			`/* # provided with the distribution. # */`
17			`/* # # */`
18			`/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */`
19			`/* # endorse or promote products derived from this software without specific prior written # */`
20			`/* # permission. # */`
21			`/* # # */`
22			`/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */`
23			`/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */`
24			`/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */`
25			`/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */`
26			`/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */`
27			`/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */`
28			`/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */`
29			`/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */`
30			`/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */`
31			`/* # ********************************************************************************************* # */`
32			`/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */`
33			`/* ################################################################################################# */`
34
35	21	zero_gravi	`.file "crt0.S"`
36			`.section .text.boot`
37			`.balign 4`
38			`.global _start`
39	2	zero_gravi
40
41			`_start:`
42	21	zero_gravi	`.cfi_startproc`
43			`.cfi_undefined ra`
44	2	zero_gravi
45	59	zero_gravi
46	61	zero_gravi	`// ************************************************************************************************`
47	62	zero_gravi	`// This is the very first instruction that is executed after hardware reset. It ensures that x0 is`
48			`// written at least once - the CPU HW will ensure it is always set to zero on any write access.`
49			`// ************************************************************************************************`
50			`lui zero, 0 // "dummy" instruction that uses no reg-file input operands at all`
51
52
53			`// ************************************************************************************************`
54	56	zero_gravi	`// Setup pointers using linker script symbols`
55	61	zero_gravi	`// ************************************************************************************************`
56	56	zero_gravi	`__crt0_pointer_init:`
57	61	zero_gravi	`.option push`
58			`.option norelax`
59	52	zero_gravi
60	61	zero_gravi	`la sp, __crt0_stack_begin // stack pointer`
61			`la gp, __global_pointer$ // global pointer`
62	52	zero_gravi
63	61	zero_gravi	`.option pop`
64
65
66			`// ************************************************************************************************`
67			`// Setup CPU core CSRs (some of them DO NOT have a dedicated`
68			`// reset and need to be explicitly initialized)`
69			`// ************************************************************************************************`
70	56	zero_gravi	`__crt0_cpu_csr_init:`
71
72	61	zero_gravi	`la x10, __crt0_dummy_trap_handler // configure early trap handler`
73			`csrw mtvec, x10`
74			`csrw mepc, x10 // just to init mepc`
75	56	zero_gravi
76	61	zero_gravi	`csrw mstatus, zero // disable global IRQ`
77	56	zero_gravi
78	61	zero_gravi	`csrw mie, zero // absolutely no interrupts sources, thanks`
79	56	zero_gravi
80	61	zero_gravi	`csrw mcounteren, zero // no access from less-privileged modes to counter CSRs`
81	56	zero_gravi
82	61	zero_gravi	`li x11, ~5 // stop all counters except for [m]cycle[h] and [m]instret[h]`
83			`csrw 0x320, x11 // = mcountinhibit (literal address for lagacy toolchain compatibility)`
84	56	zero_gravi
85	61	zero_gravi	`csrw mcycle, zero // reset cycle counters`
86			`csrw mcycleh, zero`
87			`csrw minstret, zero // reset instruction counters`
88	56	zero_gravi	`csrw minstreth, zero`
89
90
91	61	zero_gravi	`// ************************************************************************************************`
92			`// Initialize integer register file (lower half)`
93			`// ************************************************************************************************`
94			`__crt0_reg_file_clear:`
95			`//addi x0, x0, 0 // hardwired to zero`
96			`addi x1, x0, 0`
97			`//addi x2, x0, 0 // stack pointer sp`
98			`//addi x3, x0, 0 // gloabl pointer gp`
99			`addi x4, x0, 0`
100			`addi x5, x0, 0`
101			`addi x6, x0, 0`
102			`addi x7, x0, 0`
103			`//addi x8, x0, 0 // initialized within crt0`
104			`//addi x9, x0, 0 // initialized within crt0`
105			`//addi x10, x0, 0 // initialized within crt0`
106			`//addi x11, x0, 0 // initialized within crt0`
107			`//addi x12, x0, 0 // initialized within crt0`
108			`//addi x13, x0, 0 // initialized within crt0`
109			`addi x14, x0, 0`
110			`addi x15, x0, 0`
111
112
113			`// ************************************************************************************************`
114			`// Initialize integer register file (upper half, if no E extension)`
115			`// ************************************************************************************************`
116	32	zero_gravi	`#ifndef __riscv_32e`
117	61	zero_gravi	`// do not do this if compiling bootloader (to save some program space)`
118	32	zero_gravi	`#ifndef make_bootloader`
119			`addi x16, x0, 0`
120			`addi x17, x0, 0`
121			`addi x18, x0, 0`
122			`addi x19, x0, 0`
123			`addi x20, x0, 0`
124			`addi x21, x0, 0`
125			`addi x22, x0, 0`
126			`addi x23, x0, 0`
127			`addi x24, x0, 0`
128			`addi x25, x0, 0`
129			`addi x26, x0, 0`
130			`addi x27, x0, 0`
131			`addi x28, x0, 0`
132			`addi x29, x0, 0`
133			`addi x30, x0, 0`
134			`addi x31, x0, 0`
135			`#endif`
136			`#endif`
137
138
139	61	zero_gravi	`// ************************************************************************************************`
140	2	zero_gravi	`// Reset/deactivate IO/peripheral devices`
141	61	zero_gravi	`// Devices, that are not implemented, will cause a store bus access fault`
142			`// which is captured (but actually ignored) by the dummy trap handler.`
143			`// ************************************************************************************************`
144	2	zero_gravi	`__crt0_reset_io:`
145	61	zero_gravi	`la x8, __ctr0_io_space_begin // start of processor-internal IO region`
146			`la x9, __ctr0_io_space_end // end of processor-internal IO region`
147	2	zero_gravi
148			`__crt0_reset_io_loop:`
149	58	zero_gravi	`sw zero, 0(x8)`
150			`addi x8, x8, 4`
151			`bne x8, x9, __crt0_reset_io_loop`
152	2	zero_gravi
153
154	61	zero_gravi	`// ************************************************************************************************`
155	23	zero_gravi	`// Clear .bss section (byte-wise) using linker script symbols`
156	61	zero_gravi	`// ************************************************************************************************`
157	2	zero_gravi	`__crt0_clear_bss:`
158	61	zero_gravi	`la x11, __crt0_bss_start`
159			`la x12, __crt0_bss_end`
160	2	zero_gravi
161			`__crt0_clear_bss_loop:`
162	61	zero_gravi	`bge x11, x12, __crt0_clear_bss_loop_end`
163	2	zero_gravi	`sb zero, 0(x11)`
164	61	zero_gravi	`addi x11, x11, 1`
165	2	zero_gravi	`j __crt0_clear_bss_loop`
166
167			`__crt0_clear_bss_loop_end:`
168
169
170	61	zero_gravi	`// ************************************************************************************************`
171	23	zero_gravi	`// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols`
172	61	zero_gravi	`// ************************************************************************************************`
173	2	zero_gravi	`__crt0_copy_data:`
174	61	zero_gravi	`la x11, __crt0_copy_data_src_begin // start of data area (copy source)`
175			`la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)`
176			`la x13, __crt0_copy_data_dst_end // last address of destination data area`
177	2	zero_gravi
178			`__crt0_copy_data_loop:`
179			`bge x12, x13, __crt0_copy_data_loop_end`
180			`lb x14, 0(x11)`
181			`sb x14, 0(x12)`
182			`addi x11, x11, 1`
183			`addi x12, x12, 1`
184			`j __crt0_copy_data_loop`
185
186			`__crt0_copy_data_loop_end:`
187
188
189	61	zero_gravi	`// ************************************************************************************************`
190			`// Setup arguments and call main function`
191			`// ************************************************************************************************`
192	2	zero_gravi	`__crt0_main_entry:`
193	61	zero_gravi	`addi x10, zero, 0 // a0 = argc = 0`
194			`addi x11, zero, 0 // a1 = argv = 0`
195			`jal ra, main // call actual app's main function, this "should" not return`
196	2	zero_gravi
197
198	61	zero_gravi	`// ************************************************************************************************`
199			`// call "after main" handler (if there is any) if main really returns`
200			`// ************************************************************************************************`
201			`__crt0_main_aftermath:`
202			`csrw mscratch, a0 // copy main's return code in mscratch for debugger`
203	2	zero_gravi
204	61	zero_gravi	`#ifndef make_bootloader // after_main handler not supported for bootloader`
205			`.weak __neorv32_crt0_after_main`
206			`la ra, __neorv32_crt0_after_main`
207			`beqz ra, __crt0_main_aftermath_end // check if an aftermath handler has been specified`
208			`jalr ra // execute handler, main's return code in a0`
209			`#endif`
210	2	zero_gravi
211
212	61	zero_gravi	`// ************************************************************************************************`
213			`// go to endless sleep mode`
214			`// ************************************************************************************************`
215			`__crt0_main_aftermath_end:`
216			`csrci mstatus, 8 // mstatus: disable global IRQs (mstatus.mie)`
217			`__crt0_main_aftermath_end_loop:`
218			`wfi // try to go to sleep mode`
219			`j __crt0_main_aftermath_end_loop // endless loop`
220	2	zero_gravi
221	61	zero_gravi
222			`// ************************************************************************************************`
223			`// dummy trap handler (for exceptions & IRQs during very early boot stage)`
224			`// does nothing but tries to move on to next instruction`
225			`// ************************************************************************************************`
226	21	zero_gravi	`.balign 4`
227	14	zero_gravi	`__crt0_dummy_trap_handler:`
228	2	zero_gravi
229	61	zero_gravi	`addi sp, sp, -8`
230			`sw x8, 0(sp)`
231			`sw x9, 4(sp)`
232	2	zero_gravi
233	61	zero_gravi	`csrr x8, mcause`
234			`blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt`
235	2	zero_gravi
236	61	zero_gravi	`csrr x8, mepc`
237	2	zero_gravi
238	61	zero_gravi	`__crt0_dummy_trap_handler_exc_c_check: // is compressed instruction?`
239			`lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception`
240			`andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)`
241	2	zero_gravi
242	61	zero_gravi	`addi x8, x8, +2 // only this for compressed instructions`
243			`csrw mepc, x8 // set return address when compressed instruction`
244	2	zero_gravi
245	61	zero_gravi	`addi x8, zero, 3`
246			`bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction`
247
248			`__crt0_dummy_trap_handler_exc_uncrompressed: // is uncompressed instruction!`
249			`csrr x8, mepc`
250			`addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions`
251	14	zero_gravi	`csrw mepc, x8`
252	2	zero_gravi
253	14	zero_gravi	`__crt0_dummy_trap_handler_irq:`
254	61	zero_gravi	`lw x8, 0(sp)`
255			`lw x9, 4(sp)`
256			`addi sp, sp, +8`
257	2	zero_gravi
258			`mret`
259
260	21	zero_gravi	`.cfi_endproc`
261			`.end`

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[/] [neorv32/] [trunk/] [sw/] [common/] [crt0.S] - Blame information for rev 63