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/* ################################################################################################# */
/* # << NEORV32 - crt0.S - Start-Up Code >>                                                        # */
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License                                                                          # */
/* #                                                                                               # */
/* # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     # */
/* #                                                                                               # */
/* # Redistribution and use in source and binary forms, with or without modification, are          # */
/* # permitted provided that the following conditions are met:                                     # */
/* #                                                                                               # */
/* # 1. Redistributions of source code must retain the above copyright notice, this list of        # */
/* #    conditions and the following disclaimer.                                                   # */
/* #                                                                                               # */
/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     # */
/* #    conditions and the following disclaimer in the documentation and/or other materials        # */
/* #    provided with the distribution.                                                            # */
/* #                                                                                               # */
/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  # */
/* #    endorse or promote products derived from this software without specific prior written      # */
/* #    permission.                                                                                # */
/* #                                                                                               # */
/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   # */
/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               # */
/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    # */
/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     # */
/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    # */
/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     # */
/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  # */
/* # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            # */
/* # ********************************************************************************************* # */
/* # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting # */
/* ################################################################################################# */
 
.file "crt0.S"
.section .text.crt0
.balign 4
.global _start
.global __crt0_main_exit
 
 
_start:
.cfi_startproc
.cfi_undefined ra
 
 
// ************************************************************************************************
// This is the very first instruction that is executed after hardware reset. It ensures that x0 is
// written at least once - the CPU HW will ensure it is always set to zero on any write access.
// ************************************************************************************************
  lui zero, 0 // "dummy" instruction that uses no reg-file input operands at all
 
 
// ************************************************************************************************
// Setup pointers using linker script symbols
// ************************************************************************************************
__crt0_pointer_init:
  .option push
  .option norelax
 
  la sp, __crt0_stack_begin // stack pointer
  la gp, __global_pointer$  // global pointer
 
  .option pop
 
 
// ************************************************************************************************
// Setup CPU core CSRs (some of them DO NOT have a dedicated
// reset and need to be explicitly initialized)
// ************************************************************************************************
__crt0_cpu_csr_init:
 
  la   x10,   __crt0_dummy_trap_handler // configure early-boot trap handler
  csrw mtvec, x10
  csrw mepc,  x10                       // just to init mepc
 
  csrw mstatus, zero                    // clear all control flags, also disable global IRQ
  csrw mie,     zero                    // absolutely no interrupt sources, thanks
  csrw mip,     zero                    // clear all pending interrupts
 
  csrw 0x320,      zero                 // stop all counters; use "mcountinhibit" literal address for lagacy toolchain compatibility
  csrw mcounteren, zero                 // no access from less-privileged modes to counter CSRs
 
  csrw mcycle,    zero                  // reset cycle counter
  csrw mcycleh,   zero
  csrw minstret,  zero                  // reset instructions-retired counter
  csrw minstreth, zero
 
 
// ************************************************************************************************
// Initialize integer register file (lower half)
// ************************************************************************************************
__crt0_reg_file_clear:
//addi  x0, x0, 0 // hardwired to zero
  addi  x1, x0, 0
//addi  x2, x0, 0 // stack pointer sp
//addi  x3, x0, 0 // global pointer gp
  addi  x4, x0, 0
  addi  x5, x0, 0
  addi  x6, x0, 0
  addi  x7, x0, 0
//addi  x8, x0, 0 // implicitly initialized within crt0
//addi  x9, x0, 0 // implicitly initialized within crt0
//addi x10, x0, 0 // implicitly initialized within crt0
//addi x11, x0, 0 // implicitly initialized within crt0
//addi x12, x0, 0 // implicitly initialized within crt0
//addi x13, x0, 0 // implicitly initialized within crt0
//addi x14, x0, 0 // implicitly initialized within crt0
//addi x15, x0, 0 // implicitly initialized within crt0
 
 
// ************************************************************************************************
// Initialize integer register file (upper half, if no E extension)
// ************************************************************************************************
#ifndef __riscv_32e
// do not do this if compiling bootloader (to save some program space)
#ifndef make_bootloader
  addi x16, x0, 0
  addi x17, x0, 0
  addi x18, x0, 0
  addi x19, x0, 0
  addi x20, x0, 0
  addi x21, x0, 0
  addi x22, x0, 0
  addi x23, x0, 0
  addi x24, x0, 0
  addi x25, x0, 0
  addi x26, x0, 0
  addi x27, x0, 0
  addi x28, x0, 0
  addi x29, x0, 0
  addi x30, x0, 0
  addi x31, x0, 0
#endif
#endif
 
 
// ************************************************************************************************
// Reset/deactivate IO/peripheral devices
// Devices, that are not implemented, will cause a store bus access fault
// that is catched (but not further processed) by the dummy trap handler.
// ************************************************************************************************
__crt0_reset_io:
  la   x8,   __crt0_io_space_begin         // start of processor-internal IO region
  la   x9,   __crt0_io_space_end           // end of processor-internal IO region
 
__crt0_reset_io_loop:
  sw   zero, 0(x8)
  addi x8,   x8, 4
  bne  x8,   x9, __crt0_reset_io_loop
 
 
// ************************************************************************************************
// Copy initialized .data section from ROM to RAM (byte-wise)
// ************************************************************************************************
__crt0_copy_data:
  la   x11, __crt0_copy_data_src_begin        // start of data area (copy source)
  la   x12, __crt0_copy_data_dst_begin        // start of data area (copy destination)
  la   x13, __crt0_copy_data_dst_end          // last address of destination data area
 
__crt0_copy_data_loop:
  bge  x12, x13,  __crt0_copy_data_loop_end
  lb   x14, 0(x11)
  sb   x14, 0(x12)
  addi x11, x11, 1
  addi x12, x12, 1
  j    __crt0_copy_data_loop
 
__crt0_copy_data_loop_end:
 
 
// ************************************************************************************************
// Clear .bss section (byte-wise)
// ************************************************************************************************
__crt0_clear_bss:
  la   x14,  __crt0_bss_start
  la   x15,  __crt0_bss_end
 
__crt0_clear_bss_loop:
  bge  x14,  x15, __crt0_clear_bss_loop_end
  sb   zero, 0(x14)
  addi x14,  x14, 1
  j    __crt0_clear_bss_loop
 
__crt0_clear_bss_loop_end:
 
 
// ************************************************************************************************
// Setup arguments and call main function
// ************************************************************************************************
__crt0_main_entry:
  addi a0,  zero, 0                  // a0 = argc = 0
  addi a1,  zero, 0                  // a1 = argv = 0
  jal  ra,  main                     // call actual app's main function, this "should" not return
 
__crt0_main_exit:                    // main's "return" and "exit" will arrive here
  csrw mscratch, a0                  // backup main's return code to mscratch (for debugger)
 
 
// ************************************************************************************************
// call "after main" handler (if there is any) if main really returns
// ************************************************************************************************
#ifndef make_bootloader              // after_main handler not supported for bootloader
 
__crt0_main_aftermath:
  .weak __neorv32_crt0_after_main
  la   ra, __neorv32_crt0_after_main
  beqz ra, __crt0_main_aftermath_end // check if an aftermath handler has been specified
  jalr ra                            // execute handler with main's return code still in a0
 
__crt0_main_aftermath_end:
 
#endif
 
 
// ************************************************************************************************
// go to endless sleep mode
// ************************************************************************************************
__crt0_shutdown:
  csrci mstatus, 8                   // disable global IRQs (clear mstatus.mie)
  wfi                                // go to sleep mode
  j .                                // endless loop
 
 
// ************************************************************************************************
// dummy trap handler (for exceptions & IRQs during very early boot stage)
// does nothing but trying to move on to the next instruction
// ************************************************************************************************
.balign 4
__crt0_dummy_trap_handler:
 
  addi  sp,   sp, -8
  sw    x8,   0(sp)
  sw    x9,   4(sp)
 
  csrr  x8,   mcause
  blt   x8,   zero, __crt0_dummy_trap_handler_irq  // skip mepc modification if interrupt
 
  csrr  x8,   mepc
 
__crt0_dummy_trap_handler_exc_c_check:             // is compressed instruction?
  lh    x9,   0(x8)                                // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
  andi  x9,   x9, 3                                // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
 
  addi  x8,   x8, +2                               // only this for compressed instructions
  csrw  mepc, x8                                   // set return address when compressed instruction
 
  addi  x8,   zero, 3
  bne   x8,   x9, __crt0_dummy_trap_handler_irq    // jump if compressed instruction
 
__crt0_dummy_trap_handler_exc_uncrompressed:       // is uncompressed instruction!
  csrr  x8,   mepc
  addi  x8,   x8, +2                               // add another 2 (making +4) for uncompressed instructions
  csrw  mepc, x8
 
__crt0_dummy_trap_handler_irq:
  lw    x8,   0(sp)
  lw    x9,   4(sp)
  addi  sp,   sp, +8
 
  mret
 
.cfi_endproc
.end

Line No.	Rev	Author	Line
1	2	zero_gravi	`/* ################################################################################################# */`
2	21	zero_gravi	`/* # << NEORV32 - crt0.S - Start-Up Code >> # */`
3	2	zero_gravi	`/* # ********************************************************************************************* # */`
4			`/* # BSD 3-Clause License # */`
5			`/* # # */`
6	72	zero_gravi	`/* # Copyright (c) 2022, Stephan Nolting. All rights reserved. # */`
7	2	zero_gravi	`/* # # */`
8			`/* # Redistribution and use in source and binary forms, with or without modification, are # */`
9			`/* # permitted provided that the following conditions are met: # */`
10			`/* # # */`
11			`/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */`
12			`/* # conditions and the following disclaimer. # */`
13			`/* # # */`
14			`/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */`
15			`/* # conditions and the following disclaimer in the documentation and/or other materials # */`
16			`/* # provided with the distribution. # */`
17			`/* # # */`
18			`/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */`
19			`/* # endorse or promote products derived from this software without specific prior written # */`
20			`/* # permission. # */`
21			`/* # # */`
22			`/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */`
23			`/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */`
24			`/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */`
25			`/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */`
26			`/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */`
27			`/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */`
28			`/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */`
29			`/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */`
30			`/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */`
31			`/* # ********************************************************************************************* # */`
32			`/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */`
33			`/* ################################################################################################# */`
34
35	72	zero_gravi	`.file "crt0.S"`
36			`.section .text.crt0`
37	21	zero_gravi	`.balign 4`
38			`.global _start`
39	72	zero_gravi	`.global __crt0_main_exit`
40	2	zero_gravi
41
42			`_start:`
43	21	zero_gravi	`.cfi_startproc`
44			`.cfi_undefined ra`
45	2	zero_gravi
46	59	zero_gravi
47	61	zero_gravi	`// ************************************************************************************************`
48	62	zero_gravi	`// This is the very first instruction that is executed after hardware reset. It ensures that x0 is`
49			`// written at least once - the CPU HW will ensure it is always set to zero on any write access.`
50			`// ************************************************************************************************`
51			`lui zero, 0 // "dummy" instruction that uses no reg-file input operands at all`
52
53
54			`// ************************************************************************************************`
55	56	zero_gravi	`// Setup pointers using linker script symbols`
56	61	zero_gravi	`// ************************************************************************************************`
57	56	zero_gravi	`__crt0_pointer_init:`
58	61	zero_gravi	`.option push`
59			`.option norelax`
60	52	zero_gravi
61	66	zero_gravi	`la sp, __crt0_stack_begin // stack pointer`
62			`la gp, __global_pointer$ // global pointer`
63	52	zero_gravi
64	61	zero_gravi	`.option pop`
65
66
67			`// ************************************************************************************************`
68			`// Setup CPU core CSRs (some of them DO NOT have a dedicated`
69			`// reset and need to be explicitly initialized)`
70			`// ************************************************************************************************`
71	56	zero_gravi	`__crt0_cpu_csr_init:`
72
73	73	zero_gravi	`la x10, __crt0_dummy_trap_handler // configure early-boot trap handler`
74	61	zero_gravi	`csrw mtvec, x10`
75			`csrw mepc, x10 // just to init mepc`
76	56	zero_gravi
77	73	zero_gravi	`csrw mstatus, zero // clear all control flags, also disable global IRQ`
78			`csrw mie, zero // absolutely no interrupt sources, thanks`
79			`csrw mip, zero // clear all pending interrupts`
80	56	zero_gravi
81	73	zero_gravi	`csrw 0x320, zero // stop all counters; use "mcountinhibit" literal address for lagacy toolchain compatibility`
82	61	zero_gravi	`csrw mcounteren, zero // no access from less-privileged modes to counter CSRs`
83	56	zero_gravi
84	73	zero_gravi	`csrw mcycle, zero // reset cycle counter`
85	61	zero_gravi	`csrw mcycleh, zero`
86	73	zero_gravi	`csrw minstret, zero // reset instructions-retired counter`
87	56	zero_gravi	`csrw minstreth, zero`
88
89
90	61	zero_gravi	`// ************************************************************************************************`
91			`// Initialize integer register file (lower half)`
92			`// ************************************************************************************************`
93			`__crt0_reg_file_clear:`
94			`//addi x0, x0, 0 // hardwired to zero`
95			`addi x1, x0, 0`
96			`//addi x2, x0, 0 // stack pointer sp`
97	66	zero_gravi	`//addi x3, x0, 0 // global pointer gp`
98	61	zero_gravi	`addi x4, x0, 0`
99			`addi x5, x0, 0`
100			`addi x6, x0, 0`
101			`addi x7, x0, 0`
102	66	zero_gravi	`//addi x8, x0, 0 // implicitly initialized within crt0`
103			`//addi x9, x0, 0 // implicitly initialized within crt0`
104			`//addi x10, x0, 0 // implicitly initialized within crt0`
105			`//addi x11, x0, 0 // implicitly initialized within crt0`
106			`//addi x12, x0, 0 // implicitly initialized within crt0`
107			`//addi x13, x0, 0 // implicitly initialized within crt0`
108	73	zero_gravi	`//addi x14, x0, 0 // implicitly initialized within crt0`
109			`//addi x15, x0, 0 // implicitly initialized within crt0`
110	61	zero_gravi
111
112			`// ************************************************************************************************`
113			`// Initialize integer register file (upper half, if no E extension)`
114			`// ************************************************************************************************`
115	32	zero_gravi	`#ifndef __riscv_32e`
116	61	zero_gravi	`// do not do this if compiling bootloader (to save some program space)`
117	32	zero_gravi	`#ifndef make_bootloader`
118			`addi x16, x0, 0`
119			`addi x17, x0, 0`
120			`addi x18, x0, 0`
121			`addi x19, x0, 0`
122			`addi x20, x0, 0`
123			`addi x21, x0, 0`
124			`addi x22, x0, 0`
125			`addi x23, x0, 0`
126			`addi x24, x0, 0`
127			`addi x25, x0, 0`
128			`addi x26, x0, 0`
129			`addi x27, x0, 0`
130			`addi x28, x0, 0`
131			`addi x29, x0, 0`
132			`addi x30, x0, 0`
133			`addi x31, x0, 0`
134			`#endif`
135			`#endif`
136
137
138	61	zero_gravi	`// ************************************************************************************************`
139	2	zero_gravi	`// Reset/deactivate IO/peripheral devices`
140	61	zero_gravi	`// Devices, that are not implemented, will cause a store bus access fault`
141	72	zero_gravi	`// that is catched (but not further processed) by the dummy trap handler.`
142	61	zero_gravi	`// ************************************************************************************************`
143	2	zero_gravi	`__crt0_reset_io:`
144	72	zero_gravi	`la x8, __crt0_io_space_begin // start of processor-internal IO region`
145			`la x9, __crt0_io_space_end // end of processor-internal IO region`
146	2	zero_gravi
147			`__crt0_reset_io_loop:`
148	58	zero_gravi	`sw zero, 0(x8)`
149			`addi x8, x8, 4`
150			`bne x8, x9, __crt0_reset_io_loop`
151	2	zero_gravi
152
153	61	zero_gravi	`// ************************************************************************************************`
154	72	zero_gravi	`// Copy initialized .data section from ROM to RAM (byte-wise)`
155	61	zero_gravi	`// ************************************************************************************************`
156	2	zero_gravi	`__crt0_copy_data:`
157	61	zero_gravi	`la x11, __crt0_copy_data_src_begin // start of data area (copy source)`
158			`la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)`
159			`la x13, __crt0_copy_data_dst_end // last address of destination data area`
160	2	zero_gravi
161			`__crt0_copy_data_loop:`
162			`bge x12, x13, __crt0_copy_data_loop_end`
163			`lb x14, 0(x11)`
164			`sb x14, 0(x12)`
165			`addi x11, x11, 1`
166			`addi x12, x12, 1`
167			`j __crt0_copy_data_loop`
168
169			`__crt0_copy_data_loop_end:`
170
171
172	61	zero_gravi	`// ************************************************************************************************`
173	73	zero_gravi	`// Clear .bss section (byte-wise)`
174			`// ************************************************************************************************`
175			`__crt0_clear_bss:`
176			`la x14, __crt0_bss_start`
177			`la x15, __crt0_bss_end`
178
179			`__crt0_clear_bss_loop:`
180			`bge x14, x15, __crt0_clear_bss_loop_end`
181			`sb zero, 0(x14)`
182			`addi x14, x14, 1`
183			`j __crt0_clear_bss_loop`
184
185			`__crt0_clear_bss_loop_end:`
186
187
188			`// ************************************************************************************************`
189	61	zero_gravi	`// Setup arguments and call main function`
190			`// ************************************************************************************************`
191	2	zero_gravi	`__crt0_main_entry:`
192	72	zero_gravi	`addi a0, zero, 0 // a0 = argc = 0`
193			`addi a1, zero, 0 // a1 = argv = 0`
194			`jal ra, main // call actual app's main function, this "should" not return`
195	2	zero_gravi
196	72	zero_gravi	`__crt0_main_exit: // main's "return" and "exit" will arrive here`
197			`csrw mscratch, a0 // backup main's return code to mscratch (for debugger)`
198	2	zero_gravi
199	72	zero_gravi
200	61	zero_gravi	`// ************************************************************************************************`
201			`// call "after main" handler (if there is any) if main really returns`
202			`// ************************************************************************************************`
203	72	zero_gravi	`#ifndef make_bootloader // after_main handler not supported for bootloader`
204
205	61	zero_gravi	`__crt0_main_aftermath:`
206			`.weak __neorv32_crt0_after_main`
207			`la ra, __neorv32_crt0_after_main`
208			`beqz ra, __crt0_main_aftermath_end // check if an aftermath handler has been specified`
209	72	zero_gravi	`jalr ra // execute handler with main's return code still in a0`
210
211			`__crt0_main_aftermath_end:`
212
213	61	zero_gravi	`#endif`
214	2	zero_gravi
215
216	61	zero_gravi	`// ************************************************************************************************`
217			`// go to endless sleep mode`
218			`// ************************************************************************************************`
219	72	zero_gravi	`__crt0_shutdown:`
220			`csrci mstatus, 8 // disable global IRQs (clear mstatus.mie)`
221			`wfi // go to sleep mode`
222	73	zero_gravi	`j . // endless loop`
223	2	zero_gravi
224	61	zero_gravi
225			`// ************************************************************************************************`
226			`// dummy trap handler (for exceptions & IRQs during very early boot stage)`
227	72	zero_gravi	`// does nothing but trying to move on to the next instruction`
228	61	zero_gravi	`// ************************************************************************************************`
229	21	zero_gravi	`.balign 4`
230	14	zero_gravi	`__crt0_dummy_trap_handler:`
231	2	zero_gravi
232	72	zero_gravi	`addi sp, sp, -8`
233			`sw x8, 0(sp)`
234			`sw x9, 4(sp)`
235	2	zero_gravi
236	61	zero_gravi	`csrr x8, mcause`
237			`blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt`
238	2	zero_gravi
239	61	zero_gravi	`csrr x8, mepc`
240	2	zero_gravi
241	61	zero_gravi	`__crt0_dummy_trap_handler_exc_c_check: // is compressed instruction?`
242			`lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception`
243			`andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)`
244	2	zero_gravi
245	61	zero_gravi	`addi x8, x8, +2 // only this for compressed instructions`
246			`csrw mepc, x8 // set return address when compressed instruction`
247	2	zero_gravi
248	61	zero_gravi	`addi x8, zero, 3`
249			`bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction`
250
251			`__crt0_dummy_trap_handler_exc_uncrompressed: // is uncompressed instruction!`
252			`csrr x8, mepc`
253			`addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions`
254	14	zero_gravi	`csrw mepc, x8`
255	2	zero_gravi
256	14	zero_gravi	`__crt0_dummy_trap_handler_irq:`
257	61	zero_gravi	`lw x8, 0(sp)`
258			`lw x9, 4(sp)`
259			`addi sp, sp, +8`
260	2	zero_gravi
261			`mret`
262
263	21	zero_gravi	`.cfi_endproc`
264			`.end`

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[/] [neorv32/] [trunk/] [sw/] [common/] [crt0.S] - Blame information for rev 73