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/* ################################################################################################# */
/* # << NEORV32 - crt0.S - Start-Up Code >>                                                        # */
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License                                                                          # */
/* #                                                                                               # */
/* # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     # */
/* #                                                                                               # */
/* # Redistribution and use in source and binary forms, with or without modification, are          # */
/* # permitted provided that the following conditions are met:                                     # */
/* #                                                                                               # */
/* # 1. Redistributions of source code must retain the above copyright notice, this list of        # */
/* #    conditions and the following disclaimer.                                                   # */
/* #                                                                                               # */
/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     # */
/* #    conditions and the following disclaimer in the documentation and/or other materials        # */
/* #    provided with the distribution.                                                            # */
/* #                                                                                               # */
/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  # */
/* #    endorse or promote products derived from this software without specific prior written      # */
/* #    permission.                                                                                # */
/* #                                                                                               # */
/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   # */
/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               # */
/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    # */
/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     # */
/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    # */
/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     # */
/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  # */
/* # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            # */
/* # ********************************************************************************************* # */
/* # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting # */
/* ################################################################################################# */
 
.file "crt0.S"
.section .text.crt0
.balign 4
.global _start
.global __crt0_main_exit
 
 
_start:
.cfi_startproc
.cfi_undefined ra
 
 
// ************************************************************************************************
// This is the very first instruction that is executed after hardware reset. It ensures that x0 is
// written at least once - the CPU HW will ensure it is always set to zero on any write access.
//
// Furthermore, we have to disable ALL interrupts, which is required if this code is part of a
// program uploaded by the on-chip debugger (potentionally taking control from the bootloader).
// We setup a new stack pointer here and WE DO NOT WANT TO trap to an outdated trap handler with
// a modified stack pointer.
// ************************************************************************************************
  csrrci zero, mstatus, (1<<3) // disable global interrupt flag and write "anything" to x0
 
 
// ************************************************************************************************
// Setup pointers using linker script symbols
// ************************************************************************************************
__crt0_pointer_init:
  .option push
  .option norelax
 
  la sp, __crt0_stack_begin // stack pointer
  la gp, __global_pointer$  // global pointer
 
  .option pop
 
 
// ************************************************************************************************
// Setup CPU core CSRs (some of them DO NOT have a dedicated
// reset and need to be explicitly initialized)
// ************************************************************************************************
__crt0_cpu_csr_init:
 
  la   x10,   __crt0_dummy_trap_handler // configure early-boot trap handler
  csrw mtvec, x10
  csrw mepc,  x10                       // just to init mepc
 
  csrw mstatus, zero                    // clear all control flags, also disable global IRQ
  csrw mie,     zero                    // absolutely no interrupt sources, thanks
  csrw mip,     zero                    // clear all pending interrupts
 
  csrw 0x320,      zero                 // stop all counters; use "mcountinhibit" literal address for lagacy toolchain compatibility
  csrw mcounteren, zero                 // no access from less-privileged modes to counter CSRs
 
  csrw mcycle,    zero                  // reset cycle counter
  csrw mcycleh,   zero
  csrw minstret,  zero                  // reset instructions-retired counter
  csrw minstreth, zero
 
 
// ************************************************************************************************
// Initialize integer register file (lower half)
// ************************************************************************************************
__crt0_reg_file_clear:
//addi  x0, x0, 0 // hardwired to zero
  addi  x1, x0, 0
//addi  x2, x0, 0 // stack pointer sp
//addi  x3, x0, 0 // global pointer gp
  addi  x4, x0, 0
  addi  x5, x0, 0
  addi  x6, x0, 0
  addi  x7, x0, 0
//addi  x8, x0, 0 // implicitly initialized within crt0
//addi  x9, x0, 0 // implicitly initialized within crt0
//addi x10, x0, 0 // implicitly initialized within crt0
//addi x11, x0, 0 // implicitly initialized within crt0
//addi x12, x0, 0 // implicitly initialized within crt0
//addi x13, x0, 0 // implicitly initialized within crt0
//addi x14, x0, 0 // implicitly initialized within crt0
//addi x15, x0, 0 // implicitly initialized within crt0
 
 
// ************************************************************************************************
// Initialize integer register file (upper half, if no E extension)
// ************************************************************************************************
#ifndef __riscv_32e
// do not do this if compiling bootloader (to save some program space)
#ifndef make_bootloader
  addi x16, x0, 0
  addi x17, x0, 0
  addi x18, x0, 0
  addi x19, x0, 0
  addi x20, x0, 0
  addi x21, x0, 0
  addi x22, x0, 0
  addi x23, x0, 0
  addi x24, x0, 0
  addi x25, x0, 0
  addi x26, x0, 0
  addi x27, x0, 0
  addi x28, x0, 0
  addi x29, x0, 0
  addi x30, x0, 0
  addi x31, x0, 0
#endif
#endif
 
 
// ************************************************************************************************
// Reset/deactivate IO/peripheral devices
// Devices, that are not implemented, will cause a store bus access fault
// that is catched (but not further processed) by the dummy trap handler.
// ************************************************************************************************
__crt0_reset_io:
  la   x8,   __crt0_io_space_begin         // start of processor-internal IO region
  la   x9,   __crt0_io_space_end           // end of processor-internal IO region
 
__crt0_reset_io_loop:
  sw   zero, 0(x8)
  addi x8,   x8, 4
  bne  x8,   x9, __crt0_reset_io_loop
 
 
// ************************************************************************************************
// Copy initialized .data section from ROM to RAM (byte-wise)
// ************************************************************************************************
__crt0_copy_data:
  la   x11, __crt0_copy_data_src_begin        // start of data area (copy source)
  la   x12, __crt0_copy_data_dst_begin        // start of data area (copy destination)
  la   x13, __crt0_copy_data_dst_end          // last address of destination data area
 
__crt0_copy_data_loop:
  bge  x12, x13,  __crt0_copy_data_loop_end
  lb   x14, 0(x11)
  sb   x14, 0(x12)
  addi x11, x11, 1
  addi x12, x12, 1
  j    __crt0_copy_data_loop
 
__crt0_copy_data_loop_end:
 
 
// ************************************************************************************************
// Clear .bss section (byte-wise)
// ************************************************************************************************
__crt0_clear_bss:
  la   x14,  __crt0_bss_start
  la   x15,  __crt0_bss_end
 
__crt0_clear_bss_loop:
  bge  x14,  x15, __crt0_clear_bss_loop_end
  sb   zero, 0(x14)
  addi x14,  x14, 1
  j    __crt0_clear_bss_loop
 
__crt0_clear_bss_loop_end:
 
 
// ************************************************************************************************
// Setup arguments and call main function
// ************************************************************************************************
__crt0_main_entry:
  addi a0,  zero, 0                  // a0 = argc = 0
  addi a1,  zero, 0                  // a1 = argv = 0
  jal  ra,  main                     // call actual app's main function, this "should" not return
 
__crt0_main_exit:                    // main's "return" and "exit" will arrive here
  csrw mscratch, a0                  // backup main's return code to mscratch (for debugger)
 
 
// ************************************************************************************************
// call "after main" handler (if there is any) if main really returns
// ************************************************************************************************
#ifndef make_bootloader              // after_main handler not supported for bootloader
 
__crt0_main_aftermath:
  .weak __neorv32_crt0_after_main
  la   ra, __neorv32_crt0_after_main
  beqz ra, __crt0_main_aftermath_end // check if an aftermath handler has been specified
  jalr ra                            // execute handler with main's return code still in a0
 
__crt0_main_aftermath_end:
 
#endif
 
 
// ************************************************************************************************
// go to endless sleep mode
// ************************************************************************************************
__crt0_shutdown:
  csrci mstatus, 8                   // disable global IRQs (clear mstatus.mie)
  wfi                                // go to sleep mode
  j .                                // endless loop
 
 
// ************************************************************************************************
// dummy trap handler (for exceptions & IRQs during very early boot stage)
// does nothing but trying to move on to the next instruction
// ************************************************************************************************
.balign 4
__crt0_dummy_trap_handler:
 
  addi  sp,   sp, -8
  sw    x8,   0(sp)
  sw    x9,   4(sp)
 
  csrr  x8,   mcause
  blt   x8,   zero, __crt0_dummy_trap_handler_irq  // skip mepc modification if interrupt
 
  csrr  x8,   mepc
 
__crt0_dummy_trap_handler_exc_c_check:             // is compressed instruction?
  lh    x9,   0(x8)                                // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
  andi  x9,   x9, 3                                // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
 
  addi  x8,   x8, +2                               // only this for compressed instructions
  csrw  mepc, x8                                   // set return address when compressed instruction
 
  addi  x8,   zero, 3
  bne   x8,   x9, __crt0_dummy_trap_handler_irq    // jump if compressed instruction
 
__crt0_dummy_trap_handler_exc_uncrompressed:       // is uncompressed instruction!
  csrr  x8,   mepc
  addi  x8,   x8, +2                               // add another 2 (making +4) for uncompressed instructions
  csrw  mepc, x8
 
__crt0_dummy_trap_handler_irq:
  lw    x8,   0(sp)
  lw    x9,   4(sp)
  addi  sp,   sp, +8
 
  mret
 
.cfi_endproc
.end

Line No.	Rev	Author	Line
1	2	zero_gravi	`/* ################################################################################################# */`
2	21	zero_gravi	`/* # << NEORV32 - crt0.S - Start-Up Code >> # */`
3	2	zero_gravi	`/* # ********************************************************************************************* # */`
4			`/* # BSD 3-Clause License # */`
5			`/* # # */`
6	72	zero_gravi	`/* # Copyright (c) 2022, Stephan Nolting. All rights reserved. # */`
7	2	zero_gravi	`/* # # */`
8			`/* # Redistribution and use in source and binary forms, with or without modification, are # */`
9			`/* # permitted provided that the following conditions are met: # */`
10			`/* # # */`
11			`/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */`
12			`/* # conditions and the following disclaimer. # */`
13			`/* # # */`
14			`/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */`
15			`/* # conditions and the following disclaimer in the documentation and/or other materials # */`
16			`/* # provided with the distribution. # */`
17			`/* # # */`
18			`/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */`
19			`/* # endorse or promote products derived from this software without specific prior written # */`
20			`/* # permission. # */`
21			`/* # # */`
22			`/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */`
23			`/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */`
24			`/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */`
25			`/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */`
26			`/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */`
27			`/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */`
28			`/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */`
29			`/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */`
30			`/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */`
31			`/* # ********************************************************************************************* # */`
32			`/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */`
33			`/* ################################################################################################# */`
34
35	72	zero_gravi	`.file "crt0.S"`
36			`.section .text.crt0`
37	21	zero_gravi	`.balign 4`
38			`.global _start`
39	72	zero_gravi	`.global __crt0_main_exit`
40	2	zero_gravi
41
42			`_start:`
43	21	zero_gravi	`.cfi_startproc`
44			`.cfi_undefined ra`
45	2	zero_gravi
46	59	zero_gravi
47	61	zero_gravi	`// ************************************************************************************************`
48	62	zero_gravi	`// This is the very first instruction that is executed after hardware reset. It ensures that x0 is`
49			`// written at least once - the CPU HW will ensure it is always set to zero on any write access.`
50	74	zero_gravi	`//`
51			`// Furthermore, we have to disable ALL interrupts, which is required if this code is part of a`
52			`// program uploaded by the on-chip debugger (potentionally taking control from the bootloader).`
53			`// We setup a new stack pointer here and WE DO NOT WANT TO trap to an outdated trap handler with`
54			`// a modified stack pointer.`
55	62	zero_gravi	`// ************************************************************************************************`
56	74	zero_gravi	`csrrci zero, mstatus, (1<<3) // disable global interrupt flag and write "anything" to x0`
57	62	zero_gravi
58
59			`// ************************************************************************************************`
60	56	zero_gravi	`// Setup pointers using linker script symbols`
61	61	zero_gravi	`// ************************************************************************************************`
62	56	zero_gravi	`__crt0_pointer_init:`
63	61	zero_gravi	`.option push`
64			`.option norelax`
65	52	zero_gravi
66	66	zero_gravi	`la sp, __crt0_stack_begin // stack pointer`
67			`la gp, __global_pointer$ // global pointer`
68	52	zero_gravi
69	61	zero_gravi	`.option pop`
70
71
72			`// ************************************************************************************************`
73			`// Setup CPU core CSRs (some of them DO NOT have a dedicated`
74			`// reset and need to be explicitly initialized)`
75			`// ************************************************************************************************`
76	56	zero_gravi	`__crt0_cpu_csr_init:`
77
78	73	zero_gravi	`la x10, __crt0_dummy_trap_handler // configure early-boot trap handler`
79	61	zero_gravi	`csrw mtvec, x10`
80			`csrw mepc, x10 // just to init mepc`
81	56	zero_gravi
82	73	zero_gravi	`csrw mstatus, zero // clear all control flags, also disable global IRQ`
83			`csrw mie, zero // absolutely no interrupt sources, thanks`
84			`csrw mip, zero // clear all pending interrupts`
85	56	zero_gravi
86	73	zero_gravi	`csrw 0x320, zero // stop all counters; use "mcountinhibit" literal address for lagacy toolchain compatibility`
87	61	zero_gravi	`csrw mcounteren, zero // no access from less-privileged modes to counter CSRs`
88	56	zero_gravi
89	73	zero_gravi	`csrw mcycle, zero // reset cycle counter`
90	61	zero_gravi	`csrw mcycleh, zero`
91	73	zero_gravi	`csrw minstret, zero // reset instructions-retired counter`
92	56	zero_gravi	`csrw minstreth, zero`
93
94
95	61	zero_gravi	`// ************************************************************************************************`
96			`// Initialize integer register file (lower half)`
97			`// ************************************************************************************************`
98			`__crt0_reg_file_clear:`
99			`//addi x0, x0, 0 // hardwired to zero`
100			`addi x1, x0, 0`
101			`//addi x2, x0, 0 // stack pointer sp`
102	66	zero_gravi	`//addi x3, x0, 0 // global pointer gp`
103	61	zero_gravi	`addi x4, x0, 0`
104			`addi x5, x0, 0`
105			`addi x6, x0, 0`
106			`addi x7, x0, 0`
107	66	zero_gravi	`//addi x8, x0, 0 // implicitly initialized within crt0`
108			`//addi x9, x0, 0 // implicitly initialized within crt0`
109			`//addi x10, x0, 0 // implicitly initialized within crt0`
110			`//addi x11, x0, 0 // implicitly initialized within crt0`
111			`//addi x12, x0, 0 // implicitly initialized within crt0`
112			`//addi x13, x0, 0 // implicitly initialized within crt0`
113	73	zero_gravi	`//addi x14, x0, 0 // implicitly initialized within crt0`
114			`//addi x15, x0, 0 // implicitly initialized within crt0`
115	61	zero_gravi
116
117			`// ************************************************************************************************`
118			`// Initialize integer register file (upper half, if no E extension)`
119			`// ************************************************************************************************`
120	32	zero_gravi	`#ifndef __riscv_32e`
121	61	zero_gravi	`// do not do this if compiling bootloader (to save some program space)`
122	32	zero_gravi	`#ifndef make_bootloader`
123			`addi x16, x0, 0`
124			`addi x17, x0, 0`
125			`addi x18, x0, 0`
126			`addi x19, x0, 0`
127			`addi x20, x0, 0`
128			`addi x21, x0, 0`
129			`addi x22, x0, 0`
130			`addi x23, x0, 0`
131			`addi x24, x0, 0`
132			`addi x25, x0, 0`
133			`addi x26, x0, 0`
134			`addi x27, x0, 0`
135			`addi x28, x0, 0`
136			`addi x29, x0, 0`
137			`addi x30, x0, 0`
138			`addi x31, x0, 0`
139			`#endif`
140			`#endif`
141
142
143	61	zero_gravi	`// ************************************************************************************************`
144	2	zero_gravi	`// Reset/deactivate IO/peripheral devices`
145	61	zero_gravi	`// Devices, that are not implemented, will cause a store bus access fault`
146	72	zero_gravi	`// that is catched (but not further processed) by the dummy trap handler.`
147	61	zero_gravi	`// ************************************************************************************************`
148	2	zero_gravi	`__crt0_reset_io:`
149	72	zero_gravi	`la x8, __crt0_io_space_begin // start of processor-internal IO region`
150			`la x9, __crt0_io_space_end // end of processor-internal IO region`
151	2	zero_gravi
152			`__crt0_reset_io_loop:`
153	58	zero_gravi	`sw zero, 0(x8)`
154			`addi x8, x8, 4`
155			`bne x8, x9, __crt0_reset_io_loop`
156	2	zero_gravi
157
158	61	zero_gravi	`// ************************************************************************************************`
159	72	zero_gravi	`// Copy initialized .data section from ROM to RAM (byte-wise)`
160	61	zero_gravi	`// ************************************************************************************************`
161	2	zero_gravi	`__crt0_copy_data:`
162	61	zero_gravi	`la x11, __crt0_copy_data_src_begin // start of data area (copy source)`
163			`la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)`
164			`la x13, __crt0_copy_data_dst_end // last address of destination data area`
165	2	zero_gravi
166			`__crt0_copy_data_loop:`
167			`bge x12, x13, __crt0_copy_data_loop_end`
168			`lb x14, 0(x11)`
169			`sb x14, 0(x12)`
170			`addi x11, x11, 1`
171			`addi x12, x12, 1`
172			`j __crt0_copy_data_loop`
173
174			`__crt0_copy_data_loop_end:`
175
176
177	61	zero_gravi	`// ************************************************************************************************`
178	73	zero_gravi	`// Clear .bss section (byte-wise)`
179			`// ************************************************************************************************`
180			`__crt0_clear_bss:`
181			`la x14, __crt0_bss_start`
182			`la x15, __crt0_bss_end`
183
184			`__crt0_clear_bss_loop:`
185			`bge x14, x15, __crt0_clear_bss_loop_end`
186			`sb zero, 0(x14)`
187			`addi x14, x14, 1`
188			`j __crt0_clear_bss_loop`
189
190			`__crt0_clear_bss_loop_end:`
191
192
193			`// ************************************************************************************************`
194	61	zero_gravi	`// Setup arguments and call main function`
195			`// ************************************************************************************************`
196	2	zero_gravi	`__crt0_main_entry:`
197	72	zero_gravi	`addi a0, zero, 0 // a0 = argc = 0`
198			`addi a1, zero, 0 // a1 = argv = 0`
199			`jal ra, main // call actual app's main function, this "should" not return`
200	2	zero_gravi
201	72	zero_gravi	`__crt0_main_exit: // main's "return" and "exit" will arrive here`
202			`csrw mscratch, a0 // backup main's return code to mscratch (for debugger)`
203	2	zero_gravi
204	72	zero_gravi
205	61	zero_gravi	`// ************************************************************************************************`
206			`// call "after main" handler (if there is any) if main really returns`
207			`// ************************************************************************************************`
208	72	zero_gravi	`#ifndef make_bootloader // after_main handler not supported for bootloader`
209
210	61	zero_gravi	`__crt0_main_aftermath:`
211			`.weak __neorv32_crt0_after_main`
212			`la ra, __neorv32_crt0_after_main`
213			`beqz ra, __crt0_main_aftermath_end // check if an aftermath handler has been specified`
214	72	zero_gravi	`jalr ra // execute handler with main's return code still in a0`
215
216			`__crt0_main_aftermath_end:`
217
218	61	zero_gravi	`#endif`
219	2	zero_gravi
220
221	61	zero_gravi	`// ************************************************************************************************`
222			`// go to endless sleep mode`
223			`// ************************************************************************************************`
224	72	zero_gravi	`__crt0_shutdown:`
225			`csrci mstatus, 8 // disable global IRQs (clear mstatus.mie)`
226			`wfi // go to sleep mode`
227	73	zero_gravi	`j . // endless loop`
228	2	zero_gravi
229	61	zero_gravi
230			`// ************************************************************************************************`
231			`// dummy trap handler (for exceptions & IRQs during very early boot stage)`
232	72	zero_gravi	`// does nothing but trying to move on to the next instruction`
233	61	zero_gravi	`// ************************************************************************************************`
234	21	zero_gravi	`.balign 4`
235	14	zero_gravi	`__crt0_dummy_trap_handler:`
236	2	zero_gravi
237	72	zero_gravi	`addi sp, sp, -8`
238			`sw x8, 0(sp)`
239			`sw x9, 4(sp)`
240	2	zero_gravi
241	61	zero_gravi	`csrr x8, mcause`
242			`blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt`
243	2	zero_gravi
244	61	zero_gravi	`csrr x8, mepc`
245	2	zero_gravi
246	61	zero_gravi	`__crt0_dummy_trap_handler_exc_c_check: // is compressed instruction?`
247			`lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception`
248			`andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)`
249	2	zero_gravi
250	61	zero_gravi	`addi x8, x8, +2 // only this for compressed instructions`
251			`csrw mepc, x8 // set return address when compressed instruction`
252	2	zero_gravi
253	61	zero_gravi	`addi x8, zero, 3`
254			`bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction`
255
256			`__crt0_dummy_trap_handler_exc_uncrompressed: // is uncompressed instruction!`
257			`csrr x8, mepc`
258			`addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions`
259	14	zero_gravi	`csrw mepc, x8`
260	2	zero_gravi
261	14	zero_gravi	`__crt0_dummy_trap_handler_irq:`
262	61	zero_gravi	`lw x8, 0(sp)`
263			`lw x9, 4(sp)`
264			`addi sp, sp, +8`
265	2	zero_gravi
266			`mret`
267
268	21	zero_gravi	`.cfi_endproc`
269			`.end`

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