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zero_gravi |
# NEORV32 Bit-Manipulation `B` Extension (`Zbb` sub-extension)
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:warning: The RISC-V bit-manipulation extension is frozen but not yet officially ratified.
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:warning: The NEORV32 bit manipulation extensions only supports the `Zbb` sub-extension
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(basic bit-manipulation operation) yet.
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The provided test program `main.c` verifies all currently implemented instruction by checking the results against a pure-software emulation model.
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The emulation functions as well as the available **intrinsics** for the `Zbb` extension are located in `neorv32_b_extension_intrinsics.h`.
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:information_source: More information regarding the RISC-V bit manipulation extension can be found in the officail GitHub repo:
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[github.com/riscv/riscv-bitmanip](https://github.com/riscv/riscv-bitmanip).
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The specification of the bit-manipulation spec supported by the NEORV32 can be found in `docs/references/bitmanip-draft.pdf`.
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