OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [example/] [bitmanip_test/] [main.c] - Blame information for rev 63

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 63 zero_gravi
// #################################################################################################
2
// # << NEORV32 - RISC-V Bit-Manipulation 'Zbb' Extension Test Program >>                          #
3
// # ********************************************************************************************* #
4
// # BSD 3-Clause License                                                                          #
5
// #                                                                                               #
6
// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7
// #                                                                                               #
8
// # Redistribution and use in source and binary forms, with or without modification, are          #
9
// # permitted provided that the following conditions are met:                                     #
10
// #                                                                                               #
11
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12
// #    conditions and the following disclaimer.                                                   #
13
// #                                                                                               #
14
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15
// #    conditions and the following disclaimer in the documentation and/or other materials        #
16
// #    provided with the distribution.                                                            #
17
// #                                                                                               #
18
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19
// #    endorse or promote products derived from this software without specific prior written      #
20
// #    permission.                                                                                #
21
// #                                                                                               #
22
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
31
// # ********************************************************************************************* #
32
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33
// #################################################################################################
34
 
35
 
36
/**********************************************************************//**
37
 * @file bitmanip_test/main.c
38
 * @author Stephan Nolting
39
 * @brief Test program for the NEORV32 'Zbb' extension using pseudo-random
40
 * data as input; compares results from hardware against pure-sw reference functions.
41
 **************************************************************************/
42
 
43
#include <neorv32.h>
44
#include "neorv32_b_extension_intrinsics.h"
45
 
46
/**********************************************************************//**
47
 * @name User configuration
48
 **************************************************************************/
49
/**@{*/
50
/** UART BAUD rate */
51
#define BAUD_RATE      (19200)
52
//** Number of test cases for each instruction */
53
#define NUM_TEST_CASES (1000000)
54
/**@}*/
55
 
56
 
57
// Prototypes
58
uint32_t xorshift32(void);
59
uint32_t check_result(uint32_t num, uint32_t opa, uint32_t opb, uint32_t ref, uint32_t res);
60
void print_report(int num_err, int num_tests);
61
 
62
 
63
/**********************************************************************//**
64
 * Main function; test all available operations of the NEORV32 'Zbb' extensions
65
 * using bit manipulation intrinsics and software-only reference functions (emulation).
66
 *
67
 * @note This program requires the Zbb CPU extension.
68
 *
69
 * @return Irrelevant.
70
 **************************************************************************/
71
int main() {
72
 
73
  uint32_t opa = 0, opb = 0, res_hw = 0, res_sw = 0;
74
  uint32_t i = 0, err_cnt = 0;
75
  const uint32_t num_tests = (int)NUM_TEST_CASES;
76
 
77
  // capture all exceptions and give debug info via UART
78
  neorv32_rte_setup();
79
 
80
  // init UART at default baud rate, no parity bits, ho hw flow control
81
  neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
82
 
83
// Disable compilation by default
84
#ifndef RUN_CHECK
85
  #warning Program HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.
86
 
87
  // inform the user if you are actually executing this
88
  neorv32_uart_printf("ERROR! Program has not been compiled. Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.\n");
89
 
90
  return 1;
91
#endif
92
 
93
  // intro
94
  neorv32_uart_printf("NEORV32 'Zbb' Bit-Manipulation Extension Test\n\n");
95
 
96
  // check available hardware extensions and compare with compiler flags
97
  neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
98
 
99
  // check if Zbb extension is implemented at all
100
  if ((SYSINFO_CPU & (1<<SYSINFO_CPU_ZBB)) == 0) {
101
    neorv32_uart_print("Error! <Zbb> extension not synthesized!\n");
102
    return 1;
103
  }
104
 
105
  neorv32_uart_printf("Starting Zbb bit-manipulation extension tests (%i test cases per instruction)...\n", num_tests);
106
 
107
  // ANDN
108
  neorv32_uart_printf("\nANDN:\n");
109
  err_cnt = 0;
110
  for (i=0;i<num_tests; i++) {
111
    opa = xorshift32();
112
    opb = xorshift32();
113
    res_sw = riscv_emulate_andn(opa, opb);
114
    res_hw = riscv_intrinsic_andn(opa, opb);
115
    err_cnt += check_result(i, opa, opb, res_sw, res_hw);
116
  }
117
  print_report(err_cnt, num_tests);
118
 
119
  // ORN
120
  neorv32_uart_printf("\nORN:\n");
121
  err_cnt = 0;
122
  for (i=0;i<num_tests; i++) {
123
    opa = xorshift32();
124
    opb = xorshift32();
125
    res_sw = riscv_emulate_orn(opa, opb);
126
    res_hw = riscv_intrinsic_orn(opa, opb);
127
    err_cnt += check_result(i, opa, opb, res_sw, res_hw);
128
  }
129
  print_report(err_cnt, num_tests);
130
 
131
  // XNOR
132
  neorv32_uart_printf("\nXNOR:\n");
133
  err_cnt = 0;
134
  for (i=0;i<num_tests; i++) {
135
    opa = xorshift32();
136
    opb = xorshift32();
137
    res_sw = riscv_emulate_xnor(opa, opb);
138
    res_hw = riscv_intrinsic_xnor(opa, opb);
139
    err_cnt += check_result(i, opa, opb, res_sw, res_hw);
140
  }
141
  print_report(err_cnt, num_tests);
142
 
143
 
144
 
145
  // CLZ
146
  neorv32_uart_printf("\nCLZ:\n");
147
  err_cnt = 0;
148
  for (i=0;i<num_tests; i++) {
149
    opa = xorshift32();
150
    res_sw = riscv_emulate_clz(opa);
151
    res_hw = riscv_intrinsic_clz(opa);
152
    err_cnt += check_result(i, opa, 0, res_sw, res_hw);
153
  }
154
  print_report(err_cnt, num_tests);
155
 
156
  // CTZ
157
  neorv32_uart_printf("\nCTZ:\n");
158
  err_cnt = 0;
159
  for (i=0;i<num_tests; i++) {
160
    opa = xorshift32();
161
    res_sw = riscv_emulate_ctz(opa);
162
    res_hw = riscv_intrinsic_ctz(opa);
163
    err_cnt += check_result(i, opa, 0, res_sw, res_hw);
164
  }
165
  print_report(err_cnt, num_tests);
166
 
167
 
168
 
169
  // CPOP
170
  neorv32_uart_printf("\nCPOP:\n");
171
  err_cnt = 0;
172
  for (i=0;i<num_tests; i++) {
173
    opa = xorshift32();
174
    res_sw = riscv_emulate_cpop(opa);
175
    res_hw = riscv_intrinsic_cpop(opa);
176
    err_cnt += check_result(i, opa, 0, res_sw, res_hw);
177
  }
178
  print_report(err_cnt, num_tests);
179
 
180
 
181
 
182
  // MAX
183
  neorv32_uart_printf("\nMAX:\n");
184
  err_cnt = 0;
185
  for (i=0;i<num_tests; i++) {
186
    opa = xorshift32();
187
    opb = xorshift32();
188
    res_sw = riscv_emulate_max(opa, opb);
189
    res_hw = riscv_intrinsic_max(opa, opb);
190
    err_cnt += check_result(i, opa, opb, res_sw, res_hw);
191
  }
192
  print_report(err_cnt, num_tests);
193
 
194
  // MAXU
195
  neorv32_uart_printf("\nMAXU:\n");
196
  err_cnt = 0;
197
  for (i=0;i<num_tests; i++) {
198
    opa = xorshift32();
199
    opb = xorshift32();
200
    res_sw = riscv_emulate_maxu(opa, opb);
201
    res_hw = riscv_intrinsic_maxu(opa, opb);
202
    err_cnt += check_result(i, opa, opb, res_sw, res_hw);
203
  }
204
  print_report(err_cnt, num_tests);
205
 
206
  // MIN
207
  neorv32_uart_printf("\nMIN:\n");
208
  err_cnt = 0;
209
  for (i=0;i<num_tests; i++) {
210
    opa = xorshift32();
211
    opb = xorshift32();
212
    res_sw = riscv_emulate_min(opa, opb);
213
    res_hw = riscv_intrinsic_min(opa, opb);
214
    err_cnt += check_result(i, opa, opb, res_sw, res_hw);
215
  }
216
  print_report(err_cnt, num_tests);
217
 
218
  // MINU
219
  neorv32_uart_printf("\nMINU:\n");
220
  err_cnt = 0;
221
  for (i=0;i<num_tests; i++) {
222
    opa = xorshift32();
223
    opb = xorshift32();
224
    res_sw = riscv_emulate_minu(opa, opb);
225
    res_hw = riscv_intrinsic_minu(opa, opb);
226
    err_cnt += check_result(i, opa, opb, res_sw, res_hw);
227
  }
228
  print_report(err_cnt, num_tests);
229
 
230
 
231
 
232
  // SEXT.B
233
  neorv32_uart_printf("\nSEXT.B:\n");
234
  err_cnt = 0;
235
  for (i=0;i<num_tests; i++) {
236
    opa = xorshift32();
237
    res_sw = riscv_emulate_sextb(opa);
238
    res_hw = riscv_intrinsic_sextb(opa);
239
    err_cnt += check_result(i, opa, 0, res_sw, res_hw);
240
  }
241
  print_report(err_cnt, num_tests);
242
 
243
  // SEXT.H
244
  neorv32_uart_printf("\nSEXT.H:\n");
245
  err_cnt = 0;
246
  for (i=0;i<num_tests; i++) {
247
    opa = xorshift32();
248
    res_sw = riscv_emulate_sexth(opa);
249
    res_hw = riscv_intrinsic_sexth(opa);
250
    err_cnt += check_result(i, opa, 0, res_sw, res_hw);
251
  }
252
  print_report(err_cnt, num_tests);
253
 
254
  // ZEXT.H
255
  neorv32_uart_printf("\nZEXT.H:\n");
256
  err_cnt = 0;
257
  for (i=0;i<num_tests; i++) {
258
    opa = xorshift32();
259
    res_sw = riscv_emulate_zexth(opa);
260
    res_hw = riscv_intrinsic_zexth(opa);
261
    err_cnt += check_result(i, opa, 0, res_sw, res_hw);
262
  }
263
  print_report(err_cnt, num_tests);
264
 
265
 
266
 
267
  // ROL
268
  neorv32_uart_printf("\nROL:\n");
269
  err_cnt = 0;
270
  for (i=0;i<num_tests; i++) {
271
    opa = xorshift32();
272
    opb = xorshift32();
273
    res_sw = riscv_emulate_rol(opa, opb);
274
    res_hw = riscv_intrinsic_rol(opa, opb);
275
    err_cnt += check_result(i, opa, opb, res_sw, res_hw);
276
  }
277
  print_report(err_cnt, num_tests);
278
 
279
  // ROR
280
  neorv32_uart_printf("\nROR:\n");
281
  err_cnt = 0;
282
  for (i=0;i<num_tests; i++) {
283
    opa = xorshift32();
284
    opb = xorshift32();
285
    res_sw = riscv_emulate_ror(opa, opb);
286
    res_hw = riscv_intrinsic_ror(opa, opb);
287
    err_cnt += check_result(i, opa, opb, res_sw, res_hw);
288
  }
289
  print_report(err_cnt, num_tests);
290
 
291
  // RORI
292
  neorv32_uart_printf("\nRORI (imm=20):\n"); // FIXME: static immediate
293
  err_cnt = 0;
294
  for (i=0;i<num_tests; i++) {
295
    opa = xorshift32();
296
    res_sw = riscv_emulate_ror(opa, 20);
297
    res_hw = riscv_intrinsic_rori20(opa);
298
    err_cnt += check_result(i, opa, opb, res_sw, res_hw);
299
  }
300
  print_report(err_cnt, num_tests);
301
 
302
 
303
 
304
  // ORC.B
305
  neorv32_uart_printf("\nORCB:\n");
306
  err_cnt = 0;
307
  for (i=0;i<num_tests; i++) {
308
    opa = xorshift32();
309
    res_sw = riscv_emulate_orcb(opa);
310
    res_hw = riscv_intrinsic_orcb(opa);
311
    err_cnt += check_result(i, opa, 0, res_sw, res_hw);
312
  }
313
  print_report(err_cnt, num_tests);
314
 
315
 
316
 
317
  // REV8
318
  neorv32_uart_printf("\nREV8:\n");
319
  err_cnt = 0;
320
  for (i=0;i<num_tests; i++) {
321
    opa = xorshift32();
322
    res_sw = riscv_emulate_rev8(opa);
323
    res_hw = riscv_intrinsic_rev8(opa);
324
    err_cnt += check_result(i, opa, 0, res_sw, res_hw);
325
  }
326
  print_report(err_cnt, num_tests);
327
 
328
 
329
  neorv32_uart_printf("\nBit manipulation extension tests done.\n");
330
 
331
  return 0;
332
}
333
 
334
 
335
/**********************************************************************//**
336
 * Pseudo-Random Number Generator (to generate test vectors).
337
 *
338
 * @return Random data (32-bit).
339
 **************************************************************************/
340
uint32_t xorshift32(void) {
341
 
342
  static uint32_t x32 = 314159265;
343
 
344
  x32 ^= x32 << 13;
345
  x32 ^= x32 >> 17;
346
  x32 ^= x32 << 5;
347
 
348
  return x32;
349
}
350
 
351
 
352
/**********************************************************************//**
353
 * Check results (reference (SW) vs actual hardware).
354
 *
355
 * @param[in] num Test case number
356
 * @param[in] opa Operand 1
357
 * @param[in] opb Operand 2
358
 * @param[in] ref Software reference
359
 * @param[in] res Actual results
360
 * @return zero if results are equal.
361
 **************************************************************************/
362
uint32_t check_result(uint32_t num, uint32_t opa, uint32_t opb, uint32_t ref, uint32_t res) {
363
 
364
  if (ref != res) {
365
    neorv32_uart_printf("%u: opa = 0x%x, opb = 0x%x : ref = 0x%x vs res = 0x%x ", num, opa, opb, ref, res);
366
    neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
367
    return 1;
368
  }
369
  else {
370
    return 0;
371
  }
372
}
373
 
374
 
375
/**********************************************************************//**
376
 * Print test report.
377
 *
378
 * @param[in] num_err Number or errors in this test.
379
 * @param[in] num_tests Total number of conducted tests.
380
 **************************************************************************/
381
void print_report(int num_err, int num_tests) {
382
 
383
  neorv32_uart_printf("Errors: %i/%i ", num_err, num_tests);
384
 
385
  if (num_err == 0) {
386
    neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
387
  }
388
  else {
389
    neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
390
  }
391
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.