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[/] [neorv32/] [trunk/] [sw/] [example/] [processor_check/] [main.c] - Blame information for rev 67

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1 59 zero_gravi 
// #################################################################################################
2 
// # << NEORV32 - Processor Test Program >>                                                        #
3 
// # ********************************************************************************************* #
4 
// # BSD 3-Clause License                                                                          #
5 
// #                                                                                               #
6 
// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 
// #                                                                                               #
8 
// # Redistribution and use in source and binary forms, with or without modification, are          #
9 
// # permitted provided that the following conditions are met:                                     #
10 
// #                                                                                               #
11 
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12 
// #    conditions and the following disclaimer.                                                   #
13 
// #                                                                                               #
14 
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15 
// #    conditions and the following disclaimer in the documentation and/or other materials        #
16 
// #    provided with the distribution.                                                            #
17 
// #                                                                                               #
18 
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19 
// #    endorse or promote products derived from this software without specific prior written      #
20 
// #    permission.                                                                                #
21 
// #                                                                                               #
22 
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23 
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24 
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25 
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26 
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27 
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28 
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29 
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30 
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
31 
// # ********************************************************************************************* #
32 
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33 
// #################################################################################################
34 
 
35 
 
36 
/**********************************************************************//**
37 
 * @file processor_check/main.c
38 
 * @author Stephan Nolting
39 
 * @brief CPU/Processor test program.
40 
 **************************************************************************/
41 
 
42 
#include <neorv32.h>
43 
#include <string.h>
44 
 
45 
 
46 
/**********************************************************************//**
47 
 * @name User configuration
48 
 **************************************************************************/
49 
/**@{*/
50 
/** UART BAUD rate */
51 
#define BAUD_RATE           (19200)
52 
//** Reachable unaligned address */
53 64 zero_gravi 
#define ADDR_UNALIGNED_1    (0x00000001)
54 
//** Reachable unaligned address */
55 
#define ADDR_UNALIGNED_2    (0x00000002)
56 59 zero_gravi 
//** Unreachable word-aligned address */
57 
#define ADDR_UNREACHABLE    (IO_BASE_ADDRESS-4)
58 
//** external memory base address */
59 
#define EXT_MEM_BASE        (0xF0000000)
60 
/**@}*/
61 
 
62 
 
63 61 zero_gravi 
/**********************************************************************//**
64 
 * @name UART print macros
65 
 **************************************************************************/
66 
/**@{*/
67 
//** for simulation only! */
68 
#ifdef SUPPRESS_OPTIONAL_UART_PRINT
69 
//** print standard output to UART0 */
70 
#define PRINT_STANDARD(...)
71 
//** print critical output to UART1 */
72 
#define PRINT_CRITICAL(...) neorv32_uart1_printf(__VA_ARGS__)
73 
#else
74 
//** print standard output to UART0 */
75 
#define PRINT_STANDARD(...) neorv32_uart0_printf(__VA_ARGS__)
76 
//** print critical output to UART0 */
77 
#define PRINT_CRITICAL(...) neorv32_uart0_printf(__VA_ARGS__)
78 
#endif
79 
/**@}*/
80 
 
81 
 
82 59 zero_gravi 
// Prototypes
83 
void sim_irq_trigger(uint32_t sel);
84 
void global_trap_handler(void);
85 61 zero_gravi 
void xirq_trap_handler0(void);
86 
void xirq_trap_handler1(void);
87 59 zero_gravi 
void test_ok(void);
88 
void test_fail(void);
89 
 
90 
// Global variables (also test initialization of global vars here)
91 
/// Global counter for failing tests
92 
int cnt_fail = 0;
93 
/// Global counter for successful tests
94 
int cnt_ok   = 0;
95 
/// Global counter for total number of tests
96 
int cnt_test = 0;
97 61 zero_gravi 
/// Global number of available HPMs
98 59 zero_gravi 
uint32_t num_hpm_cnts_global = 0;
99 61 zero_gravi 
/// XIRQ trap handler acknowledge
100 
uint32_t xirq_trap_handler_ack = 0;
101 59 zero_gravi 
 
102 61 zero_gravi 
/// Variable to test atomic accesses
103 59 zero_gravi 
uint32_t atomic_access_addr;
104 
 
105 
 
106 
/**********************************************************************//**
107 
 * High-level CPU/processor test program.
108 
 *
109 
 * @note Applications has to be compiler with <USER_FLAGS+=-DRUN_CPUTEST>
110 61 zero_gravi 
 * @warning This test is intended for simulation only.
111 
 * @warning This test requires all optional extensions/modules to be enabled.
112 59 zero_gravi 
 *
113 60 zero_gravi 
 * @return 0 if execution was successful
114 59 zero_gravi 
 **************************************************************************/
115 
int main() {
116 
 
117 
  register uint32_t tmp_a, tmp_b;
118 
  uint8_t id;
119 
 
120 64 zero_gravi 
  // disable global interrupts
121 
  neorv32_cpu_dint();
122 59 zero_gravi 
 
123 61 zero_gravi 
  // init UARTs at default baud rate, no parity bits, no hw flow control
124 
  neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
125 64 zero_gravi 
  NEORV32_UART1.CTRL = NEORV32_UART0.CTRL; // copy configuration to initialize UART1
126 59 zero_gravi 
 
127 61 zero_gravi 
#ifdef SUPPRESS_OPTIONAL_UART_PRINT
128 
  neorv32_uart0_disable(); // do not generate any UART0 output
129 
#endif
130 
 
131 59 zero_gravi 
// Disable processor_check compilation by default
132 
#ifndef RUN_CHECK
133 
  #warning processor_check HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.
134 
 
135 
  // inform the user if you are actually executing this
136 61 zero_gravi 
  PRINT_CRITICAL("ERROR! processor_check has not been compiled. Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.\n");
137 59 zero_gravi 
 
138 60 zero_gravi 
  return 1;
139 59 zero_gravi 
#endif
140 
 
141 
 
142 
  // ----------------------------------------------
143 
  // setup RTE
144 
  neorv32_rte_setup(); // this will install a full-detailed debug handler for ALL traps
145 
  // ----------------------------------------------
146 
 
147 
  // check available hardware extensions and compare with compiler flags
148 
  neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
149 
 
150 
 
151 
  // intro
152 61 zero_gravi 
  PRINT_STANDARD("\n<< PROCESSOR CHECK >>\n");
153 
  PRINT_STANDARD("build: "__DATE__" "__TIME__"\n");
154 59 zero_gravi 
 
155 
 
156 
  // reset performance counter
157 66 zero_gravi 
  // neorv32_cpu_csr_write(CSR_MCYCLEH, 0);   -> done in crt0.S
158 
  // neorv32_cpu_csr_write(CSR_MCYCLE, 0);    -> done in crt0.S
159 
  // neorv32_cpu_csr_write(CSR_MINSTRETH, 0); -> done in crt0.S
160 
  // neorv32_cpu_csr_write(CSR_MINSTRET, 0);  -> done in crt0.S
161 59 zero_gravi 
  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable performance counter auto increment (ALL counters)
162 
  neorv32_cpu_csr_write(CSR_MCOUNTEREN, 7); // allow access from user-mode code to standard counters only
163 
 
164 64 zero_gravi 
  // set CMP of machine system timer MTIME to max to prevent an IRQ
165 
  neorv32_mtime_set_timecmp(-1);
166 59 zero_gravi 
  neorv32_mtime_set_time(0);
167 
 
168 
 
169 
  // fancy intro
170 
  // -----------------------------------------------
171 
  // logo
172 
  neorv32_rte_print_logo();
173 
 
174 
  // show project credits
175 
  neorv32_rte_print_credits();
176 
 
177 
  // show full HW config report
178 
  neorv32_rte_print_hw_config();
179 
 
180 
 
181 
  // configure RTE
182 
  // -----------------------------------------------
183 66 zero_gravi 
  PRINT_STANDARD("\n\nRTE setup... ");
184 59 zero_gravi 
 
185 
  int install_err = 0;
186 
  // initialize ALL provided trap handler (overriding the default debug handlers)
187 
  for (id=0; id<NEORV32_RTE_NUM_TRAPS; id++) {
188 
    install_err += neorv32_rte_exception_install(id, global_trap_handler);
189 
  }
190 
  if (install_err) {
191 66 zero_gravi 
    PRINT_CRITICAL("ERROR!\n");
192 60 zero_gravi 
    return 1;
193 59 zero_gravi 
  }
194 
 
195 64 zero_gravi 
  // clear testbench IRQ triggers
196 
  sim_irq_trigger(0);
197 59 zero_gravi 
 
198 64 zero_gravi 
  // clear all interrupt enables, enable only where needed
199 
  neorv32_cpu_csr_write(CSR_MIE, 0);
200 
 
201 59 zero_gravi 
  // test intro
202 66 zero_gravi 
  PRINT_STANDARD("\nStarting tests.\n\n");
203 59 zero_gravi 
 
204 67 zero_gravi 
  // sync (test)
205 
  asm volatile ("fence.i");
206 
 
207 59 zero_gravi 
  // enable global interrupts
208 
  neorv32_cpu_eint();
209 
 
210 
 
211 63 zero_gravi 
  // **********************************************************************************************
212 
  // Run CPU and SoC tests
213 
  // **********************************************************************************************
214 
 
215 
 
216 59 zero_gravi 
  // ----------------------------------------------------------
217 63 zero_gravi 
  // Test performance counter: setup as many events and counter as feasible
218 
  // ----------------------------------------------------------
219 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
220 66 zero_gravi 
  PRINT_STANDARD("[%i] Setup HPM events: ", cnt_test);
221 63 zero_gravi 
 
222 
  num_hpm_cnts_global = neorv32_cpu_hpm_get_counters();
223 
 
224 
  if (num_hpm_cnts_global != 0) {
225 
    cnt_test++;
226 
 
227 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER3,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT3,  1 << HPMCNT_EVENT_CIR);
228 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER4,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT4,  1 << HPMCNT_EVENT_WAIT_IF);
229 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER5,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT5,  1 << HPMCNT_EVENT_WAIT_II);
230 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER6,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT6,  1 << HPMCNT_EVENT_WAIT_MC);
231 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER7,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT7,  1 << HPMCNT_EVENT_LOAD);
232 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER8,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT8,  1 << HPMCNT_EVENT_STORE);
233 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER9,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT9,  1 << HPMCNT_EVENT_WAIT_LS);
234 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT10, 1 << HPMCNT_EVENT_JUMP);
235 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_BRANCH);
236 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT12, 1 << HPMCNT_EVENT_TBRANCH);
237 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT13, 1 << HPMCNT_EVENT_TRAP);
238 
    neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT14, 1 << HPMCNT_EVENT_ILLEGAL);
239 
 
240 
    neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable all counters
241 
 
242 
    // make sure there was no exception
243 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
244 
      test_ok();
245 
    }
246 
    else {
247 
      test_fail();
248 
    }
249 
  }
250 
  else {
251 
    PRINT_STANDARD("skipped (n.a.)\n");
252 
  }
253 
 
254 
 
255 
  // ----------------------------------------------------------
256 59 zero_gravi 
  // Test standard RISC-V performance counter [m]cycle[h]
257 
  // ----------------------------------------------------------
258 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
259 66 zero_gravi 
  PRINT_STANDARD("[%i] cycle counter: ", cnt_test);
260 59 zero_gravi 
 
261 
  cnt_test++;
262 
 
263 
  // make sure counter is enabled
264 
  asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_CY));
265 
 
266 61 zero_gravi 
  // prepare overflow
267 
  neorv32_cpu_set_mcycle(0x00000000FFFFFFFFULL);
268 59 zero_gravi 
 
269 61 zero_gravi 
  // get current cycle counter HIGH
270 
  tmp_a = neorv32_cpu_csr_read(CSR_MCYCLEH);
271 
 
272 
  // make sure cycle counter high has incremented and there was no exception during access
273 
  if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
274 59 zero_gravi 
    test_ok();
275 
  }
276 
  else {
277 
    test_fail();
278 
  }
279 
 
280 
 
281 
  // ----------------------------------------------------------
282 
  // Test standard RISC-V performance counter [m]instret[h]
283 
  // ----------------------------------------------------------
284 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
285 66 zero_gravi 
  PRINT_STANDARD("[%i] instret counter: ", cnt_test);
286 59 zero_gravi 
 
287 
  cnt_test++;
288 
 
289 
  // make sure counter is enabled
290 
  asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_IR));
291 
 
292 61 zero_gravi 
  // prepare overflow
293 
  neorv32_cpu_set_minstret(0x00000000FFFFFFFFULL);
294 59 zero_gravi 
 
295 61 zero_gravi 
  // get instruction counter HIGH
296 
  tmp_a = neorv32_cpu_csr_read(CSR_INSTRETH);
297 
 
298 
  // make sure instruction counter high has incremented and there was no exception during access
299 
  if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
300 
    test_ok();
301 59 zero_gravi 
  }
302 
  else {
303 
    test_fail();
304 
  }
305 
 
306 
 
307 
  // ----------------------------------------------------------
308 
  // Test mcountinhibt: inhibit auto-inc of [m]cycle
309 
  // ----------------------------------------------------------
310 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
311 61 zero_gravi 
  PRINT_STANDARD("[%i] mcountinhibt.cy CSR: ", cnt_test);
312 59 zero_gravi 
 
313 
  cnt_test++;
314 
 
315 
  // inhibit [m]cycle CSR
316 
  tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
317 
  tmp_a |= (1<<CSR_MCOUNTINHIBIT_CY); // inhibit cycle counter auto-increment
318 
  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp_a);
319 
 
320 
  // get current cycle counter
321 
  tmp_a = neorv32_cpu_csr_read(CSR_CYCLE);
322 
 
323 
  // wait some time to have a nice "increment" (there should be NO increment at all!)
324 
  asm volatile ("nop");
325 
  asm volatile ("nop");
326 
 
327 
  tmp_b = neorv32_cpu_csr_read(CSR_CYCLE);
328 
 
329 
  // make sure instruction counter has NOT incremented and there was no exception during access
330 
  if ((tmp_a == tmp_b) && (tmp_a != 0) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
331 
    test_ok();
332 
  }
333 
  else {
334 
    test_fail();
335 
  }
336 
 
337 
  // re-enable [m]cycle CSR
338 
  tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
339 
  tmp_a &= ~(1<<CSR_MCOUNTINHIBIT_CY); // clear inhibit of cycle counter auto-increment
340 
  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp_a);
341 
 
342 
 
343 
  // ----------------------------------------------------------
344 
  // Test mcounteren: do not allow cycle[h] access from user-mode
345 
  // ----------------------------------------------------------
346 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
347 61 zero_gravi 
  PRINT_STANDARD("[%i] mcounteren.cy CSR: ", cnt_test);
348 59 zero_gravi 
 
349 64 zero_gravi 
  cnt_test++;
350 59 zero_gravi 
 
351 64 zero_gravi 
  // do not allow user-level code to access cycle[h] CSRs
352 
  tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);
353 
  tmp_a &= ~(1<<CSR_MCOUNTEREN_CY); // clear access right
354 
  neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
355 59 zero_gravi 
 
356 65 zero_gravi 
  neorv32_cpu_csr_write(CSR_CYCLE, 1); // make sure CSR is != 0 for this test
357 
 
358 64 zero_gravi 
  // switch to user mode (hart will be back in MACHINE mode when trap handler returns)
359 
  neorv32_cpu_goto_user_mode();
360 
  {
361 
    // access to cycle CSR is no longer allowed
362 65 zero_gravi 
    asm volatile (" mv      %[result], zero  \n" // initialize with zero
363 
                  " rdcycle %[result]          " // read CSR_CYCLE, is not allowed and should not alter [result]
364 
                  : [result] "=r" (tmp_a) : );
365 64 zero_gravi 
  }
366 59 zero_gravi 
 
367 65 zero_gravi 
  if (tmp_a != 0) {
368 
    PRINT_CRITICAL("%c[1m<SECURITY FAILURE> %c[0m\n", 27, 27);
369 
  }
370 
 
371 64 zero_gravi 
  // make sure there was an illegal instruction trap
372 65 zero_gravi 
  if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) && (tmp_a == 0)) {
373 64 zero_gravi 
    test_ok();
374 59 zero_gravi 
  }
375 64 zero_gravi 
  else {
376 
    test_fail();
377 59 zero_gravi 
  }
378 
 
379 
  // re-allow user-level code to access cycle[h] CSRs
380 
  tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);
381 
  tmp_a |= (1<<CSR_MCOUNTEREN_CY); // re-allow access right
382 
  neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
383 
 
384 
 
385 
  // ----------------------------------------------------------
386 62 zero_gravi 
  // Execute MRET in U-mode (has to trap!)
387 
  // ----------------------------------------------------------
388 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
389 
  PRINT_STANDARD("[%i] MRET in U-mode: ", cnt_test);
390 
 
391 64 zero_gravi 
  cnt_test++;
392 62 zero_gravi 
 
393 64 zero_gravi 
  // switch to user mode (hart will be back in MACHINE mode when trap handler returns)
394 
  neorv32_cpu_goto_user_mode();
395 
  {
396 
    asm volatile ("mret");
397 
  }
398 62 zero_gravi 
 
399 64 zero_gravi 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
400 
    test_ok();
401 62 zero_gravi 
  }
402 
  else {
403 64 zero_gravi 
    test_fail();
404 62 zero_gravi 
  }
405 
 
406 
 
407 
  // ----------------------------------------------------------
408 59 zero_gravi 
  // External memory interface test
409 
  // ----------------------------------------------------------
410 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
411 61 zero_gravi 
  PRINT_STANDARD("[%i] External memory access (@ 0x%x): ", cnt_test, (uint32_t)EXT_MEM_BASE);
412 59 zero_gravi 
 
413 64 zero_gravi 
  if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_EXT)) {
414 61 zero_gravi 
    cnt_test++;
415 59 zero_gravi 
 
416 61 zero_gravi 
    // create test program in RAM
417 
    static const uint32_t dummy_ext_program[2] __attribute__((aligned(8))) = {
418 
      0x3407D073, // csrwi mscratch, 15
419 
      0x00008067  // ret (32-bit)
420 
    };
421 59 zero_gravi 
 
422 61 zero_gravi 
    // copy to external memory
423 
    if (memcpy((void*)EXT_MEM_BASE, (void*)&dummy_ext_program, (size_t)sizeof(dummy_ext_program)) == NULL) {
424 
      test_fail();
425 
    }
426 
    else {
427 59 zero_gravi 
 
428 61 zero_gravi 
      // execute program
429 
      tmp_a = (uint32_t)EXT_MEM_BASE; // call the dummy sub program
430 
      asm volatile ("jalr ra, %[input_i]" :  : [input_i] "r" (tmp_a));
431 
 
432 
      if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) { // make sure there was no exception
433 
        if (neorv32_cpu_csr_read(CSR_MSCRATCH) == 15) { // make sure the program was executed in the right way
434 
          test_ok();
435 59 zero_gravi 
        }
436 
        else {
437 
          test_fail();
438 
        }
439 
      }
440 61 zero_gravi 
      else {
441 
        test_fail();
442 
      }
443 59 zero_gravi 
    }
444 
  }
445 
  else {
446 61 zero_gravi 
    PRINT_STANDARD("skipped (n.a.)\n");
447 59 zero_gravi 
  }
448 
 
449 
 
450 61 zero_gravi 
  // ----------------------------------------------------------
451 59 zero_gravi 
  // Illegal CSR access (CSR not implemented)
452 
  // ----------------------------------------------------------
453 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
454 61 zero_gravi 
  PRINT_STANDARD("[%i] Non-existent CSR access: ", cnt_test);
455 59 zero_gravi 
 
456 
  cnt_test++;
457 
 
458 61 zero_gravi 
  tmp_a = neorv32_cpu_csr_read(0xfff); // CSR 0xfff not implemented
459 59 zero_gravi 
 
460 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
461 
    test_ok();
462 
  }
463 
  else {
464 
    test_fail();
465 
  }
466 
 
467 
 
468 
  // ----------------------------------------------------------
469 
  // Write-access to read-only CSR
470 
  // ----------------------------------------------------------
471 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
472 61 zero_gravi 
  PRINT_STANDARD("[%i] Read-only CSR write access: ", cnt_test);
473 59 zero_gravi 
 
474 
  cnt_test++;
475 
 
476 
  neorv32_cpu_csr_write(CSR_TIME, 0); // time CSR is read-only
477 
 
478 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
479 
    test_ok();
480 
  }
481 
  else {
482 
    test_fail();
483 
  }
484 
 
485 
 
486 
  // ----------------------------------------------------------
487 
  // No "real" CSR write access (because rs1 = r0)
488 
  // ----------------------------------------------------------
489 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
490 61 zero_gravi 
  PRINT_STANDARD("[%i] Read-only CSR 'no-write' (rs1=0) access: ", cnt_test);
491 59 zero_gravi 
 
492 
  cnt_test++;
493 
 
494 
  // time CSR is read-only, but no actual write is performed because rs1=r0
495 
  // -> should cause no exception
496 
  asm volatile("csrrs zero, time, zero");
497 
 
498 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
499 
    test_ok();
500 
  }
501 
  else {
502 
    test_fail();
503 
  }
504 
 
505 
 
506 
  // ----------------------------------------------------------
507 
  // Unaligned instruction address
508 
  // ----------------------------------------------------------
509 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
510 61 zero_gravi 
  PRINT_STANDARD("[%i] I_ALIGN (instr. alignment) EXC: ", cnt_test);
511 59 zero_gravi 
 
512 
  // skip if C-mode is implemented
513 61 zero_gravi 
  if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C)) == 0) {
514 59 zero_gravi 
 
515 
    cnt_test++;
516 
 
517 
    // call unaligned address
518 64 zero_gravi 
    ((void (*)(void))ADDR_UNALIGNED_2)();
519 
    asm volatile("nop");
520 59 zero_gravi 
 
521 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_MISALIGNED) {
522 64 zero_gravi 
      test_ok();
523 59 zero_gravi 
    }
524 
    else {
525 64 zero_gravi 
      test_fail();
526 59 zero_gravi 
    }
527 64 zero_gravi 
 
528 59 zero_gravi 
  }
529 
  else {
530 61 zero_gravi 
    PRINT_STANDARD("skipped (n.a. with C-ext)\n");
531 59 zero_gravi 
  }
532 
 
533 
 
534 
  // ----------------------------------------------------------
535 
  // Instruction access fault
536 
  // ----------------------------------------------------------
537 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
538 61 zero_gravi 
  PRINT_STANDARD("[%i] I_ACC (instr. bus access) EXC: ", cnt_test);
539 59 zero_gravi 
  cnt_test++;
540 
 
541 
  // call unreachable aligned address
542 
  ((void (*)(void))ADDR_UNREACHABLE)();
543 
 
544 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ACCESS) {
545 
    test_ok();
546 
  }
547 
  else {
548 
    test_fail();
549 
  }
550 
 
551 
 
552 
  // ----------------------------------------------------------
553 
  // Illegal instruction
554 
  // ----------------------------------------------------------
555 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
556 61 zero_gravi 
  PRINT_STANDARD("[%i] I_ILLEG (illegal instr.) EXC: ", cnt_test);
557 59 zero_gravi 
 
558 
  cnt_test++;
559 
 
560 66 zero_gravi 
  // illegal 32-bit instruction (malformed SUB)
561 
  asm volatile (".align 4 \n"
562 
                ".word 0x80000033");
563 59 zero_gravi 
 
564 
  // make sure this has cause an illegal exception
565 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
566 
    // make sure this is really the instruction that caused the exception
567 66 zero_gravi 
    // -> for illegal instructions MTVAL contains the faulting instruction word
568 
    if (neorv32_cpu_csr_read(CSR_MTVAL) == 0x80000033) {
569 59 zero_gravi 
      test_ok();
570 
    }
571 
    else {
572 
      test_fail();
573 
    }
574 
  }
575 
  else {
576 
    test_fail();
577 
  }
578 
 
579 
 
580 
  // ----------------------------------------------------------
581 
  // Illegal compressed instruction
582 
  // ----------------------------------------------------------
583 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
584 61 zero_gravi 
  PRINT_STANDARD("[%i] CI_ILLEG (illegal compr. instr.) EXC: ", cnt_test);
585 59 zero_gravi 
 
586 
  // skip if C-mode is not implemented
587 64 zero_gravi 
  if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C))) {
588 59 zero_gravi 
 
589 
    cnt_test++;
590 
 
591 66 zero_gravi 
    // illegal 16-bit instruction (official UNIMP instruction)
592 
    asm volatile (".align 2     \n"
593 
                  ".half 0x0001 \n" // NOP
594 
                  ".half 0x0000");  // UNIMP
595 59 zero_gravi 
 
596 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
597 
      test_ok();
598 
    }
599 
    else {
600 
      test_fail();
601 
    }
602 
  }
603 
  else {
604 61 zero_gravi 
    PRINT_STANDARD("skipped (n.a. with C-ext)\n");
605 59 zero_gravi 
  }
606 
 
607 
 
608 
  // ----------------------------------------------------------
609 
  // Breakpoint instruction
610 
  // ----------------------------------------------------------
611 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
612 61 zero_gravi 
  PRINT_STANDARD("[%i] BREAK (break instr.) EXC: ", cnt_test);
613 59 zero_gravi 
  cnt_test++;
614 
 
615 
  asm volatile("EBREAK");
616 
 
617 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_BREAKPOINT) {
618 
    test_ok();
619 
  }
620 
  else {
621 
    test_fail();
622 
  }
623 
 
624 
 
625 
  // ----------------------------------------------------------
626 
  // Unaligned load address
627 
  // ----------------------------------------------------------
628 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
629 61 zero_gravi 
  PRINT_STANDARD("[%i] L_ALIGN (load addr alignment) EXC: ", cnt_test);
630 59 zero_gravi 
  cnt_test++;
631 
 
632 
  // load from unaligned address
633 64 zero_gravi 
  neorv32_cpu_load_unsigned_word(ADDR_UNALIGNED_1);
634 59 zero_gravi 
 
635 66 zero_gravi 
  if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_L_MISALIGNED) &&
636 
      (neorv32_cpu_csr_read(CSR_MTVAL) == ADDR_UNALIGNED_1)) {
637 59 zero_gravi 
    test_ok();
638 
  }
639 
  else {
640 
    test_fail();
641 
  }
642 
 
643 
 
644 
  // ----------------------------------------------------------
645 
  // Load access fault
646 
  // ----------------------------------------------------------
647 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
648 61 zero_gravi 
  PRINT_STANDARD("[%i] L_ACC (load bus access) EXC: ", cnt_test);
649 59 zero_gravi 
  cnt_test++;
650 
 
651 
  // load from unreachable aligned address
652 61 zero_gravi 
  neorv32_cpu_load_unsigned_word(ADDR_UNREACHABLE);
653 59 zero_gravi 
 
654 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_L_ACCESS) {
655 
    test_ok();
656 
  }
657 
  else {
658 
    test_fail();
659 
  }
660 
 
661 
 
662 
  // ----------------------------------------------------------
663 
  // Unaligned store address
664 
  // ----------------------------------------------------------
665 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
666 61 zero_gravi 
  PRINT_STANDARD("[%i] S_ALIGN (store addr alignment) EXC: ", cnt_test);
667 59 zero_gravi 
  cnt_test++;
668 
 
669 
  // store to unaligned address
670 64 zero_gravi 
  neorv32_cpu_store_unsigned_word(ADDR_UNALIGNED_2, 0);
671 59 zero_gravi 
 
672 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_MISALIGNED) {
673 
    test_ok();
674 
  }
675 
  else {
676 
    test_fail();
677 
  }
678 
 
679 
 
680 
  // ----------------------------------------------------------
681 
  // Store access fault
682 
  // ----------------------------------------------------------
683 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
684 61 zero_gravi 
  PRINT_STANDARD("[%i] S_ACC (store bus access) EXC: ", cnt_test);
685 59 zero_gravi 
  cnt_test++;
686 
 
687 
  // store to unreachable aligned address
688 
  neorv32_cpu_store_unsigned_word(ADDR_UNREACHABLE, 0);
689 
 
690 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) {
691 
    test_ok();
692 
  }
693 
  else {
694 
    test_fail();
695 
  }
696 
 
697 
 
698 
  // ----------------------------------------------------------
699 
  // Environment call from M-mode
700 
  // ----------------------------------------------------------
701 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
702 61 zero_gravi 
  PRINT_STANDARD("[%i] ENVCALL (ecall instr.) from M-mode EXC: ", cnt_test);
703 59 zero_gravi 
  cnt_test++;
704 
 
705 
  asm volatile("ECALL");
706 
 
707 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MENV_CALL) {
708 
    test_ok();
709 
  }
710 
  else {
711 
    test_fail();
712 
  }
713 
 
714 
 
715 
  // ----------------------------------------------------------
716 
  // Environment call from U-mode
717 
  // ----------------------------------------------------------
718 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
719 61 zero_gravi 
  PRINT_STANDARD("[%i] ENVCALL (ecall instr.) from U-mode EXC: ", cnt_test);
720 59 zero_gravi 
 
721 64 zero_gravi 
  cnt_test++;
722 59 zero_gravi 
 
723 64 zero_gravi 
  // switch to user mode (hart will be back in MACHINE mode when trap handler returns)
724 
  neorv32_cpu_goto_user_mode();
725 
  {
726 
    asm volatile("ECALL");
727 
  }
728 59 zero_gravi 
 
729 64 zero_gravi 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_UENV_CALL) {
730 
    test_ok();
731 59 zero_gravi 
  }
732 
  else {
733 64 zero_gravi 
    test_fail();
734 59 zero_gravi 
  }
735 
 
736 
 
737 
  // ----------------------------------------------------------
738 
  // Machine timer interrupt (MTIME)
739 
  // ----------------------------------------------------------
740 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
741 65 zero_gravi 
  PRINT_STANDARD("[%i] MTI (MTIME): ", cnt_test);
742 59 zero_gravi 
 
743 61 zero_gravi 
  cnt_test++;
744 59 zero_gravi 
 
745 64 zero_gravi 
  // configure MTIME IRQ (and check overflow from low word to high word)
746 61 zero_gravi 
  neorv32_mtime_set_timecmp(-1);
747 
  neorv32_mtime_set_time(0);
748 59 zero_gravi 
 
749 64 zero_gravi 
  // enable interrupt
750 61 zero_gravi 
  neorv32_mtime_set_timecmp(0x0000000100000000ULL);
751 
  neorv32_mtime_set_time(   0x00000000FFFFFFFEULL);
752 64 zero_gravi 
  neorv32_cpu_irq_enable(CSR_MIE_MTIE);
753 59 zero_gravi 
 
754 61 zero_gravi 
  // wait some time for the IRQ to trigger and arrive the CPU
755 
  asm volatile("nop");
756 
  asm volatile("nop");
757 59 zero_gravi 
 
758 64 zero_gravi 
  // disable interrupt
759 
  neorv32_cpu_irq_disable(CSR_MIE_MTIE);
760 
 
761 61 zero_gravi 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MTI) {
762 
    test_ok();
763 59 zero_gravi 
  }
764 
  else {
765 61 zero_gravi 
    test_fail();
766 59 zero_gravi 
  }
767 
 
768 61 zero_gravi 
  // no more mtime interrupts
769 
  neorv32_mtime_set_timecmp(-1);
770 59 zero_gravi 
 
771 61 zero_gravi 
 
772 59 zero_gravi 
  // ----------------------------------------------------------
773 
  // Machine software interrupt (MSI) via testbench
774 
  // ----------------------------------------------------------
775 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
776 65 zero_gravi 
  PRINT_STANDARD("[%i] MSI (testbench): ", cnt_test);
777 59 zero_gravi 
 
778 61 zero_gravi 
  cnt_test++;
779 59 zero_gravi 
 
780 64 zero_gravi 
  // enable interrupt
781 
  neorv32_cpu_irq_enable(CSR_MIE_MSIE);
782 
 
783 61 zero_gravi 
  // trigger IRQ
784 
  sim_irq_trigger(1 << CSR_MIE_MSIE);
785 59 zero_gravi 
 
786 61 zero_gravi 
  // wait some time for the IRQ to arrive the CPU
787 
  asm volatile("nop");
788 
  asm volatile("nop");
789 59 zero_gravi 
 
790 64 zero_gravi 
  // disable interrupt
791 
  neorv32_cpu_irq_disable(CSR_MIE_MSIE);
792 
 
793 61 zero_gravi 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MSI) {
794 
    test_ok();
795 59 zero_gravi 
  }
796 
  else {
797 61 zero_gravi 
    test_fail();
798 59 zero_gravi 
  }
799 
 
800 
 
801 
  // ----------------------------------------------------------
802 
  // Machine external interrupt (MEI) via testbench
803 
  // ----------------------------------------------------------
804 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
805 65 zero_gravi 
  PRINT_STANDARD("[%i] MEI (testbench): ", cnt_test);
806 59 zero_gravi 
 
807 61 zero_gravi 
  cnt_test++;
808 59 zero_gravi 
 
809 64 zero_gravi 
  // enable interrupt
810 
  neorv32_cpu_irq_enable(CSR_MIE_MEIE);
811 
 
812 61 zero_gravi 
  // trigger IRQ
813 
  sim_irq_trigger(1 << CSR_MIE_MEIE);
814 59 zero_gravi 
 
815 61 zero_gravi 
  // wait some time for the IRQ to arrive the CPU
816 
  asm volatile("nop");
817 
  asm volatile("nop");
818 59 zero_gravi 
 
819 64 zero_gravi 
  // enable interrupt
820 
  neorv32_cpu_irq_disable(CSR_MIE_MEIE);
821 
 
822 61 zero_gravi 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MEI) {
823 
    test_ok();
824 59 zero_gravi 
  }
825 
  else {
826 61 zero_gravi 
    test_fail();
827 59 zero_gravi 
  }
828 
 
829 
 
830 
  // ----------------------------------------------------------
831 64 zero_gravi 
  // Permanent IRQ (make sure interrupted program advances)
832 59 zero_gravi 
  // ----------------------------------------------------------
833 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
834 64 zero_gravi 
  PRINT_STANDARD("[%i] Permanent IRQ (MTIME): ", cnt_test);
835 59 zero_gravi 
 
836 61 zero_gravi 
  cnt_test++;
837 59 zero_gravi 
 
838 64 zero_gravi 
  // fire MTIME IRQ
839 
  neorv32_cpu_irq_enable(CSR_MIE_MTIE);
840 
  neorv32_mtime_set_time(1); // prepare overflow
841 
  neorv32_mtime_set_timecmp(0); // IRQ on overflow
842 59 zero_gravi 
 
843 64 zero_gravi 
  register int test_cnt = 0;
844 
  while(test_cnt < 2) {
845 
    test_cnt++;
846 
  }
847 
 
848 
  // end MTIME IRQ
849 
  neorv32_cpu_irq_disable(CSR_MIE_MTIE);
850 
  neorv32_mtime_set_timecmp(-1);
851 
 
852 
  if (test_cnt == 2) {
853 
    test_ok();
854 
  }
855 
  else {
856 
    test_fail();
857 
  }
858 
 
859 
 
860 
  // ----------------------------------------------------------
861 
  // Test pending interrupt
862 
  // ----------------------------------------------------------
863 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
864 65 zero_gravi 
  PRINT_STANDARD("[%i] Pending IRQ (MTIME): ", cnt_test);
865 64 zero_gravi 
 
866 
  cnt_test++;
867 
 
868 
  // enable interrupt
869 
  neorv32_cpu_irq_enable(CSR_MIE_MTIE);
870 
 
871 
  // disable global interrupts
872 
  neorv32_cpu_dint();
873 
 
874 
  // fire MTIME IRQ
875 
  neorv32_mtime_set_time(1); // prepare overflow
876 
  neorv32_mtime_set_timecmp(0); // IRQ on overflow
877 
 
878 61 zero_gravi 
  // wait some time for the IRQ to arrive the CPU
879 
  asm volatile("nop");
880 
  asm volatile("nop");
881 59 zero_gravi 
 
882 64 zero_gravi 
  int was_pending = 0;
883 
  if (neorv32_cpu_csr_read(CSR_MIP) & (1 << CSR_MIP_MTIP)) { // should be pending now
884 
    was_pending = 1;
885 
  }
886 
 
887 
  // clear pending MTI
888 
  neorv32_mtime_set_timecmp(-1);
889 
 
890 
  int is_pending = 0;
891 
  if (neorv32_cpu_csr_read(CSR_MIP) & (1 << CSR_MIP_MTIP)) { // should NOT be pending anymore
892 
    is_pending = 1;
893 
  }
894 
 
895 
  neorv32_cpu_irq_disable(CSR_MIE_MTIE);
896 
 
897 
  if ((was_pending == 1) && (is_pending == 0)) {
898 61 zero_gravi 
    test_ok();
899 59 zero_gravi 
  }
900 
  else {
901 61 zero_gravi 
    test_fail();
902 59 zero_gravi 
  }
903 
 
904 64 zero_gravi 
  // re-enable global interrupts
905 
  neorv32_cpu_eint();
906 59 zero_gravi 
 
907 64 zero_gravi 
 
908 59 zero_gravi 
  // ----------------------------------------------------------
909 
  // Fast interrupt channel 0 (WDT)
910 
  // ----------------------------------------------------------
911 61 zero_gravi 
  if (neorv32_wdt_available()) {
912 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
913 65 zero_gravi 
    PRINT_STANDARD("[%i] FIRQ0 (WDT): ", cnt_test);
914 59 zero_gravi 
 
915 
    cnt_test++;
916 
 
917 
    // enable fast interrupt
918 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ0E);
919 
 
920 
    // configure WDT
921 
    neorv32_wdt_setup(CLK_PRSC_4096, 0, 1); // highest clock prescaler, trigger IRQ on timeout, lock access
922 64 zero_gravi 
    NEORV32_WDT.CTRL = 0; // try to deactivate WDT (should fail as access is loced)
923 59 zero_gravi 
    neorv32_wdt_force(); // force watchdog into action
924 
 
925 
    // wait some time for the IRQ to arrive the CPU
926 
    asm volatile("nop");
927 65 zero_gravi 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ0E);
928 59 zero_gravi 
 
929 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_0) {
930 
      test_ok();
931 
    }
932 
    else {
933 
      test_fail();
934 
    }
935 
 
936 
    // no more WDT interrupts
937 
    neorv32_wdt_disable();
938 
  }
939 
 
940 
 
941 
  // ----------------------------------------------------------
942 
  // Fast interrupt channel 1 (CFS)
943 
  // ----------------------------------------------------------
944 65 zero_gravi 
  PRINT_STANDARD("[%i] FIRQ1 (CFS): ", cnt_test);
945 64 zero_gravi 
  PRINT_STANDARD("skipped \n");
946 59 zero_gravi 
 
947 
 
948 
  // ----------------------------------------------------------
949 
  // Fast interrupt channel 2 (UART0.RX)
950 
  // ----------------------------------------------------------
951 61 zero_gravi 
  if (neorv32_uart1_available()) {
952 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
953 65 zero_gravi 
    PRINT_STANDARD("[%i] FIRQ2 (UART0.RX): ", cnt_test);
954 59 zero_gravi 
 
955 
    cnt_test++;
956 
 
957 
    // wait for UART0 to finish transmitting
958 61 zero_gravi 
    while(neorv32_uart0_tx_busy());
959 59 zero_gravi 
 
960 
    // backup current UART0 configuration
961 64 zero_gravi 
    tmp_a = NEORV32_UART0.CTRL;
962 59 zero_gravi 
 
963 61 zero_gravi 
    // make sure UART is enabled
964 64 zero_gravi 
    NEORV32_UART0.CTRL |= (1 << UART_CTRL_EN);
965 61 zero_gravi 
    // make sure sim mode is disabled
966 64 zero_gravi 
    NEORV32_UART0.CTRL &= ~(1 << UART_CTRL_SIM_MODE);
967 59 zero_gravi 
 
968 
    // trigger UART0 RX IRQ
969 61 zero_gravi 
    neorv32_uart0_putc(0);
970 59 zero_gravi 
    // wait for UART0 to finish transmitting
971 61 zero_gravi 
    while(neorv32_uart0_tx_busy());
972 59 zero_gravi 
 
973 65 zero_gravi 
    // enable fast interrupt
974 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ2E);
975 
 
976 59 zero_gravi 
    // wait some time for the IRQ to arrive the CPU
977 
    asm volatile("nop");
978 65 zero_gravi 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ2E);
979 59 zero_gravi 
 
980 61 zero_gravi 
    // restore original configuration
981 64 zero_gravi 
    NEORV32_UART0.CTRL = tmp_a;
982 59 zero_gravi 
 
983 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_2) {
984 
      test_ok();
985 
    }
986 
    else {
987 
      test_fail();
988 
    }
989 
  }
990 
 
991 
 
992 
  // ----------------------------------------------------------
993 
  // Fast interrupt channel 3 (UART0.TX)
994 
  // ----------------------------------------------------------
995 61 zero_gravi 
  if (neorv32_uart0_available()) {
996 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
997 65 zero_gravi 
    PRINT_STANDARD("[%i] FIRQ3 (UART0.TX): ", cnt_test);
998 59 zero_gravi 
 
999 61 zero_gravi 
    cnt_test++;
1000 59 zero_gravi 
 
1001 61 zero_gravi 
    // wait for UART0 to finish transmitting
1002 
    while(neorv32_uart0_tx_busy());
1003 59 zero_gravi 
 
1004 61 zero_gravi 
    // backup current UART0 configuration
1005 64 zero_gravi 
    tmp_a = NEORV32_UART0.CTRL;
1006 59 zero_gravi 
 
1007 61 zero_gravi 
    // make sure UART is enabled
1008 64 zero_gravi 
    NEORV32_UART0.CTRL |= (1 << UART_CTRL_EN);
1009 61 zero_gravi 
    // make sure sim mode is disabled
1010 64 zero_gravi 
    NEORV32_UART0.CTRL &= ~(1 << UART_CTRL_SIM_MODE);
1011 59 zero_gravi 
 
1012 61 zero_gravi 
    // trigger UART0 TX IRQ
1013 
    neorv32_uart0_putc(0);
1014 65 zero_gravi 
    // UART0 TX interrupt enable
1015 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E);
1016 61 zero_gravi 
    // wait for UART to finish transmitting
1017 
    while(neorv32_uart0_tx_busy());
1018 59 zero_gravi 
 
1019 61 zero_gravi 
    // wait some time for the IRQ to arrive the CPU
1020 
    asm volatile("nop");
1021 65 zero_gravi 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ3E);
1022 59 zero_gravi 
 
1023 61 zero_gravi 
    // restore original configuration
1024 64 zero_gravi 
    NEORV32_UART0.CTRL = tmp_a;
1025 59 zero_gravi 
 
1026 61 zero_gravi 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) {
1027 
      test_ok();
1028 
    }
1029 
    else {
1030 
      test_fail();
1031 
    }
1032 59 zero_gravi 
  }
1033 
 
1034 
 
1035 
  // ----------------------------------------------------------
1036 
  // Fast interrupt channel 4 (UART1.RX)
1037 
  // ----------------------------------------------------------
1038 61 zero_gravi 
  if (neorv32_uart1_available()) {
1039 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1040 65 zero_gravi 
    PRINT_STANDARD("[%i] FIRQ4 (UART1.RX): ", cnt_test);
1041 59 zero_gravi 
 
1042 
    cnt_test++;
1043 
 
1044 61 zero_gravi 
    // backup current UART1 configuration
1045 64 zero_gravi 
    tmp_a = NEORV32_UART1.CTRL;
1046 59 zero_gravi 
 
1047 61 zero_gravi 
    // make sure UART is enabled
1048 64 zero_gravi 
    NEORV32_UART1.CTRL |= (1 << UART_CTRL_EN);
1049 61 zero_gravi 
    // make sure sim mode is disabled
1050 64 zero_gravi 
    NEORV32_UART1.CTRL &= ~(1 << UART_CTRL_SIM_MODE);
1051 61 zero_gravi 
 
1052 59 zero_gravi 
    // trigger UART1 RX IRQ
1053 61 zero_gravi 
    neorv32_uart1_putc(0);
1054 59 zero_gravi 
    // wait for UART1 to finish transmitting
1055 
    while(neorv32_uart1_tx_busy());
1056 65 zero_gravi 
    // UART1 RX interrupt enable
1057 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ4E);
1058 59 zero_gravi 
 
1059 
    // wait some time for the IRQ to arrive the CPU
1060 
    asm volatile("nop");
1061 65 zero_gravi 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ4E);
1062 59 zero_gravi 
 
1063 61 zero_gravi 
    // restore original configuration
1064 64 zero_gravi 
    NEORV32_UART1.CTRL = tmp_a;
1065 59 zero_gravi 
 
1066 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_4) {
1067 
      test_ok();
1068 
    }
1069 
    else {
1070 
      test_fail();
1071 
    }
1072 
  }
1073 
 
1074 
 
1075 
  // ----------------------------------------------------------
1076 
  // Fast interrupt channel 5 (UART1.TX)
1077 
  // ----------------------------------------------------------
1078 61 zero_gravi 
  if (neorv32_uart1_available()) {
1079 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1080 65 zero_gravi 
    PRINT_STANDARD("[%i] FIRQ5 (UART1.TX): ", cnt_test);
1081 59 zero_gravi 
 
1082 
    cnt_test++;
1083 
 
1084 61 zero_gravi 
    // backup current UART1 configuration
1085 64 zero_gravi 
    tmp_a = NEORV32_UART1.CTRL;
1086 59 zero_gravi 
 
1087 61 zero_gravi 
    // make sure UART is enabled
1088 64 zero_gravi 
    NEORV32_UART1.CTRL |= (1 << UART_CTRL_EN);
1089 61 zero_gravi 
    // make sure sim mode is disabled
1090 64 zero_gravi 
    NEORV32_UART1.CTRL &= ~(1 << UART_CTRL_SIM_MODE);
1091 61 zero_gravi 
 
1092 59 zero_gravi 
    // trigger UART1 TX IRQ
1093 61 zero_gravi 
    neorv32_uart1_putc(0);
1094 65 zero_gravi 
    // UART1 RX interrupt enable
1095 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ5E);
1096 59 zero_gravi 
    // wait for UART1 to finish transmitting
1097 
    while(neorv32_uart1_tx_busy());
1098 
 
1099 
    // wait some time for the IRQ to arrive the CPU
1100 
    asm volatile("nop");
1101 65 zero_gravi 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ5E);
1102 59 zero_gravi 
 
1103 61 zero_gravi 
    // restore original configuration
1104 64 zero_gravi 
    NEORV32_UART1.CTRL = tmp_a;
1105 59 zero_gravi 
 
1106 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_5) {
1107 
      test_ok();
1108 
    }
1109 
    else {
1110 
      test_fail();
1111 
    }
1112 
  }
1113 
 
1114 
 
1115 
  // ----------------------------------------------------------
1116 
  // Fast interrupt channel 6 (SPI)
1117 
  // ----------------------------------------------------------
1118 61 zero_gravi 
  if (neorv32_spi_available()) {
1119 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1120 65 zero_gravi 
    PRINT_STANDARD("[%i] FIRQ6 (SPI): ", cnt_test);
1121 59 zero_gravi 
 
1122 
    cnt_test++;
1123 
 
1124 
    // configure SPI
1125 65 zero_gravi 
    neorv32_spi_setup(CLK_PRSC_2, 0, 0, 0);
1126 59 zero_gravi 
 
1127 
    // trigger SPI IRQ
1128 
    neorv32_spi_trans(0);
1129 65 zero_gravi 
    // enable fast interrupt
1130 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E);
1131 59 zero_gravi 
    while(neorv32_spi_busy()); // wait for current transfer to finish
1132 
 
1133 
    // wait some time for the IRQ to arrive the CPU
1134 
    asm volatile("nop");
1135 65 zero_gravi 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ6E);
1136 59 zero_gravi 
 
1137 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_6) {
1138 
      test_ok();
1139 
    }
1140 
    else {
1141 
      test_fail();
1142 
    }
1143 
 
1144 
    // disable SPI
1145 
    neorv32_spi_disable();
1146 
  }
1147 
 
1148 
 
1149 
  // ----------------------------------------------------------
1150 
  // Fast interrupt channel 7 (TWI)
1151 
  // ----------------------------------------------------------
1152 61 zero_gravi 
  if (neorv32_twi_available()) {
1153 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1154 65 zero_gravi 
    PRINT_STANDARD("[%i] FIRQ7 (TWI): ", cnt_test);
1155 59 zero_gravi 
 
1156 
    cnt_test++;
1157 
 
1158 
    // configure TWI, fastest clock, no peripheral clock stretching
1159 
    neorv32_twi_setup(CLK_PRSC_2, 0);
1160 
 
1161 
    // trigger TWI IRQ
1162 
    neorv32_twi_generate_start();
1163 
    neorv32_twi_trans(0);
1164 
    neorv32_twi_generate_stop();
1165 65 zero_gravi 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E);
1166 59 zero_gravi 
 
1167 
    // wait some time for the IRQ to arrive the CPU
1168 
    asm volatile("nop");
1169 65 zero_gravi 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ7E);
1170 59 zero_gravi 
 
1171 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_7) {
1172 
      test_ok();
1173 
    }
1174 
    else {
1175 
      test_fail();
1176 
    }
1177 
 
1178 
    // disable TWI
1179 
    neorv32_twi_disable();
1180 
  }
1181 
 
1182 
 
1183 
  // ----------------------------------------------------------
1184 61 zero_gravi 
  // Fast interrupt channel 8 (XIRQ)
1185 59 zero_gravi 
  // ----------------------------------------------------------
1186 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1187 65 zero_gravi 
  PRINT_STANDARD("[%i] FIRQ8 (XIRQ): ", cnt_test);
1188 61 zero_gravi 
  if (neorv32_xirq_available()) {
1189 59 zero_gravi 
 
1190 61 zero_gravi 
    cnt_test++;
1191 59 zero_gravi 
 
1192 61 zero_gravi 
    int xirq_err_cnt = 0;
1193 
    xirq_trap_handler_ack = 0;
1194 59 zero_gravi 
 
1195 61 zero_gravi 
    xirq_err_cnt += neorv32_xirq_setup(); // initialize XIRQ
1196 
    xirq_err_cnt += neorv32_xirq_install(0, xirq_trap_handler0); // install XIRQ IRQ handler channel 0
1197 
    xirq_err_cnt += neorv32_xirq_install(1, xirq_trap_handler1); // install XIRQ IRQ handler channel 1
1198 59 zero_gravi 
 
1199 64 zero_gravi 
    // enable XIRQ FIRQ
1200 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ8E);
1201 59 zero_gravi 
 
1202 61 zero_gravi 
    // trigger XIRQ channel 1 and 0
1203 
    neorv32_gpio_port_set(3);
1204 59 zero_gravi 
 
1205 61 zero_gravi 
    // wait for IRQs to arrive CPU
1206 
    asm volatile("nop");
1207 
    asm volatile("nop");
1208 65 zero_gravi 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ8E);
1209 59 zero_gravi 
 
1210 61 zero_gravi 
    if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_8) && // FIRQ8 IRQ
1211 
        (xirq_err_cnt == 0) && // no errors during XIRQ configuration
1212 
        (xirq_trap_handler_ack == 4)) { // XIRQ channel handler 0 executed before handler 1
1213 
      test_ok();
1214 59 zero_gravi 
    }
1215 
    else {
1216 61 zero_gravi 
      test_fail();
1217 59 zero_gravi 
    }
1218 61 zero_gravi 
 
1219 64 zero_gravi 
    NEORV32_XIRQ.IER = 0;
1220 
    NEORV32_XIRQ.IPR = -1;
1221 59 zero_gravi 
  }
1222 
 
1223 
 
1224 
  // ----------------------------------------------------------
1225 61 zero_gravi 
  // Fast interrupt channel 9 (NEOLED)
1226 59 zero_gravi 
  // ----------------------------------------------------------
1227 61 zero_gravi 
  PRINT_STANDARD("[%i] FIRQ9 (NEOLED): skipped\n", cnt_test);
1228 59 zero_gravi 
 
1229 
 
1230 
  // ----------------------------------------------------------
1231 61 zero_gravi 
  // Fast interrupt channel 10 & 11 (SLINK)
1232 59 zero_gravi 
  // ----------------------------------------------------------
1233 61 zero_gravi 
  if (neorv32_slink_available()) {
1234 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1235 
    PRINT_STANDARD("[%i] FIRQ10 & 11 (SLINK): ", cnt_test);
1236 59 zero_gravi 
 
1237 
    cnt_test++;
1238 
 
1239 61 zero_gravi 
    // enable SLINK
1240 
    neorv32_slink_enable();
1241 
 
1242 65 zero_gravi 
    // configure SLINK IRQs
1243 
    neorv32_slink_tx_irq_config(0, SLINK_IRQ_ENABLE, SLINK_IRQ_TX_NOT_FULL);
1244 
    neorv32_slink_rx_irq_config(0, SLINK_IRQ_ENABLE, SLINK_IRQ_RX_NOT_EMPTY);
1245 
 
1246 61 zero_gravi 
    // enable SLINK FIRQs
1247 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ10E);
1248 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ11E);
1249 
 
1250 
    tmp_a = 0; // error counter
1251 
 
1252 65 zero_gravi 
    // wait some time for the IRQ to arrive the CPU
1253 
    asm volatile("nop");
1254 
 
1255 
    // check if TX FIFO fires IRQ
1256 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_FIRQ_11) {
1257 
      tmp_a += 1;
1258 
    }
1259 
    neorv32_slink_tx_irq_config(0, SLINK_IRQ_DISABLE, SLINK_IRQ_TX_NOT_FULL);
1260 
 
1261 61 zero_gravi 
    // send single data word via link 0
1262 
    if (neorv32_slink_tx0_nonblocking(0xA1B2C3D4)) {
1263 65 zero_gravi 
      tmp_a += 2; // sending failed
1264 59 zero_gravi 
    }
1265 
 
1266 65 zero_gravi 
    // wait some time for the IRQ to arrive the CPU
1267 
    asm volatile("nop");
1268 
 
1269 
    // check if RX FIFO fires IRQ
1270 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_FIRQ_10) {
1271 
      tmp_a += 4;
1272 
    }
1273 
    neorv32_slink_rx_irq_config(0, SLINK_IRQ_DISABLE, SLINK_IRQ_RX_NOT_EMPTY);
1274 
 
1275 61 zero_gravi 
    // get single data word from link 0
1276 
    uint32_t slink_rx_data;
1277 
    if (neorv32_slink_rx0_nonblocking(&slink_rx_data)) {
1278 65 zero_gravi 
      tmp_a += 8; // receiving failed
1279 61 zero_gravi 
    }
1280 59 zero_gravi 
 
1281 65 zero_gravi 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ10E);
1282 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ11E);
1283 59 zero_gravi 
 
1284 65 zero_gravi 
    if ((tmp_a == 0) && // local error counter = 0
1285 61 zero_gravi 
        (slink_rx_data == 0xA1B2C3D4)) { // correct data read-back
1286 
      test_ok();
1287 59 zero_gravi 
    }
1288 61 zero_gravi 
    else {
1289 
      test_fail();
1290 
    }
1291 59 zero_gravi 
 
1292 61 zero_gravi 
    // shutdown SLINK
1293 
    neorv32_slink_disable();
1294 59 zero_gravi 
  }
1295 
 
1296 
 
1297 67 zero_gravi 
  // ----------------------------------------------------------
1298 
  // Fast interrupt channel 12 (GPTMR)
1299 
  // ----------------------------------------------------------
1300 
  if (neorv32_slink_available()) {
1301 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1302 
    PRINT_STANDARD("[%i] FIRQ12 (GPTMR): ", cnt_test);
1303 
 
1304 
    cnt_test++;
1305 
 
1306 
    // enable GPTMR FIRQ
1307 
    neorv32_cpu_irq_enable(CSR_MIE_FIRQ12E);
1308 
 
1309 
    // configure timer IRQ for one-shot mode after 2*4 clock cycles
1310 
    neorv32_gptmr_setup(CLK_PRSC_2, 0, 4);
1311 
 
1312 
    // wait some time for the IRQ to arrive the CPU
1313 
    asm volatile("nop");
1314 
    asm volatile("nop");
1315 
 
1316 
    // disable GPTMR interrupt
1317 
    neorv32_cpu_irq_disable(CSR_MIE_FIRQ12E);
1318 
 
1319 
    // check if RX FIFO fires IRQ
1320 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_12) {
1321 
      test_ok();
1322 
    }
1323 
    else {
1324 
      test_fail();
1325 
    }
1326 
 
1327 
    // disable GPTMR
1328 
    neorv32_gptmr_disable();
1329 
  }
1330 
 
1331 
 
1332 61 zero_gravi 
//// ----------------------------------------------------------
1333 67 zero_gravi 
//// Fast interrupt channel 13..15 (reserved)
1334 61 zero_gravi 
//// ----------------------------------------------------------
1335 67 zero_gravi 
//PRINT_STANDARD("[%i] FIRQ13..15: ", cnt_test);
1336 61 zero_gravi 
//PRINT_STANDARD("skipped (n.a.)\n");
1337 59 zero_gravi 
 
1338 61 zero_gravi 
 
1339 59 zero_gravi 
  // ----------------------------------------------------------
1340 
  // Test WFI ("sleep") instructions, wakeup via MTIME
1341 
  // ----------------------------------------------------------
1342 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1343 65 zero_gravi 
  PRINT_STANDARD("[%i] WFI (sleep instruction, wake-up via MTIME): ", cnt_test);
1344 59 zero_gravi 
 
1345 61 zero_gravi 
  cnt_test++;
1346 59 zero_gravi 
 
1347 64 zero_gravi 
  // program wake-up timer
1348 
  neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + 500);
1349 
 
1350 65 zero_gravi 
  // enable mtime interrupt
1351 64 zero_gravi 
  neorv32_cpu_irq_enable(CSR_MIE_MTIE);
1352 
 
1353 65 zero_gravi 
  // put CPU into sleep mode
1354 
  asm volatile ("wfi");
1355 62 zero_gravi 
 
1356 64 zero_gravi 
  // no more mtime interrupts
1357 
  neorv32_cpu_irq_disable(CSR_MIE_MTIE);
1358 
  neorv32_mtime_set_timecmp(-1);
1359 
 
1360 61 zero_gravi 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_MTI) {
1361 
    test_fail();
1362 59 zero_gravi 
  }
1363 
  else {
1364 61 zero_gravi 
    test_ok();
1365 59 zero_gravi 
  }
1366 
 
1367 
 
1368 
  // ----------------------------------------------------------
1369 
  // Test invalid CSR access in user mode
1370 
  // ----------------------------------------------------------
1371 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1372 61 zero_gravi 
  PRINT_STANDARD("[%i] Invalid CSR access (mstatus) from user mode: ", cnt_test);
1373 59 zero_gravi 
 
1374 64 zero_gravi 
  cnt_test++;
1375 59 zero_gravi 
 
1376 64 zero_gravi 
  // switch to user mode (hart will be back in MACHINE mode when trap handler returns)
1377 
  neorv32_cpu_goto_user_mode();
1378 
  {
1379 
    // access to misa not allowed for user-level programs
1380 
    tmp_a = neorv32_cpu_csr_read(CSR_MISA);
1381 
  }
1382 59 zero_gravi 
 
1383 64 zero_gravi 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
1384 
    test_ok();
1385 59 zero_gravi 
  }
1386 
  else {
1387 64 zero_gravi 
    test_fail();
1388 59 zero_gravi 
  }
1389 
 
1390 
 
1391 
  // ----------------------------------------------------------
1392 
  // Test RTE debug trap handler
1393 
  // ----------------------------------------------------------
1394 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1395 61 zero_gravi 
  PRINT_STANDARD("[%i] RTE debug trap handler: ", cnt_test);
1396 59 zero_gravi 
 
1397 
  cnt_test++;
1398 
 
1399 
  // uninstall custom handler and use default RTE debug handler
1400 
  neorv32_rte_exception_uninstall(RTE_TRAP_I_ILLEGAL);
1401 
 
1402 
  // trigger illegal instruction exception
1403 
  neorv32_cpu_csr_read(0xfff); // CSR not available
1404 
 
1405 61 zero_gravi 
  PRINT_STANDARD(" ");
1406 59 zero_gravi 
  if (neorv32_cpu_csr_read(CSR_MCAUSE) != 0) {
1407 
    test_ok();
1408 
  }
1409 
  else {
1410 
    test_fail();
1411 61 zero_gravi 
    PRINT_STANDARD("answer: 0x%x", neorv32_cpu_csr_read(CSR_MCAUSE));
1412 59 zero_gravi 
  }
1413 
 
1414 
  // restore original handler
1415 
  neorv32_rte_exception_install(RTE_TRAP_I_ILLEGAL, global_trap_handler);
1416 
 
1417 
 
1418 
  // ----------------------------------------------------------
1419 
  // Test physical memory protection
1420 
  // ----------------------------------------------------------
1421 61 zero_gravi 
  PRINT_STANDARD("[%i] PMP - Physical memory protection: ", cnt_test);
1422 59 zero_gravi 
 
1423 
  // check if PMP is implemented
1424 
  if (neorv32_cpu_pmp_get_num_regions() != 0)  {
1425 
 
1426 
    // Create PMP protected region
1427 
    // ---------------------------------------------
1428 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1429 
    cnt_test++;
1430 
 
1431 61 zero_gravi 
    // find out minimal region size (granularity)
1432 59 zero_gravi 
    tmp_b = neorv32_cpu_pmp_get_granularity();
1433 
 
1434 64 zero_gravi 
    tmp_a = NEORV32_SYSINFO.DSPACE_BASE; // base address of protected region
1435 61 zero_gravi 
    PRINT_STANDARD("Creating protected page (NAPOT, [!X,!W,!R], %u bytes) @ 0x%x: ", tmp_b, tmp_a);
1436 59 zero_gravi 
 
1437 
    // configure
1438 61 zero_gravi 
    int pmp_return = neorv32_cpu_pmp_configure_region(0, tmp_a, tmp_b, 0b00011000); // NAPOT, NO read permission, NO write permission, and NO execute permissions
1439 59 zero_gravi 
 
1440 
    if ((pmp_return == 0) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
1441 
      test_ok();
1442 
    }
1443 
    else {
1444 65 zero_gravi 
      if (neorv32_cpu_csr_read(CSR_PMPCFG0) & 0x80) {
1445 
      PRINT_CRITICAL("%c[1m<Entry LOCKED!> %c[0m\n", 27, 27);
1446 
      }
1447 59 zero_gravi 
      test_fail();
1448 
    }
1449 
 
1450 
 
1451 
    // ------ EXECUTE: should fail ------
1452 61 zero_gravi 
    PRINT_STANDARD("[%i] PMP: U-mode execute: ", cnt_test);
1453 59 zero_gravi 
    cnt_test++;
1454 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1455 
 
1456 
    // switch to user mode (hart will be back in MACHINE mode when trap handler returns)
1457 
    neorv32_cpu_goto_user_mode();
1458 
    {
1459 
      asm volatile ("jalr ra, %[input_i]" :  : [input_i] "r" (tmp_a)); // call address to execute -> should fail
1460 
    }
1461 
 
1462 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
1463 61 zero_gravi 
      // switch back to machine mode (if not already)
1464 59 zero_gravi 
      asm volatile ("ecall");
1465 
 
1466 
      test_fail();
1467 
    }
1468 
    else {
1469 61 zero_gravi 
      // switch back to machine mode (if not already)
1470 59 zero_gravi 
      asm volatile ("ecall");
1471 
 
1472 
      test_ok();
1473 
    }
1474 
 
1475 
 
1476 61 zero_gravi 
    // ------ LOAD: should fail ------
1477 
    PRINT_STANDARD("[%i] PMP: U-mode read: ", cnt_test);
1478 59 zero_gravi 
    cnt_test++;
1479 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1480 
 
1481 
    // switch to user mode (hart will be back in MACHINE mode when trap handler returns)
1482 
    neorv32_cpu_goto_user_mode();
1483 64 zero_gravi 
    tmp_b = 0;
1484 59 zero_gravi 
    {
1485 61 zero_gravi 
      tmp_b = neorv32_cpu_load_unsigned_word(tmp_a); // load access -> should fail
1486 59 zero_gravi 
    }
1487 
 
1488 61 zero_gravi 
    if (tmp_b != 0) {
1489 
      PRINT_CRITICAL("%c[1m<SECURITY FAILURE> %c[0m\n", 27, 27);
1490 
    }
1491 
 
1492 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_L_ACCESS) {
1493 
      // switch back to machine mode (if not already)
1494 59 zero_gravi 
      asm volatile ("ecall");
1495 
 
1496 
      test_ok();
1497 
    }
1498 
    else {
1499 61 zero_gravi 
      // switch back to machine mode (if not already)
1500 59 zero_gravi 
      asm volatile ("ecall");
1501 
 
1502 
      test_fail();
1503 
    }
1504 
 
1505 
 
1506 
    // ------ STORE: should fail ------
1507 61 zero_gravi 
    PRINT_STANDARD("[%i] PMP: U-mode write: ", cnt_test);
1508 59 zero_gravi 
    cnt_test++;
1509 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1510 
 
1511 
    // switch to user mode (hart will be back in MACHINE mode when trap handler returns)
1512 
    neorv32_cpu_goto_user_mode();
1513 
    {
1514 61 zero_gravi 
      neorv32_cpu_store_unsigned_word(tmp_a, 0); // store access -> should fail
1515 59 zero_gravi 
    }
1516 
 
1517 
    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) {
1518 61 zero_gravi 
      // switch back to machine mode (if not already)
1519 59 zero_gravi 
      asm volatile ("ecall");
1520 
 
1521 
      test_ok();
1522 
    }
1523 
    else {
1524 61 zero_gravi 
      // switch back to machine mode (if not already)
1525 59 zero_gravi 
      asm volatile ("ecall");
1526 
 
1527 
      test_fail();
1528 
    }
1529 
 
1530 
 
1531 
    // ------ Lock test - pmpcfg0.0 / pmpaddr0 ------
1532 61 zero_gravi 
    PRINT_STANDARD("[%i] PMP: Entry [mode=off] lock: ", cnt_test);
1533 59 zero_gravi 
    cnt_test++;
1534 
    neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1535 
 
1536 
    neorv32_cpu_csr_write(CSR_PMPCFG0, 0b10000001); // locked, but entry is deactivated (mode = off)
1537 
 
1538 
    // make sure a locked cfg cannot be written
1539 
    tmp_a = neorv32_cpu_csr_read(CSR_PMPCFG0);
1540 
    neorv32_cpu_csr_write(CSR_PMPCFG0, 0b00011001); // try to re-write CFG content
1541 
 
1542 
    tmp_b = neorv32_cpu_csr_read(CSR_PMPADDR0);
1543 
    neorv32_cpu_csr_write(CSR_PMPADDR0, 0xABABCDCD); // try to re-write ADDR content
1544 
 
1545 
    if ((tmp_a != neorv32_cpu_csr_read(CSR_PMPCFG0)) || (tmp_b != neorv32_cpu_csr_read(CSR_PMPADDR0)) || (neorv32_cpu_csr_read(CSR_MCAUSE) != 0)) {
1546 
      test_fail();
1547 
    }
1548 
    else {
1549 
      test_ok();
1550 
    }
1551 
 
1552 
  }
1553 
  else {
1554 61 zero_gravi 
    PRINT_STANDARD("skipped (n.a.)\n");
1555 59 zero_gravi 
  }
1556 
 
1557 
 
1558 
  // ----------------------------------------------------------
1559 
  // Test atomic LR/SC operation - should succeed
1560 
  // ----------------------------------------------------------
1561 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1562 61 zero_gravi 
  PRINT_STANDARD("[%i] Atomic access (LR+SC succeeding access): ", cnt_test);
1563 59 zero_gravi 
 
1564 
#ifdef __riscv_atomic
1565 
  // skip if A-mode is not implemented
1566 61 zero_gravi 
  if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A)) != 0) {
1567 59 zero_gravi 
 
1568 
    cnt_test++;
1569 
 
1570 
    neorv32_cpu_store_unsigned_word((uint32_t)&atomic_access_addr, 0x11223344);
1571 
 
1572 
    tmp_a = neorv32_cpu_load_reservate_word((uint32_t)&atomic_access_addr); // make reservation
1573 
    asm volatile ("nop");
1574 
    tmp_b = neorv32_cpu_store_conditional((uint32_t)&atomic_access_addr, 0x22446688);
1575 
 
1576 
    // atomic access
1577 
    if ((tmp_b == 0) && // status: success
1578 
        (tmp_a == 0x11223344) && // correct data read
1579 
        (neorv32_cpu_load_unsigned_word((uint32_t)&atomic_access_addr) == 0x22446688) && // correct data write
1580 
        (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { // no exception triggered
1581 
      test_ok();
1582 
    }
1583 
    else {
1584 
      test_fail();
1585 
    }
1586 
  }
1587 
  else {
1588 61 zero_gravi 
    PRINT_STANDARD("skipped (n.a.)\n");
1589 59 zero_gravi 
  }
1590 
#else
1591 61 zero_gravi 
  PRINT_STANDARD("skipped (n.a.)\n");
1592 59 zero_gravi 
#endif
1593 
 
1594 
 
1595 
  // ----------------------------------------------------------
1596 
  // Test atomic LR/SC operation - should fail
1597 
  // ----------------------------------------------------------
1598 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1599 61 zero_gravi 
  PRINT_STANDARD("[%i] Atomic access (LR+SC failing access 1): ", cnt_test);
1600 59 zero_gravi 
 
1601 
#ifdef __riscv_atomic
1602 
  // skip if A-mode is not implemented
1603 61 zero_gravi 
  if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A)) != 0) {
1604 59 zero_gravi 
 
1605 
    cnt_test++;
1606 
 
1607 
    neorv32_cpu_store_unsigned_word((uint32_t)&atomic_access_addr, 0xAABBCCDD);
1608 
 
1609 
    // atomic access
1610 
    tmp_a = neorv32_cpu_load_reservate_word((uint32_t)&atomic_access_addr); // make reservation
1611 65 zero_gravi 
    // neorv32_cpu_store_unsigned_word((uint32_t)&atomic_access_addr, 0xDEADDEAD); // destroy reservation
1612 
    neorv32_cpu_load_unsigned_word((uint32_t)&atomic_access_addr); // destroy reservation
1613 59 zero_gravi 
    tmp_b = neorv32_cpu_store_conditional((uint32_t)&atomic_access_addr, 0x22446688);
1614 
 
1615 
    if ((tmp_b != 0) && // status: fail
1616 
        (tmp_a == 0xAABBCCDD) && // correct data read
1617 65 zero_gravi 
        (neorv32_cpu_load_unsigned_word((uint32_t)&atomic_access_addr) == 0xAABBCCDD)) { // correct data write
1618 59 zero_gravi 
      test_ok();
1619 
    }
1620 
    else {
1621 
      test_fail();
1622 
    }
1623 
  }
1624 
  else {
1625 61 zero_gravi 
    PRINT_STANDARD("skipped (n.a.)\n");
1626 59 zero_gravi 
  }
1627 
#else
1628 61 zero_gravi 
  PRINT_STANDARD("skipped (n.a.)\n");
1629 59 zero_gravi 
#endif
1630 
 
1631 
 
1632 
  // ----------------------------------------------------------
1633 
  // Test atomic LR/SC operation - should fail
1634 
  // ----------------------------------------------------------
1635 
  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
1636 61 zero_gravi 
  PRINT_STANDARD("[%i] Atomic access (LR+SC failing access 2): ", cnt_test);
1637 59 zero_gravi 
 
1638 
#ifdef __riscv_atomic
1639 
  // skip if A-mode is not implemented
1640 61 zero_gravi 
  if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A)) != 0) {
1641 59 zero_gravi 
 
1642 
    cnt_test++;
1643 
 
1644 
    neorv32_cpu_store_unsigned_word((uint32_t)&atomic_access_addr, 0x12341234);
1645 
 
1646 
    // atomic access
1647 
    tmp_a = neorv32_cpu_load_reservate_word((uint32_t)&atomic_access_addr); // make reservation
1648 
    asm volatile ("ecall"); // destroy reservation via trap (simulate a context switch)
1649 
    tmp_b = neorv32_cpu_store_conditional((uint32_t)&atomic_access_addr, 0xDEADBEEF);
1650 
 
1651 
    if ((tmp_b != 0) && // status: fail
1652 
        (tmp_a == 0x12341234) && // correct data read
1653 
        (neorv32_cpu_load_unsigned_word((uint32_t)&atomic_access_addr) == 0x12341234)) { // correct data write
1654 
      test_ok();
1655 
    }
1656 
    else {
1657 
      test_fail();
1658 
    }
1659 
  }
1660 
  else {
1661 61 zero_gravi 
    PRINT_STANDARD("skipped (on real HW)\n");
1662 59 zero_gravi 
  }
1663 
#else
1664 61 zero_gravi 
  PRINT_STANDARD("skipped (n.a.)\n");
1665 59 zero_gravi 
#endif
1666 
 
1667 
 
1668 
  // ----------------------------------------------------------
1669 
  // HPM reports
1670 
  // ----------------------------------------------------------
1671 
  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
1672 61 zero_gravi 
  PRINT_STANDARD("\n\n-- HPM reports LOW (%u HPMs available) --\n", num_hpm_cnts_global);
1673 
  PRINT_STANDARD("#IR - Instr.:   %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = "HPM_0"
1674 
//PRINT_STANDARD("#TM - Time:     %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_TIME));    // = "HPM_1"
1675 
  PRINT_STANDARD("#CY - CLKs:     %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE));   // = "HPM_2"
1676 
  PRINT_STANDARD("#03 - Compr.:   %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3));
1677 
  PRINT_STANDARD("#04 - IF wait:  %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4));
1678 
  PRINT_STANDARD("#05 - II wait:  %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5));
1679 
  PRINT_STANDARD("#06 - ALU wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6));
1680 
  PRINT_STANDARD("#07 - Loads:    %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7));
1681 
  PRINT_STANDARD("#08 - Stores:   %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8));
1682 
  PRINT_STANDARD("#09 - MEM wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9));
1683 
  PRINT_STANDARD("#10 - Jumps:    %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10));
1684 
  PRINT_STANDARD("#11 - Branches: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
1685 
  PRINT_STANDARD("#12 -  Taken:   %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12));
1686 
  PRINT_STANDARD("#13 - Traps:    %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13));
1687 
  PRINT_STANDARD("#14 - Illegals: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14));
1688 59 zero_gravi 
 
1689 
 
1690 
  // ----------------------------------------------------------
1691 
  // Final test reports
1692 
  // ----------------------------------------------------------
1693 61 zero_gravi 
  PRINT_CRITICAL("\n\nTest results:\nPASS: %i/%i\nFAIL: %i/%i\n\n", cnt_ok, cnt_test, cnt_fail, cnt_test);
1694 59 zero_gravi 
 
1695 
  // final result
1696 
  if (cnt_fail == 0) {
1697 61 zero_gravi 
    PRINT_STANDARD("%c[1m[CPU TEST COMPLETED SUCCESSFULLY!]%c[0m\n", 27, 27);
1698 59 zero_gravi 
  }
1699 
  else {
1700 61 zero_gravi 
    PRINT_STANDARD("%c[1m[CPU TEST FAILED!]%c[0m\n", 27, 27);
1701 59 zero_gravi 
  }
1702 
 
1703 61 zero_gravi 
  return (int)cnt_fail; // return error counter for after-main handler
1704 59 zero_gravi 
}
1705 
 
1706 
 
1707 
/**********************************************************************//**
1708 
 * Simulation-based function to trigger CPU interrupts (MSI, MEI, FIRQ4..7).
1709 
 *
1710 
 * @param[in] sel IRQ select mask (bit positions according to #NEORV32_CSR_MIE_enum).
1711 
 **************************************************************************/
1712 
void sim_irq_trigger(uint32_t sel) {
1713 
 
1714 
  *(IO_REG32 (0xFF000000)) = sel;
1715 64 zero_gravi 
  asm volatile("nop"); // interrupt should kick in here (latest)
1716 
  *(IO_REG32 (0xFF000000)) = 0;
1717 59 zero_gravi 
}
1718 
 
1719 
 
1720 
/**********************************************************************//**
1721 
 * Trap handler for ALL exceptions/interrupts.
1722 
 **************************************************************************/
1723 
void global_trap_handler(void) {
1724 
 
1725 
  // hack: always come back in MACHINE MODE
1726 
  register uint32_t mask = (1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L);
1727 
  asm volatile ("csrrs zero, mstatus, %[input_j]" :  : [input_j] "r" (mask));
1728 
}
1729 
 
1730 
 
1731 
/**********************************************************************//**
1732 61 zero_gravi 
 * XIRQ handler channel 0.
1733 
 **************************************************************************/
1734 
void xirq_trap_handler0(void) {
1735 
 
1736 
  xirq_trap_handler_ack += 2;
1737 
}
1738 
 
1739 
 
1740 
/**********************************************************************//**
1741 
 * XIRQ handler channel 1.
1742 
 **************************************************************************/
1743 
void xirq_trap_handler1(void) {
1744 
 
1745 
  xirq_trap_handler_ack *= 2;
1746 
}
1747 
 
1748 
 
1749 
/**********************************************************************//**
1750 59 zero_gravi 
 * Test results helper function: Shows "[ok]" and increments global cnt_ok
1751 
 **************************************************************************/
1752 
void test_ok(void) {
1753 
 
1754 61 zero_gravi 
  PRINT_STANDARD("%c[1m[ok]%c[0m\n", 27, 27);
1755 59 zero_gravi 
  cnt_ok++;
1756 
}
1757 
 
1758 
 
1759 
/**********************************************************************//**
1760 61 zero_gravi 
 * Test results helper function: Shows "[FAIL]" and increments global cnt_fail
1761 59 zero_gravi 
 **************************************************************************/
1762 
void test_fail(void) {
1763 
 
1764 61 zero_gravi 
  PRINT_CRITICAL("%c[1m[FAIL]%c[0m\n", 27, 27);
1765 59 zero_gravi 
  cnt_fail++;
1766 
}
1767 61 zero_gravi 
 
1768 
 
1769 
/**********************************************************************//**
1770 
 * "after-main" handler that is executed after the application's
1771 
 * main function returns (called by crt0.S start-up code): Output minimal
1772 
 * test report to physical UART
1773 
 **************************************************************************/
1774 
int __neorv32_crt0_after_main(int32_t return_code) {
1775 
 
1776 
  // make sure sim mode is disabled and UARTs are actually enabled
1777 64 zero_gravi 
  NEORV32_UART0.CTRL |=  (1 << UART_CTRL_EN);
1778 
  NEORV32_UART0.CTRL &= ~(1 << UART_CTRL_SIM_MODE);
1779 
  NEORV32_UART1.CTRL = NEORV32_UART0.CTRL;
1780 61 zero_gravi 
 
1781 
  // minimal result report
1782 
  PRINT_CRITICAL("%u/%u\n", (uint32_t)return_code, (uint32_t)cnt_test);
1783 
 
1784 
  return 0;
1785 
}

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