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// #################################################################################################

// # << NEORV32 - Processor Test Program >>                                                        #

// # ********************************************************************************************* #

// # BSD 3-Clause License                                                                          #

// #                                                                                               #

// # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #

// #                                                                                               #

// # Redistribution and use in source and binary forms, with or without modification, are          #

// # permitted provided that the following conditions are met:                                     #

// #                                                                                               #

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// #    conditions and the following disclaimer.                                                   #

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// #    conditions and the following disclaimer in the documentation and/or other materials        #

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// #    permission.                                                                                #

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// # ********************************************************************************************* #

// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #

// #################################################################################################

/**********************************************************************//**

 * @file processor_check/main.c

 * @author Stephan Nolting

 * @brief CPU/Processor test program.

 **************************************************************************/

#include <neorv32.h>

#include <string.h>

/**********************************************************************//**

 * @name User configuration

 **************************************************************************/

/**@{*/

/** UART BAUD rate */

#define BAUD_RATE           (19200)

//** Reachable unaligned address */

#define ADDR_UNALIGNED_1    (0x00000001)

//** Reachable unaligned address */

#define ADDR_UNALIGNED_2    (0x00000002)

//** Unreachable word-aligned address */

#define ADDR_UNREACHABLE    (IO_BASE_ADDRESS-4)

//**Read-only word-aligned address */

#define ADDR_READONLY       ((uint32_t)&NEORV32_SYSINFO.CLK)

//** external memory base address */

#define EXT_MEM_BASE        (0xF0000000)

/**@}*/

/**********************************************************************//**

 * @name UART print macros

 **************************************************************************/

/**@{*/

//** for simulation only! */

#ifdef SUPPRESS_OPTIONAL_UART_PRINT

//** print standard output to UART0 */

#define PRINT_STANDARD(...) 

//** print critical output to UART1 */

#define PRINT_CRITICAL(...) neorv32_uart1_printf(__VA_ARGS__)

#else

//** print standard output to UART0 */

#define PRINT_STANDARD(...) neorv32_uart0_printf(__VA_ARGS__)

//** print critical output to UART0 */

#define PRINT_CRITICAL(...) neorv32_uart0_printf(__VA_ARGS__)

#endif

/**@}*/

// Prototypes

void sim_irq_trigger(uint32_t sel);

void global_trap_handler(void);

void xirq_trap_handler0(void);

void xirq_trap_handler1(void);

void test_ok(void);

void test_fail(void);

// Global variables (also test initialization of global vars here)

/// Global counter for failing tests

int cnt_fail = 0;

/// Global counter for successful tests

int cnt_ok   = 0;

/// Global counter for total number of tests

int cnt_test = 0;

/// Global number of available HPMs

uint32_t num_hpm_cnts_global = 0;

/// XIRQ trap handler acknowledge

uint32_t xirq_trap_handler_ack = 0;

/// Variable to test atomic accesses

uint32_t atomic_access_addr;

/**********************************************************************//**

 * High-level CPU/processor test program.

 *

 * @note Applications has to be compiler with <USER_FLAGS+=-DRUN_CPUTEST>

 * @warning This test is intended for simulation only.

 * @warning This test requires all optional extensions/modules to be enabled.

 *

 * @return 0 if execution was successful

 **************************************************************************/

int main() {

  register uint32_t tmp_a, tmp_b;

  uint8_t id;

  // disable global interrupts

  neorv32_cpu_dint();

  // init UARTs at default baud rate, no parity bits, no hw flow control

  neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);

  NEORV32_UART1.CTRL = NEORV32_UART0.CTRL; // copy configuration to initialize UART1

#ifdef SUPPRESS_OPTIONAL_UART_PRINT

  neorv32_uart0_disable(); // do not generate any UART0 output

#endif

// Disable processor_check compilation by default

#ifndef RUN_CHECK

  #warning processor_check HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.

  // inform the user if you are actually executing this

  PRINT_CRITICAL("ERROR! processor_check has not been compiled. Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.\n");

  return 1;

#endif

  // ----------------------------------------------

  // setup RTE

  neorv32_rte_setup(); // this will install a full-detailed debug handler for ALL traps

  // ----------------------------------------------

  // check available hardware extensions and compare with compiler flags

  neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch

  // intro

  PRINT_STANDARD("\n<< PROCESSOR CHECK >>\n");

  PRINT_STANDARD("build: "__DATE__" "__TIME__"\n");

  PRINT_STANDARD("is simulation: ");

  if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IS_SIM)) {

    PRINT_STANDARD("yes\n");

  }

  else {

    PRINT_STANDARD("no\n");

  }

  // reset performance counter

  // neorv32_cpu_csr_write(CSR_MCYCLEH, 0);   -> done in crt0.S

  // neorv32_cpu_csr_write(CSR_MCYCLE, 0);    -> done in crt0.S

  // neorv32_cpu_csr_write(CSR_MINSTRETH, 0); -> done in crt0.S

  // neorv32_cpu_csr_write(CSR_MINSTRET, 0);  -> done in crt0.S

  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable performance counter auto increment (ALL counters)

  neorv32_cpu_csr_write(CSR_MCOUNTEREN, 7); // allow access from user-mode code to standard counters only

  // set CMP of machine system timer MTIME to max to prevent an IRQ

  neorv32_mtime_set_timecmp(-1);

  neorv32_mtime_set_time(0);

  // fancy intro

  // -----------------------------------------------

  // logo

  neorv32_rte_print_logo();

  // show project credits

  neorv32_rte_print_credits();

  // show full HW config report

  neorv32_rte_print_hw_config();

  // configure RTE

  // -----------------------------------------------

  PRINT_STANDARD("\n\nRTE setup... ");

  int install_err = 0;

  // initialize ALL provided trap handler (overriding the default debug handlers)

  for (id=0; id<NEORV32_RTE_NUM_TRAPS; id++) {

    install_err += neorv32_rte_exception_install(id, global_trap_handler);

  }

  if (install_err) {

    PRINT_CRITICAL("ERROR!\n");

    return 1;

  }

  // clear testbench IRQ triggers

  sim_irq_trigger(0);

  // clear all interrupt enables, enable only where needed

  neorv32_cpu_csr_write(CSR_MIE, 0);

  // test intro

  PRINT_STANDARD("\nStarting tests.\n\n");

  // sync (test)

  asm volatile ("fence.i");

  // enable global interrupts

  neorv32_cpu_eint();

  // **********************************************************************************************

  // Run CPU and SoC tests

  // **********************************************************************************************

  // ----------------------------------------------------------

  // Test performance counter: setup as many events and counter as feasible

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] Setup HPM events: ", cnt_test);

  num_hpm_cnts_global = neorv32_cpu_hpm_get_counters();

  if (num_hpm_cnts_global != 0) {

    cnt_test++;

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER3,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT3,  1 << HPMCNT_EVENT_CIR);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER4,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT4,  1 << HPMCNT_EVENT_WAIT_IF);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER5,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT5,  1 << HPMCNT_EVENT_WAIT_II);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER6,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT6,  1 << HPMCNT_EVENT_WAIT_MC);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER7,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT7,  1 << HPMCNT_EVENT_LOAD);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER8,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT8,  1 << HPMCNT_EVENT_STORE);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER9,  0); neorv32_cpu_csr_write(CSR_MHPMEVENT9,  1 << HPMCNT_EVENT_WAIT_LS);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT10, 1 << HPMCNT_EVENT_JUMP);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_BRANCH);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT12, 1 << HPMCNT_EVENT_TBRANCH);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT13, 1 << HPMCNT_EVENT_TRAP);

    neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT14, 1 << HPMCNT_EVENT_ILLEGAL);

    neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable all counters

    // make sure there was no exception

    if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {

      test_ok();

    }

    else {

      test_fail();

    }

  }

  else {

    PRINT_STANDARD("skipped (n.a.)\n");

  }

//// ----------------------------------------------------------

//// Test standard RISC-V performance counter [m]cycle[h]

//// ----------------------------------------------------------

//neorv32_cpu_csr_write(CSR_MCAUSE, 0);

//PRINT_STANDARD("[%i] cycle counter: ", cnt_test);

//

//cnt_test++;

//

//// make sure counter is enabled

//asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_CY));

//

//// prepare overflow

//neorv32_cpu_set_mcycle(0x00000000FFFFFFFFULL);

//

//// get current cycle counter HIGH

//tmp_a = neorv32_cpu_csr_read(CSR_MCYCLEH);

//

//// make sure cycle counter high has incremented and there was no exception during access

//if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {

//  test_ok();

//}

//else {

//  test_fail();

//}

//// ----------------------------------------------------------

//// Test standard RISC-V performance counter [m]instret[h]

//// ----------------------------------------------------------

//neorv32_cpu_csr_write(CSR_MCAUSE, 0);

//PRINT_STANDARD("[%i] instret counter: ", cnt_test);

//

//cnt_test++;

//

//// make sure counter is enabled

//asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_IR));

//

//// prepare overflow

//neorv32_cpu_set_minstret(0x00000000FFFFFFFFULL);

//

//// get instruction counter HIGH

//tmp_a = neorv32_cpu_csr_read(CSR_INSTRETH);

//

//// make sure instruction counter high has incremented and there was no exception during access

//if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {

//  test_ok();

//}

//else {

//  test_fail();

//}

  // ----------------------------------------------------------

  // Test mcountinhibt: inhibit auto-inc of [m]cycle

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] mcountinhibt.cy CSR: ", cnt_test);

  cnt_test++;

  // inhibit [m]cycle CSR

  tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);

  tmp_a |= (1<<CSR_MCOUNTINHIBIT_CY); // inhibit cycle counter auto-increment

  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp_a);

  // get current cycle counter

  tmp_a = neorv32_cpu_csr_read(CSR_CYCLE);

  // wait some time to have a nice "increment" (there should be NO increment at all!)

  asm volatile ("nop");

  asm volatile ("nop");

  tmp_b = neorv32_cpu_csr_read(CSR_CYCLE);

  // make sure instruction counter has NOT incremented and there was no exception during access

  if ((tmp_a == tmp_b) && (tmp_a != 0) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {

    test_ok();

  }

  else {

    test_fail();

  }

  // re-enable [m]cycle CSR

  tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);

  tmp_a &= ~(1<<CSR_MCOUNTINHIBIT_CY); // clear inhibit of cycle counter auto-increment

  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp_a);

  // ----------------------------------------------------------

  // Test mcounteren: do not allow cycle[h] access from user-mode

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] mcounteren.cy CSR: ", cnt_test);

  cnt_test++;

  // do not allow user-level code to access cycle[h] CSRs

  tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);

  tmp_a &= ~(1<<CSR_MCOUNTEREN_CY); // clear access right

  neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);

  neorv32_cpu_csr_write(CSR_CYCLE, 1); // make sure CSR is != 0 for this test

  // switch to user mode (hart will be back in MACHINE mode when trap handler returns)

  neorv32_cpu_goto_user_mode();

  {

    // access to cycle CSR is no longer allowed

    asm volatile (" mv      %[result], zero  \n" // initialize with zero

                  " rdcycle %[result]          " // read CSR_CYCLE, is not allowed and should not alter [result]

                  : [result] "=r" (tmp_a) : );

  }

  if (tmp_a != 0) {

    PRINT_CRITICAL("%c[1m<SECURITY FAILURE> %c[0m\n", 27, 27);

  }

  // make sure there was an illegal instruction trap

  if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) && (tmp_a == 0)) {

    test_ok();

  }

  else {

    test_fail();

  }

  // re-allow user-level code to access cycle[h] CSRs

  tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);

  tmp_a |= (1<<CSR_MCOUNTEREN_CY); // re-allow access right

  neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);

  // ----------------------------------------------------------

  // Execute MRET in U-mode (has to trap!)

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] MRET in U-mode: ", cnt_test);

  cnt_test++;

  // switch to user mode (hart will be back in MACHINE mode when trap handler returns)

  neorv32_cpu_goto_user_mode();

  {

    asm volatile ("mret");

  }

  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {

    test_ok();

  }

  else {

    test_fail();

  }

  // ----------------------------------------------------------

  // External memory interface test

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] External memory access (@ 0x%x): ", cnt_test, (uint32_t)EXT_MEM_BASE);

  if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_EXT)) {

    cnt_test++;

    // create test program in RAM

    static const uint32_t dummy_ext_program[2] __attribute__((aligned(8))) = {

      0x3407D073, // csrwi mscratch, 15

      0x00008067  // ret (32-bit)

    };

    // copy to external memory

    if (memcpy((void*)EXT_MEM_BASE, (void*)&dummy_ext_program, (size_t)sizeof(dummy_ext_program)) == NULL) {

      test_fail();

    }

    else {

      // execute program

      tmp_a = (uint32_t)EXT_MEM_BASE; // call the dummy sub program

      asm volatile ("jalr ra, %[input_i]" :  : [input_i] "r" (tmp_a));

      if ((neorv32_cpu_csr_read(CSR_MCAUSE) == 0) && // make sure there was no exception

          (neorv32_cpu_csr_read(CSR_MSCRATCH) == 15)) { // make sure the program was executed in the right way

        test_ok();

      }

      else {

        test_fail();

      }

    }

  }

  else {

    PRINT_STANDARD("skipped (n.a.)\n");

  }

  // ----------------------------------------------------------

  // Illegal CSR access (CSR not implemented)

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] Non-existent CSR access: ", cnt_test);

  cnt_test++;

  tmp_a = neorv32_cpu_csr_read(0xfff); // CSR 0xfff not implemented

  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {

    test_ok();

  }

  else {

    test_fail();

  }

  // ----------------------------------------------------------

  // Write-access to read-only CSR

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] Read-only CSR write access: ", cnt_test);

  cnt_test++;

  neorv32_cpu_csr_write(CSR_TIME, 0); // time CSR is read-only

  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {

    test_ok();

  }

  else {

    test_fail();

  }

//// ----------------------------------------------------------

//// No "real" CSR write access (because rs1 = r0)

//// ----------------------------------------------------------

//neorv32_cpu_csr_write(CSR_MCAUSE, 0);

//PRINT_STANDARD("[%i] Read-only CSR 'no-write' (rs1=0) access: ", cnt_test);

//

//cnt_test++;

//

//// time CSR is read-only, but no actual write is performed because rs1=r0

//// -> should cause no exception

//asm volatile("csrrs zero, time, zero");

//

//if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {

//  test_ok();

//}

//else {

//  test_fail();

//}

  // ----------------------------------------------------------

  // Unaligned instruction address

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] I_ALIGN (instr. alignment) EXC: ", cnt_test);

  // skip if C-mode is implemented

  if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C)) == 0) {

    cnt_test++;

    // call unaligned address

    ((void (*)(void))ADDR_UNALIGNED_2)();

    asm volatile("nop");

    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_MISALIGNED) {

      test_ok();

    }

    else {

      test_fail();

    }

  }

  else {

    PRINT_STANDARD("skipped (n.a. with C-ext)\n");

  }

  // ----------------------------------------------------------

  // Instruction access fault

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] I_ACC (instr. bus access) EXC: ", cnt_test);

  cnt_test++;

  // call unreachable aligned address

  ((void (*)(void))ADDR_UNREACHABLE)();

  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ACCESS) {

    test_ok();

  }

  else {

    test_fail();

  }

  // ----------------------------------------------------------

  // Illegal instruction

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] I_ILLEG (illegal instr.) EXC: ", cnt_test);

  cnt_test++;

  // illegal 32-bit instruction (malformed SUB)

  asm volatile (".align 4 \n"

                ".word 0x80000033");

  // make sure this has cause an illegal exception

  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {

    // make sure this is really the instruction that caused the exception

    // -> for illegal instructions MTVAL contains the faulting instruction word

    if (neorv32_cpu_csr_read(CSR_MTVAL) == 0x80000033) {

      test_ok();

    }

    else {

      test_fail();

    }

  }

  else {

    test_fail();

  }

  // ----------------------------------------------------------

  // Illegal compressed instruction

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] CI_ILLEG (illegal compr. instr.) EXC: ", cnt_test);

  // skip if C-mode is not implemented

  if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C))) {

    cnt_test++;

    // illegal 16-bit instruction (official UNIMP instruction)

    asm volatile (".align 2     \n"

                  ".half 0x0001 \n" // NOP

                  ".half 0x0000");  // UNIMP

    if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {

      test_ok();

    }

    else {

      test_fail();

    }

  }

  else {

    PRINT_STANDARD("skipped (n.a. with C-ext)\n");

  }

  // ----------------------------------------------------------

  // Breakpoint instruction

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] BREAK (break instr.) EXC: ", cnt_test);

  cnt_test++;

  asm volatile("EBREAK");

  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_BREAKPOINT) {

    test_ok();

  }

  else {

    test_fail();

  }

  // ----------------------------------------------------------

  // Unaligned load address

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] L_ALIGN (load addr alignment) EXC: ", cnt_test);

  cnt_test++;

  // load from unaligned address

  neorv32_cpu_load_unsigned_word(ADDR_UNALIGNED_1);

  if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_L_MISALIGNED) &&

      (neorv32_cpu_csr_read(CSR_MTVAL) == ADDR_UNALIGNED_1)) {

    test_ok();

  }

  else {

    test_fail();

  }

  // ----------------------------------------------------------

  // Load access fault

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] L_ACC (load bus access) EXC: ", cnt_test);

  cnt_test++;

  tmp_a = (1 << BUSKEEPER_ERR_FLAG) | (1 << BUSKEEPER_ERR_TYPE);

  // load from unreachable aligned address

  neorv32_cpu_load_unsigned_word(ADDR_UNREACHABLE);

  if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_L_ACCESS) && // load bus access error exception

     (NEORV32_BUSKEEPER.CTRL = tmp_a)) { // buskeeper: error flag + timeout error

    test_ok();

  }

  else {

    test_fail();

  }

  // ----------------------------------------------------------

  // Unaligned store address

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] S_ALIGN (store addr alignment) EXC: ", cnt_test);

  cnt_test++;

  // store to unaligned address

  neorv32_cpu_store_unsigned_word(ADDR_UNALIGNED_2, 0);

  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_MISALIGNED) {

    test_ok();

  }

  else {

    test_fail();

  }

  // ----------------------------------------------------------

  // Store access fault

  // ----------------------------------------------------------

  neorv32_cpu_csr_write(CSR_MCAUSE, 0);

  PRINT_STANDARD("[%i] S_ACC (store bus access) EXC: ", cnt_test);

  cnt_test++;

  tmp_a = (1 << BUSKEEPER_ERR_FLAG) | (0 << BUSKEEPER_ERR_TYPE);

  // store to unreachable aligned address

  neorv32_cpu_store_unsigned_word(ADDR_READONLY, 0);