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1 2 zero_gravi
// #################################################################################################
2
// # << NEORV32: neorv32.h - Main Core Library File >>                                             #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License                                                                          #
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// #                                                                                               #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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// #                                                                                               #
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// # Redistribution and use in source and binary forms, with or without modification, are          #
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// # permitted provided that the following conditions are met:                                     #
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// #                                                                                               #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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// #    conditions and the following disclaimer.                                                   #
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// #                                                                                               #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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// #    conditions and the following disclaimer in the documentation and/or other materials        #
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// #    provided with the distribution.                                                            #
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// #                                                                                               #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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// #    endorse or promote products derived from this software without specific prior written      #
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// #    permission.                                                                                #
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// #                                                                                               #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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// # ********************************************************************************************* #
32
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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// #################################################################################################
34
 
35
 
36
/**********************************************************************//**
37
 * @file neorv32.h
38
 * @author Stephan Nolting
39
 * @date 30 May 2020
40
 *
41
 * @brief Main NEORV32 core library file.
42
 *
43
 * @details This file defines the addresses of the IO devices and their according
44
 * registers and register bits as well as the available CPU CSRs and flags.
45
 **************************************************************************/
46
 
47
#ifndef neorv32_h
48
#define neorv32_h
49
 
50
// Standard libraries
51
#include <stdint.h>
52
#include <stdlib.h>
53
#include <string.h>
54
#include <stdbool.h>
55
#include <inttypes.h>
56
#include <limits.h>
57
 
58
 
59
/**********************************************************************//**
60
 * Available CPU Control and Status Registers (CSRs)
61
 **************************************************************************/
62
enum NEORV32_CPU_CSRS_enum {
63 6 zero_gravi
  CSR_MSTATUS     = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
64
  CSR_MISA        = 0x301, /**< 0x301 - misa    (r/-): CPU ISA and extensions */
65
  CSR_MIE         = 0x304, /**< 0x304 - mie     (r/w): Machine interrupt-enable register */
66
  CSR_MTVEC       = 0x305, /**< 0x305 - mtvec   (r/w): Machine trap-handler base address (for ALL traps) */
67 2 zero_gravi
 
68
  CSR_MSCRATCH    = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
69
  CSR_MEPC        = 0x341, /**< 0x341 - mepc     (r/w): Machine exception program counter */
70
  CSR_MCAUSE      = 0x342, /**< 0x342 - mcause   (r/-): Machine trap cause */
71
  CSR_MTVAL       = 0x343, /**< 0x343 - mtval    (r/-): Machine bad address or instruction */
72
  CSR_MIP         = 0x344, /**< 0x344 - mip      (r/w): Machine interrupt pending register */
73
 
74 11 zero_gravi
  CSR_MCYCLE      = 0xb00, /**< 0xb00 - mcycle    (r/w): Machine cycle counter low word */
75
  CSR_MINSTRET    = 0xb02, /**< 0xb02 - minstret  (r/w): Machine instructions-retired counter low word */
76
  CSR_MCYCLEH     = 0xb80, /**< 0xb80 - mcycleh   (r/w): Machine cycle counter high word */
77
  CSR_MINSTRETH   = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */
78 2 zero_gravi
 
79
  CSR_CYCLE       = 0xc00, /**< 0xc00 - cycle    (r/-): Cycle counter low word */
80 11 zero_gravi
  CSR_TIME        = 0xc01, /**< 0xc01 - time     (r/-): Timer low word (from MTIME.TIME) */
81 2 zero_gravi
  CSR_INSTRET     = 0xc02, /**< 0xc02 - instret  (r/-): Instructions-retired counter low word */
82
 
83
  CSR_CYCLEH      = 0xc80, /**< 0xc80 - cycleh   (r/-): Cycle counter high word */
84 11 zero_gravi
  CSR_TIMEH       = 0xc81, /**< 0xc81 - timeh    (r/-): Timer high word (from MTIME.TIME) */
85 2 zero_gravi
  CSR_INSTRETH    = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word */
86
 
87
  CSR_MIMPID      = 0xf13, /**< 0xf13 - mimpid  (r/-): Implementation ID/version */
88
  CSR_MHARTID     = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (via HART_ID generic) */
89
 
90
  CSR_MFEATURES   = 0xfc0, /**< 0xfc0 - CUSTOM (r/-): Implemented processor devices/features (via IO_x_USE generics) */
91
  CSR_MCLOCK      = 0xfc1, /**< 0xfc1 - CUSTOM (r/-): Processor primary clock spedd in Hz (via CLOCK_FREQUENCY generic)*/
92
  CSR_MISPACEBASE = 0xfc4, /**< 0xfc4 - CUSTOM (r/-): Base address of instruction memory space (via MEM_ISPACE_BASE generic) */
93
  CSR_MDSPACEBASE = 0xfc5, /**< 0xfc5 - CUSTOM (r/-): Base address of data memory space (via MEM_DSPACE_BASE generic) */
94
  CSR_MISPACESIZE = 0xfc6, /**< 0xfc6 - CUSTOM (r/-): Total size of instruction memory space in byte (via MEM_ISPACE_SIZE generic) */
95
  CSR_MDSPACESIZE = 0xfc7  /**< 0xfc7 - CUSTOM (r/-): Total size of data memory space in byte (via MEM_DSPACE_SIZE generic) */
96
};
97
 
98
 
99
/**********************************************************************//**
100
 * CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
101
 **************************************************************************/
102
enum NEORV32_CPU_MSTATUS_enum {
103
  CPU_MSTATUS_MIE  = 3, /**< CPU mstatus CSR (3): Machine interrupt enable bit (r/w) */
104
  CPU_MSTATUS_MPIE = 7  /**< CPU mstatus CSR (7): Machine previous interrupt enable bit (r/w) */
105
};
106
 
107
 
108
/**********************************************************************//**
109
 * CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.)
110
 **************************************************************************/
111
enum NEORV32_CPU_MIE_enum {
112
  CPU_MIE_MSIE  =  3, /**< CPU mie CSR (3): Machine software interrupt enable bit (r/w) */
113
  CPU_MIE_MTIE  =  7, /**< CPU mie CSR (7): Machine timer interrupt (MTIME) enable bit (r/w) */
114
  CPU_MIE_MEIE  = 11  /**< CPU mie CSR (11): Machine external interrupt (via CLIC) enable bit (r/w) */
115
};
116
 
117
 
118
/**********************************************************************//**
119
 * CPU <b>mip</b> CSR (r/w): Machine interrupt pending (RISC-V spec.)
120
 **************************************************************************/
121
enum NEORV32_CPU_MIP_enum {
122
  CPU_MIP_MSIP  =  3, /**< CPU mip CSR (3): Machine software interrupt pending (r/w), can be triggered when set */
123
  CPU_MIP_MTIP  =  7, /**< CPU mip CSR (7): Machine timer interrupt (MTIME) pending (r/-) */
124
  CPU_MIP_MEIP  = 11  /**< CPU mip CSR (11): Machine external interrupt (via CLIC) pending (r/-) */
125
};
126
 
127
 
128
/**********************************************************************//**
129 6 zero_gravi
 * CPU <b>misa</b> CSR (r/w): Machine instruction set extensions (RISC-V spec.)
130
 **************************************************************************/
131
enum NEORV32_CPU_MISA_enum {
132 11 zero_gravi
  CPU_MISA_C_EXT      =  2, /**< CPU misa CSR  (2): C: Compressed instructions CPU extension available (r/-), can be switched on/off */
133 6 zero_gravi
  CPU_MISA_E_EXT      =  4, /**< CPU misa CSR  (3): E: Embedded CPU extension available (r/-) */
134
  CPU_MISA_I_EXT      =  8, /**< CPU misa CSR  (8): I: Base integer ISA CPU extension available (r/-) */
135 11 zero_gravi
  CPU_MISA_M_EXT      = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-), can be switched on/off */
136 6 zero_gravi
  CPU_MISA_X_EXT      = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
137 8 zero_gravi
  CPU_MISA_Z_EXT      = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension(s) available (r/-) */
138 6 zero_gravi
  CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
139
  CPU_MISA_MXL_HI_EXT = 31  /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
140
};
141
 
142
 
143
/**********************************************************************//**
144 2 zero_gravi
 * CPU <b>mfeatures</b> CSR (r/-): Implemented processor devices/features (CUSTOM)
145
 **************************************************************************/
146
 enum NEORV32_CPU_MFEATURES_enum {
147
  CPU_MFEATURES_BOOTLOADER       =  0, /**< CPU mfeatures CSR (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
148
  CPU_MFEATURES_MEM_EXT          =  1, /**< CPU mfeatures CSR (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
149
  CPU_MFEATURES_MEM_INT_IMEM     =  2, /**< CPU mfeatures CSR (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
150
  CPU_MFEATURES_MEM_INT_IMEM_ROM =  3, /**< CPU mfeatures CSR (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
151
  CPU_MFEATURES_MEM_INT_DMEM     =  4, /**< CPU mfeatures CSR (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
152 6 zero_gravi
  CPU_MFEATURES_CSR_COUNTERS     =  5, /**< CPU mfeatures CSR (5) (r/-): RISC-V performance counters implemented when 1 (via CSR_COUNTERS_USE generic) */
153 2 zero_gravi
 
154
  CPU_MFEATURES_IO_GPIO          = 16, /**< CPU mfeatures CSR (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
155
  CPU_MFEATURES_IO_MTIME         = 17, /**< CPU mfeatures CSR (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
156
  CPU_MFEATURES_IO_UART          = 18, /**< CPU mfeatures CSR (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
157
  CPU_MFEATURES_IO_SPI           = 19, /**< CPU mfeatures CSR (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
158
  CPU_MFEATURES_IO_TWI           = 20, /**< CPU mfeatures CSR (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */
159
  CPU_MFEATURES_IO_PWM           = 21, /**< CPU mfeatures CSR (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */
160
  CPU_MFEATURES_IO_WDT           = 22, /**< CPU mfeatures CSR (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */
161
  CPU_MFEATURES_IO_CLIC          = 23, /**< CPU mfeatures CSR (23) (r/-): Core-local interrupt controller implemented when 1 (via IO_CLIC_USE generic) */
162 3 zero_gravi
  CPU_MFEATURES_IO_TRNG          = 24, /**< CPU mfeatures CSR (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
163
  CPU_MFEATURES_IO_DEVNULL       = 25  /**< CPU mfeatures CSR (24) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */
164 2 zero_gravi
};
165
 
166
 
167
/**********************************************************************//**
168
 * Exception IDs.
169
 **************************************************************************/
170
enum NEORV32_EXCEPTION_IDS_enum {
171
  EXCID_I_MISALIGNED =  0, /**< 0: Instruction address misaligned */
172
  EXCID_I_ACCESS     =  1, /**< 1: Instruction (bus) access fault */
173
  EXCID_I_ILLEGAL    =  2, /**< 2: Illegal instruction */
174
  EXCID_BREAKPOINT   =  3, /**< 3: Breakpoint (EBREAK instruction) */
175
  EXCID_L_MISALIGNED =  4, /**< 4: Load address misaligned */
176
  EXCID_L_ACCESS     =  5, /**< 5: Load (bus) access fault */
177
  EXCID_S_MISALIGNED =  6, /**< 6: Store address misaligned */
178
  EXCID_S_ACCESS     =  7, /**< 7: Store (bus) access fault */
179
  EXCID_MENV_CALL    = 11, /**< 11: Environment call from machine mode (ECALL instruction) */
180
  EXCID_MSI          = 19, /**< 16 + 3: Machine software interrupt */
181
  EXCID_MTI          = 23, /**< 16 + 7: Machine timer interrupt (via MTIME) */
182
  EXCID_MEI          = 27  /**< 16 + 11: Machine external interrupt (via CLIC) */
183
};
184
 
185
 
186
/**********************************************************************//**
187
 * Processor clock prescalers
188
 **************************************************************************/
189
enum NEORV32_CLOCK_PRSC_enum {
190
  CLK_PRSC_2    =  0, /**< CPU_CLK / 2 */
191
  CLK_PRSC_4    =  1, /**< CPU_CLK / 4 */
192
  CLK_PRSC_8    =  2, /**< CPU_CLK / 8 */
193
  CLK_PRSC_64   =  3, /**< CPU_CLK / 64 */
194
  CLK_PRSC_128  =  4, /**< CPU_CLK / 128 */
195
  CLK_PRSC_1024 =  5, /**< CPU_CLK / 1024 */
196
  CLK_PRSC_2048 =  6, /**< CPU_CLK / 2048 */
197
  CLK_PRSC_4096 =  7  /**< CPU_CLK / 4096 */
198
};
199
 
200
 
201
/**********************************************************************//**
202
 * @name Helper macros for easy memory-mapped register access
203
 **************************************************************************/
204
/**@{*/
205
/** memory-mapped byte (8-bit) read/write register */
206
#define IO_REG8  (volatile uint8_t*)
207
/** memory-mapped half-word (16-bit) read/write register */
208
#define IO_REG16 (volatile uint16_t*)
209
/** memory-mapped word (32-bit) read/write register */
210
#define IO_REG32 (volatile uint32_t*)
211
/** memory-mapped double-word (64-bit) read/write register */
212
#define IO_REG64 (volatile uint64_t*)
213
/** memory-mapped byte (8-bit) read-only register */
214
#define IO_ROM8  (const volatile uint8_t*) 
215
/** memory-mapped half-word (16-bit) read-only register */
216
#define IO_ROM16 (const volatile uint16_t*)
217
/** memory-mapped word (32-bit) read-only register */
218
#define IO_ROM32 (const volatile uint32_t*)
219
/** memory-mapped double-word (64-bit) read-only register */
220
#define IO_ROM64 (const volatile uint64_t*)
221
/**@}*/
222
 
223
 
224
/**********************************************************************//**
225
 * @name Address space sections
226
 **************************************************************************/
227
/**@{*/
228
/** instruction memory base address (r/w/x) */
229 6 zero_gravi
// -> use value from MEM_ISPACE_BASE CSR
230 2 zero_gravi
/** data memory base address (r/w/x) */
231 6 zero_gravi
// -> use value from MEM_DSPACE_BASE CSR
232 2 zero_gravi
/** bootloader memory base address (r/-/x) */
233 6 zero_gravi
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
234 2 zero_gravi
/** peripheral/IO devices memory base address (r/w/x) */
235 6 zero_gravi
#define IO_BASE_ADDRESS (0xFFFFFF80UL)
236 2 zero_gravi
/**@}*/
237
 
238
 
239
/**********************************************************************//**
240
 * @name IO Device: General Purpose Input/Output Port Unit (GPIO)
241
 **************************************************************************/
242
/**@{*/
243
/** GPIO parallel input port (r/-) */
244 6 zero_gravi
#define GPIO_INPUT  (*(IO_ROM32 0xFFFFFF80UL))
245 2 zero_gravi
/** GPIO parallel output port (r/w) */
246 6 zero_gravi
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
247 2 zero_gravi
/**@}*/
248
 
249
 
250
/**********************************************************************//**
251
 * @name IO Device: Core Local Interrupts Controller (CLIC)
252
 **************************************************************************/
253
/**@{*/
254
/** CLIC control register (r/w) */
255 6 zero_gravi
#define CLIC_CT (*(IO_REG32 0xFFFFFF88UL))
256 2 zero_gravi
 
257
/** CLIC control register bits */
258
enum NEORV32_CLIC_CT_enum {
259
  CLIC_CT_SRC0        =  0, /**< CLIC control register(0) (r/-): IRQ source bit 0 */
260
  CLIC_CT_SRC1        =  1, /**< CLIC control register(1) (r/-): IRQ source bit 1 */
261
  CLIC_CT_SRC2        =  2, /**< CLIC control register(2) (r/-): IRQ source bit 2 */
262
  CLIC_CT_ACK         =  3, /**< CLIC control register(3) (-/w): Acknowledge current IRQ when set, auto-clears when set */
263
  CLIC_CT_EN          =  4, /**< CLIC control register(4) (r/w): Unit enable */
264
 
265
  CLIC_CT_IRQ0_EN     =  8, /**< CLIC control register(8)  (r/w): Enable IRQ channel 0 */
266
  CLIC_CT_IRQ1_EN     =  9, /**< CLIC control register(9)  (r/w): Enable IRQ channel 1 */
267
  CLIC_CT_IRQ2_EN     = 10, /**< CLIC control register(10) (r/w): Enable IRQ channel 2 */
268
  CLIC_CT_IRQ3_EN     = 11, /**< CLIC control register(11) (r/w): Enable IRQ channel 3 */
269
  CLIC_CT_IRQ4_EN     = 12, /**< CLIC control register(12) (r/w): Enable IRQ channel 4 */
270
  CLIC_CT_IRQ5_EN     = 13, /**< CLIC control register(13) (r/w): Enable IRQ channel 5 */
271
  CLIC_CT_IRQ6_EN     = 14, /**< CLIC control register(14) (r/w): Enable IRQ channel 6 */
272
  CLIC_CT_IRQ7_EN     = 15, /**< CLIC control register(15) (r/w): Enable IRQ channel 7 */
273
 
274
  CLIC_CT_SW_IRQ_SRC0 = 16, /**< CLIC control register(16) (-/w): SW IRQ trigger, IRQ select bit 0, auto-clears when set */
275
  CLIC_CT_SW_IRQ_SRC1 = 17, /**< CLIC control register(17) (-/w): SW IRQ trigger, IRQ select bit 1, auto-clears when set */
276
  CLIC_CT_SW_IRQ_SRC2 = 18, /**< CLIC control register(18) (-/w): SW IRQ trigger, IRQ select bit 2, auto-clears when set */
277
  CLIC_CT_SW_IRQ_EN   = 19  /**< CLIC control register(19) (-/w): SW IRQ trigger enable, auto-clears when set */
278
};
279
/**@}*/
280
 
281
 
282
/**********************************************************************//**
283
 * Core-local interrupt controller IRQ channel
284
 **************************************************************************/
285
enum NEORV32_CLIC_CHANNELS_enum {
286
  CLIC_CH_WDT   = 0, /**< CLIC channel 0: Watchdog timer overflow interrupt */
287
  CLIC_CH_RES   = 1, /**< CLIC channel 1: reserved */
288
  CLIC_CH_GPIO  = 2, /**< CLIC channel 2: GPIO pin-change interrupt */
289
  CLIC_CH_UART  = 3, /**< CLIC channel 3: UART RX available or TX done interrupt */
290
  CLIC_CH_SPI   = 4, /**< CLIC channel 4: SPI transmission done interrupt */
291
  CLIC_CH_TWI   = 5, /**< CLIC channel 5: TWI transmission done interrupt */
292
  CLIC_CH_EXT0  = 6, /**< CLIC channel 6: Processor-external interrupt request 0 */
293
  CLIC_CH_EXT1  = 7  /**< CLIC channel 7: Processor-external interrupt request 1 */
294
};
295
 
296
 
297
/**********************************************************************//**
298
 * @name IO Device: Watchdog Timer (WDT)
299
 **************************************************************************/
300
/**@{*/
301
/** Watchdog control register (r/w) */
302 6 zero_gravi
#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL))
303 2 zero_gravi
 
304
/** WTD control register bits */
305
enum NEORV32_WDT_CT_enum {
306
  WDT_CT_CLK_SEL0     =  0, /**< WDT control register(0) (r/w): Clock prescaler select bit 0 */
307
  WDT_CT_CLK_SEL1     =  1, /**< WDT control register(1) (r/w): Clock prescaler select bit 1 */
308
  WDT_CT_CLK_SEL2     =  2, /**< WDT control register(2) (r/w): Clock prescaler select bit 2 */
309
  WDT_CT_EN           =  3, /**< WDT control register(3) (r/w): Watchdog enable */
310
  WDT_CT_MODE         =  4, /**< WDT control register(4) (r/w): Watchdog mode; when 0: timeout causes interrupt; when 1: timeout causes processor reset */
311
  WDT_CT_CAUSE        =  5, /**< WDT control register(5) (r/-): Last action (reset/IRQ) cause (0: external reset, 1: watchdog timeout) */
312
  WDT_CT_PWFAIL       =  6, /**< WDT control register(6) (r/-): Last Watchdog action (reset/IRQ) caused by wrong password when 1 */
313
 
314
  WDT_CT_PASSWORD_LSB =  8, /**< WDT control register(8)  (-/w): First bit / position begin for watchdog access password */
315
  WDT_CT_PASSWORD_MSB = 15  /**< WDT control register(15) (-/w): Last bit / position end for watchdog access password */
316
};
317
 
318
/** Watchdog access passwort, must be set in WDT_CT bits 15:8 for every control register access */
319
#define WDT_PASSWORD 0x47
320
/**@}*/
321
 
322
 
323
/**********************************************************************//**
324
 * @name IO Device: Machine System Timer (MTIME)
325
 **************************************************************************/
326
/**@{*/
327 11 zero_gravi
/** MTIME (time register) low word (r/w) */
328
#define MTIME_LO     (*(IO_REG32 0xFFFFFF90UL))
329
/** MTIME (time register) high word (r/w) */
330
#define MTIME_HI     (*(IO_REG32 0xFFFFFF94UL))
331 2 zero_gravi
/** MTIMECMP (time compare register) low word (r/w) */
332 6 zero_gravi
#define MTIMECMP_LO  (*(IO_REG32 0xFFFFFF98UL))
333 2 zero_gravi
/** MTIMECMP (time register) high word (r/w) */
334 6 zero_gravi
#define MTIMECMP_HI  (*(IO_REG32 0xFFFFFF9CUL))
335 2 zero_gravi
 
336 11 zero_gravi
/** MTIME (time register) 64-bit access (r/w) */
337
#define MTIME        (*(IO_REG64 (&MTIME_LO)))
338 2 zero_gravi
/** MTIMECMP (time compare register) low word (r/w) */
339
#define MTIMECMP     (*(IO_REG64 (&MTIMECMP_LO)))
340
/**@}*/
341
 
342
 
343
/**********************************************************************//**
344
 * @name IO Device: Universal Asynchronous Receiver and Transmitter (UART)
345
 **************************************************************************/
346
/**@{*/
347
/** UART control register (r/w) */
348 6 zero_gravi
#define UART_CT  (*(IO_REG32 0xFFFFFFA0UL))
349 2 zero_gravi
/** UART receive/transmit data register (r/w) */
350 6 zero_gravi
#define UART_DATA (*(IO_REG32 0xFFFFFFA4UL))
351 2 zero_gravi
 
352
/** UART control register bits */
353
enum NEORV32_UART_CT_enum {
354
  UART_CT_BAUD00  =  0, /**< UART control register(0)  (r/w): BAUD rate config value lsb (12-bi, bit 0) */
355
  UART_CT_BAUD01  =  1, /**< UART control register(1)  (r/w): BAUD rate config value (12-bi, bit 1) */
356
  UART_CT_BAUD02  =  2, /**< UART control register(2)  (r/w): BAUD rate config value (12-bi, bit 2) */
357
  UART_CT_BAUD03  =  3, /**< UART control register(3)  (r/w): BAUD rate config value (12-bi, bit 3) */
358
  UART_CT_BAUD04  =  4, /**< UART control register(4)  (r/w): BAUD rate config value (12-bi, bit 4) */
359
  UART_CT_BAUD05  =  5, /**< UART control register(5)  (r/w): BAUD rate config value (12-bi, bit 4) */
360
  UART_CT_BAUD06  =  6, /**< UART control register(6)  (r/w): BAUD rate config value (12-bi, bit 5) */
361
  UART_CT_BAUD07  =  7, /**< UART control register(7)  (r/w): BAUD rate config value (12-bi, bit 6) */
362
  UART_CT_BAUD08  =  8, /**< UART control register(8)  (r/w): BAUD rate config value (12-bi, bit 7) */
363
  UART_CT_BAUD09  =  9, /**< UART control register(9)  (r/w): BAUD rate config value (12-bi, bit 8) */
364
  UART_CT_BAUD10  = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bi, bit 9) */
365
  UART_CT_BAUD11  = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bi, bit 0)*/
366
 
367
  UART_CT_PRSC0   = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
368
  UART_CT_PRSC1   = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
369
  UART_CT_PRSC2   = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
370
  UART_CT_RXOR    = 27, /**< UART control register(27) (r/-): RX data overrun when set */
371
  UART_CT_EN      = 28, /**< UART control register(28) (r/w): UART global enable */
372
  UART_CT_RX_IRQ  = 29, /**< UART control register(29) (r/w): Activate interrupt on RX done */
373
  UART_CT_TX_IRQ  = 30, /**< UART control register(30) (r/w): Activate interrupt on TX done */
374
  UART_CT_TX_BUSY = 31  /**< UART control register(31) (r/-): Transmitter is busy when set */
375
};
376
 
377
/** UART receive/transmit data register bits */
378
enum NEORV32_UART_DATA_enum {
379
  UART_DATA_LSB   =  0, /**< UART receive/transmit data register(0)  (r/w): Receive/transmit data LSB (bit 0) */
380
  UART_DATA_MSB   =  7, /**< UART receive/transmit data register(7)  (r/w): Receive/transmit data MSB (bit 7) */
381
  UART_DATA_AVAIL = 31  /**< UART receive/transmit data register(31) (r/-): RX data available when set */
382
};
383
/**@}*/
384
 
385
 
386
/**********************************************************************//**
387 10 zero_gravi
 * @name IO Device: Serial Peripheral Interface Controller (SPI)
388 2 zero_gravi
 **************************************************************************/
389
/**@{*/
390
/** SPI control register (r/w) */
391 6 zero_gravi
#define SPI_CT  (*(IO_REG32 0xFFFFFFA8UL))
392 2 zero_gravi
/** SPI receive/transmit data register (r/w) */
393 6 zero_gravi
#define SPI_DATA (*(IO_REG32 0xFFFFFFACUL))
394 2 zero_gravi
 
395
/** SPI control register bits */
396
enum NEORV32_SPI_CT_enum {
397
  SPI_CT_CS0    =  0, /**< UART control register(0) (r/w): Direct chip select line 0 (output is low when set) */
398
  SPI_CT_CS1    =  1, /**< UART control register(1) (r/w): Direct chip select line 1 (output is low when set) */
399
  SPI_CT_CS2    =  2, /**< UART control register(2) (r/w): Direct chip select line 2 (output is low when set) */
400
  SPI_CT_CS3    =  3, /**< UART control register(3) (r/w): Direct chip select line 3 (output is low when set) */
401
  SPI_CT_CS4    =  4, /**< UART control register(4) (r/w): Direct chip select line 4 (output is low when set) */
402
  SPI_CT_CS5    =  5, /**< UART control register(5) (r/w): Direct chip select line 5 (output is low when set) */
403
  SPI_CT_CS6    =  6, /**< UART control register(6) (r/w): Direct chip select line 6 (output is low when set) */
404
  SPI_CT_CS7    =  7, /**< UART control register(7) (r/w): Direct chip select line 7 (output is low when set) */
405
 
406
  SPI_CT_EN     =  8, /**< UART control register(8) (r/w): SPI unit enable */
407
  SPI_CT_CPHA   =  9, /**< UART control register(9) (r/w): Clock polarity (idle polarity) */
408
  SPI_CT_PRSC0  = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */
409
  SPI_CT_PRSC1  = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */
410
  SPI_CT_PRSC2  = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */
411
  SPI_CT_DIR    = 13, /**< UART control register(13) (r/w): Shift direction (0: MSB first, 1: LSB first) */
412
  SPI_CT_SIZE0  = 14, /**< UART control register(14) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
413
  SPI_CT_SIZE1  = 15, /**< UART control register(15) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
414
 
415
  SPI_CT_IRQ_EN = 16, /**< UART control register(16) (r/w): Transfer done interrupt enable */
416
 
417
  SPI_CT_BUSY   = 31  /**< UART control register(31) (r/-): SPI busy flag */
418
};
419
/**@}*/
420
 
421
 
422
/**********************************************************************//**
423 10 zero_gravi
 * @name IO Device: Two-Wire Interface Controller (TWI)
424 2 zero_gravi
 **************************************************************************/
425
/**@{*/
426
/** TWI control register (r/w) */
427 6 zero_gravi
#define TWI_CT   (*(IO_REG32 0xFFFFFFB0UL))
428 2 zero_gravi
/** TWI receive/transmit data register (r/w) */
429 6 zero_gravi
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4UL))
430 2 zero_gravi
 
431
/** TWI control register bits */
432
enum NEORV32_TWI_CT_enum {
433
  TWI_CT_EN     =  0, /**< TWI control register(0) (r/w): TWI enable */
434
  TWI_CT_START  =  1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
435
  TWI_CT_STOP   =  2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
436
  TWI_CT_IRQ_EN =  3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
437
  TWI_CT_PRSC0  =  4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
438
  TWI_CT_PRSC1  =  5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
439
  TWI_CT_PRSC2  =  6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
440 10 zero_gravi
  TWI_CT_MACK   =  7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */
441 2 zero_gravi
 
442
  TWI_CT_ACK    = 30, /**< TWI control register(30) (r/-): ACK received when set */
443
  TWI_CT_BUSY   = 31  /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
444
};
445
 
446
/** WTD receive/transmit data register bits */
447
enum NEORV32_TWI_DATA_enum {
448
  TWI_DATA_LSB = 0, /**< TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB */
449
  TWI_DATA_MSB = 7  /**< TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB */
450
};
451
/**@}*/
452
 
453
 
454
/**********************************************************************//**
455
 * @name IO Device: Pulse Width Modulation Controller (PWM)
456
 **************************************************************************/
457
/**@{*/
458
/** PWM control register (r/w) */
459 6 zero_gravi
#define PWM_CT   (*(IO_REG32 0xFFFFFFB8UL)) // r/w: control register
460 2 zero_gravi
/** PWM duty cycle register (4-channels) (r/w) */
461 6 zero_gravi
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBCUL)) // r/w: duty cycle channel 1 and 0
462 2 zero_gravi
 
463
/** PWM control register bits */
464
enum NEORV32_PWM_CT_enum {
465
  PWM_CT_EN    =  0, /**< PWM control register(0) (r/w): PWM controller enable */
466
  PWM_CT_PRSC0 =  1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
467
  PWM_CT_PRSC1 =  2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
468
  PWM_CT_PRSC2 =  3  /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
469
};
470
 
471
/**PWM duty cycle register bits */
472
enum NEORV32_PWM_DUTY_enum {
473
  PWM_DUTY_CH0_LSB =  0, /**< PWM duty cycle register(0)  (r/w): Channel 0 duty cycle (8-bit) LSB */
474
  PWM_DUTY_CH0_MSB =  7, /**< PWM duty cycle register(7)  (r/w): Channel 0 duty cycle (8-bit) MSB */
475
  PWM_DUTY_CH1_LSB =  8, /**< PWM duty cycle register(8)  (r/w): Channel 1 duty cycle (8-bit) LSB */
476
  PWM_DUTY_CH1_MSB = 15, /**< PWM duty cycle register(15) (r/w): Channel 1 duty cycle (8-bit) MSB */
477
  PWM_DUTY_CH2_LSB = 16, /**< PWM duty cycle register(16) (r/w): Channel 2 duty cycle (8-bit) LSB */
478
  PWM_DUTY_CH2_MSB = 23, /**< PWM duty cycle register(23) (r/w): Channel 2 duty cycle (8-bit) MSB */
479
  PWM_DUTY_CH3_LSB = 24, /**< PWM duty cycle register(24) (r/w): Channel 3 duty cycle (8-bit) LSB */
480
  PWM_DUTY_CH3_MSB = 31  /**< PWM duty cycle register(31) (r/w): Channel 3 duty cycle (8-bit) MSB */
481
};
482
/**@}*/
483
 
484
 
485
/**********************************************************************//**
486
 * @name IO Device: True Random Number Generator (TRNG)
487
 **************************************************************************/
488
/**@{*/
489
/** TRNG control register (r/w) */
490 6 zero_gravi
#define TRNG_CT   (*(IO_REG32 0xFFFFFFC0UL))
491 2 zero_gravi
/** TRNG data register (r/-) */
492 6 zero_gravi
#define TRNG_DATA (*(IO_ROM32 0xFFFFFFC4UL))
493 2 zero_gravi
 
494
/** TRNG control register bits */
495
enum NEORV32_TRNG_CT_enum {
496
  TRNG_CT_TAP_LSB =  0, /**< TRNG control register(0)  (r/w): TAP mask (16-bit) LSB */
497
  TRNG_CT_TAP_MSB = 15, /**< TRNG control register(15) (r/w): TAP mask (16-bit) MSB */
498
  TRNG_CT_EN      = 31  /**< TRNG control register(31) (r/w): TRNG enable */
499
};
500
 
501
/** WTD data register bits */
502
enum NEORV32_TRNG_DUTY_enum {
503
  TRNG_DATA_LSB   =  0, /**< TRNG data register(0)  (r/-): Random data (16-bit) LSB */
504
  TRNG_DATA_MSB   = 15, /**< TRNG data register(15) (r/-): Random data (16-bit) MSB */
505
  TRNG_DATA_VALID = 31  /**< TRNG data register(31) (r/-): Random data output valid */
506
};
507
/**@}*/
508
 
509
 
510 3 zero_gravi
/**********************************************************************//**
511
 * @name IO Device: Dummy Device (DEVNULL)
512
 **************************************************************************/
513
/**@{*/
514 6 zero_gravi
/** DEVNULL data register (r/w) */
515
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFCUL))
516 3 zero_gravi
/**@}*/
517
 
518
 
519 2 zero_gravi
// ----------------------------------------------------------------------------
520
// Include all IO driver headers
521
// ----------------------------------------------------------------------------
522
// cpu core
523
#include "neorv32_cpu.h"
524
 
525
// neorv32 runtime environment
526
#include "neorv32_rte.h"
527
 
528
// io/peripheral devices
529
#include "neorv32_clic.h"
530
#include "neorv32_gpio.h"
531
#include "neorv32_mtime.h"
532
#include "neorv32_pwm.h"
533
#include "neorv32_spi.h"
534
#include "neorv32_trng.h"
535
#include "neorv32_twi.h"
536
#include "neorv32_uart.h"
537
#include "neorv32_wdt.h"
538
 
539
#endif // neorv32_h

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