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// #################################################################################################
2 
// # << NEORV32: neorv32.h - Main Core Library File >>                                             #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License                                                                          #
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// #                                                                                               #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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// #                                                                                               #
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// # Redistribution and use in source and binary forms, with or without modification, are          #
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// # permitted provided that the following conditions are met:                                     #
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// #                                                                                               #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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// #    conditions and the following disclaimer.                                                   #
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// #                                                                                               #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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// #    conditions and the following disclaimer in the documentation and/or other materials        #
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// #    provided with the distribution.                                                            #
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// #                                                                                               #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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// #    endorse or promote products derived from this software without specific prior written      #
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// #    permission.                                                                                #
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// #                                                                                               #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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// #################################################################################################
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35 
 
36 
/**********************************************************************//**
37 
 * @file neorv32.h
38 
 * @author Stephan Nolting
39 
 * @date 30 May 2020
40 
 *
41 
 * @brief Main NEORV32 core library file.
42 
 *
43 
 * @details This file defines the addresses of the IO devices and their according
44 
 * registers and register bits as well as the available CPU CSRs and flags.
45 
 **************************************************************************/
46 
 
47 
#ifndef neorv32_h
48 
#define neorv32_h
49 
 
50 
// Standard libraries
51 
#include <stdint.h>
52 
#include <stdlib.h>
53 
#include <string.h>
54 
#include <stdbool.h>
55 
#include <inttypes.h>
56 
#include <limits.h>
57 
 
58 
 
59 
/**********************************************************************//**
60 
 * Available CPU Control and Status Registers (CSRs)
61 
 **************************************************************************/
62 
enum NEORV32_CPU_CSRS_enum {
63 
  CSR_MSTATUS     = 0x300, /**< 0x300 - mstatus  (r/w): Machine status register */
64 
  CSR_MISA        = 0x301, /**< 0x301 - misa     (r/-): CPU ISA and extensions */
65 
  CSR_MIE         = 0x304, /**< 0x304 - mie      (r/w): Machine interrupt-enable register */
66 
  CSR_MTVEC       = 0x305, /**< 0x305 - mtvec    (r/w): Machine trap-handler base address (for ALL traps) */
67 
 
68 
  CSR_MSCRATCH    = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
69 
  CSR_MEPC        = 0x341, /**< 0x341 - mepc     (r/w): Machine exception program counter */
70 
  CSR_MCAUSE      = 0x342, /**< 0x342 - mcause   (r/-): Machine trap cause */
71 
  CSR_MTVAL       = 0x343, /**< 0x343 - mtval    (r/-): Machine bad address or instruction */
72 
  CSR_MIP         = 0x344, /**< 0x344 - mip      (r/w): Machine interrupt pending register */
73 
  CSR_MTINST      = 0x34a, /**< 0x34a - mtinst   (r/-): Machine trap instruction (transformed) */
74 
 
75 
  CSR_MCYCLE      = 0xb00, /**< 0xb00 - mcycle    (r/-): Machine cycle counter low word */
76 
  CSR_MINSTRET    = 0xb02, /**< 0xb02 - minstret  (r/-): Machine instructions-retired counter low word */
77 
  CSR_MCYCLEH     = 0xb80, /**< 0xb80 - mcycleh   (r/-): Machine cycle counter high word */
78 
  CSR_MINSTRETH   = 0xb82, /**< 0xb82 - minstreth (r/-): Machine instructions-retired counter high word */
79 
 
80 
  CSR_CYCLE       = 0xc00, /**< 0xc00 - cycle    (r/-): Cycle counter low word */
81 
  CSR_TIME        = 0xc01, /**< 0xc01 - time     (r/-): Timer low word*/
82 
  CSR_INSTRET     = 0xc02, /**< 0xc02 - instret  (r/-): Instructions-retired counter low word */
83 
 
84 
  CSR_CYCLEH      = 0xc80, /**< 0xc80 - cycleh   (r/-): Cycle counter high word */
85 
  CSR_TIMEH       = 0xc81, /**< 0xc81 - timeh    (r/-): Timer high word*/
86 
  CSR_INSTRETH    = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word */
87 
 
88 
  CSR_MIMPID      = 0xf13, /**< 0xf13 - mimpid  (r/-): Implementation ID/version */
89 
  CSR_MHARTID     = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (via HART_ID generic) */
90 
 
91 
  CSR_MFEATURES   = 0xfc0, /**< 0xfc0 - CUSTOM (r/-): Implemented processor devices/features (via IO_x_USE generics) */
92 
  CSR_MCLOCK      = 0xfc1, /**< 0xfc1 - CUSTOM (r/-): Processor primary clock spedd in Hz (via CLOCK_FREQUENCY generic)*/
93 
  CSR_MISPACEBASE = 0xfc4, /**< 0xfc4 - CUSTOM (r/-): Base address of instruction memory space (via MEM_ISPACE_BASE generic) */
94 
  CSR_MDSPACEBASE = 0xfc5, /**< 0xfc5 - CUSTOM (r/-): Base address of data memory space (via MEM_DSPACE_BASE generic) */
95 
  CSR_MISPACESIZE = 0xfc6, /**< 0xfc6 - CUSTOM (r/-): Total size of instruction memory space in byte (via MEM_ISPACE_SIZE generic) */
96 
  CSR_MDSPACESIZE = 0xfc7  /**< 0xfc7 - CUSTOM (r/-): Total size of data memory space in byte (via MEM_DSPACE_SIZE generic) */
97 
};
98 
 
99 
 
100 
/**********************************************************************//**
101 
 * CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
102 
 **************************************************************************/
103 
enum NEORV32_CPU_MSTATUS_enum {
104 
  CPU_MSTATUS_MIE  = 3, /**< CPU mstatus CSR (3): Machine interrupt enable bit (r/w) */
105 
  CPU_MSTATUS_MPIE = 7  /**< CPU mstatus CSR (7): Machine previous interrupt enable bit (r/w) */
106 
};
107 
 
108 
 
109 
/**********************************************************************//**
110 
 * CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.)
111 
 **************************************************************************/
112 
enum NEORV32_CPU_MIE_enum {
113 
  CPU_MIE_MSIE  =  3, /**< CPU mie CSR (3): Machine software interrupt enable bit (r/w) */
114 
  CPU_MIE_MTIE  =  7, /**< CPU mie CSR (7): Machine timer interrupt (MTIME) enable bit (r/w) */
115 
  CPU_MIE_MEIE  = 11  /**< CPU mie CSR (11): Machine external interrupt (via CLIC) enable bit (r/w) */
116 
};
117 
 
118 
 
119 
/**********************************************************************//**
120 
 * CPU <b>mip</b> CSR (r/w): Machine interrupt pending (RISC-V spec.)
121 
 **************************************************************************/
122 
enum NEORV32_CPU_MIP_enum {
123 
  CPU_MIP_MSIP  =  3, /**< CPU mip CSR (3): Machine software interrupt pending (r/w), can be triggered when set */
124 
  CPU_MIP_MTIP  =  7, /**< CPU mip CSR (7): Machine timer interrupt (MTIME) pending (r/-) */
125 
  CPU_MIP_MEIP  = 11  /**< CPU mip CSR (11): Machine external interrupt (via CLIC) pending (r/-) */
126 
};
127 
 
128 
 
129 
/**********************************************************************//**
130 
 * CPU <b>mfeatures</b> CSR (r/-): Implemented processor devices/features (CUSTOM)
131 
 **************************************************************************/
132 
 enum NEORV32_CPU_MFEATURES_enum {
133 
  CPU_MFEATURES_BOOTLOADER       =  0, /**< CPU mfeatures CSR (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
134 
  CPU_MFEATURES_MEM_EXT          =  1, /**< CPU mfeatures CSR (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
135 
  CPU_MFEATURES_MEM_INT_IMEM     =  2, /**< CPU mfeatures CSR (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
136 
  CPU_MFEATURES_MEM_INT_IMEM_ROM =  3, /**< CPU mfeatures CSR (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
137 
  CPU_MFEATURES_MEM_INT_DMEM     =  4, /**< CPU mfeatures CSR (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
138 
 
139 
  CPU_MFEATURES_IO_GPIO          = 16, /**< CPU mfeatures CSR (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
140 
  CPU_MFEATURES_IO_MTIME         = 17, /**< CPU mfeatures CSR (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
141 
  CPU_MFEATURES_IO_UART          = 18, /**< CPU mfeatures CSR (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
142 
  CPU_MFEATURES_IO_SPI           = 19, /**< CPU mfeatures CSR (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
143 
  CPU_MFEATURES_IO_TWI           = 20, /**< CPU mfeatures CSR (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */
144 
  CPU_MFEATURES_IO_PWM           = 21, /**< CPU mfeatures CSR (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */
145 
  CPU_MFEATURES_IO_WDT           = 22, /**< CPU mfeatures CSR (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */
146 
  CPU_MFEATURES_IO_CLIC          = 23, /**< CPU mfeatures CSR (23) (r/-): Core-local interrupt controller implemented when 1 (via IO_CLIC_USE generic) */
147 
  CPU_MFEATURES_IO_TRNG          = 24  /**< CPU mfeatures CSR (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
148 
};
149 
 
150 
 
151 
/**********************************************************************//**
152 
 * Exception IDs.
153 
 **************************************************************************/
154 
enum NEORV32_EXCEPTION_IDS_enum {
155 
  EXCID_I_MISALIGNED =  0, /**< 0: Instruction address misaligned */
156 
  EXCID_I_ACCESS     =  1, /**< 1: Instruction (bus) access fault */
157 
  EXCID_I_ILLEGAL    =  2, /**< 2: Illegal instruction */
158 
  EXCID_BREAKPOINT   =  3, /**< 3: Breakpoint (EBREAK instruction) */
159 
  EXCID_L_MISALIGNED =  4, /**< 4: Load address misaligned */
160 
  EXCID_L_ACCESS     =  5, /**< 5: Load (bus) access fault */
161 
  EXCID_S_MISALIGNED =  6, /**< 6: Store address misaligned */
162 
  EXCID_S_ACCESS     =  7, /**< 7: Store (bus) access fault */
163 
  EXCID_MENV_CALL    = 11, /**< 11: Environment call from machine mode (ECALL instruction) */
164 
  EXCID_MSI          = 19, /**< 16 + 3: Machine software interrupt */
165 
  EXCID_MTI          = 23, /**< 16 + 7: Machine timer interrupt (via MTIME) */
166 
  EXCID_MEI          = 27  /**< 16 + 11: Machine external interrupt (via CLIC) */
167 
};
168 
 
169 
 
170 
/**********************************************************************//**
171 
 * Processor clock prescalers
172 
 **************************************************************************/
173 
enum NEORV32_CLOCK_PRSC_enum {
174 
  CLK_PRSC_2    =  0, /**< CPU_CLK / 2 */
175 
  CLK_PRSC_4    =  1, /**< CPU_CLK / 4 */
176 
  CLK_PRSC_8    =  2, /**< CPU_CLK / 8 */
177 
  CLK_PRSC_64   =  3, /**< CPU_CLK / 64 */
178 
  CLK_PRSC_128  =  4, /**< CPU_CLK / 128 */
179 
  CLK_PRSC_1024 =  5, /**< CPU_CLK / 1024 */
180 
  CLK_PRSC_2048 =  6, /**< CPU_CLK / 2048 */
181 
  CLK_PRSC_4096 =  7  /**< CPU_CLK / 4096 */
182 
};
183 
 
184 
 
185 
/**********************************************************************//**
186 
 * @name Helper macros for easy memory-mapped register access
187 
 **************************************************************************/
188 
/**@{*/
189 
/** memory-mapped byte (8-bit) read/write register */
190 
#define IO_REG8  (volatile uint8_t*)
191 
/** memory-mapped half-word (16-bit) read/write register */
192 
#define IO_REG16 (volatile uint16_t*)
193 
/** memory-mapped word (32-bit) read/write register */
194 
#define IO_REG32 (volatile uint32_t*)
195 
/** memory-mapped double-word (64-bit) read/write register */
196 
#define IO_REG64 (volatile uint64_t*)
197 
/** memory-mapped byte (8-bit) read-only register */
198 
#define IO_ROM8  (const volatile uint8_t*)
199 
/** memory-mapped half-word (16-bit) read-only register */
200 
#define IO_ROM16 (const volatile uint16_t*)
201 
/** memory-mapped word (32-bit) read-only register */
202 
#define IO_ROM32 (const volatile uint32_t*)
203 
/** memory-mapped double-word (64-bit) read-only register */
204 
#define IO_ROM64 (const volatile uint64_t*)
205 
/**@}*/
206 
 
207 
 
208 
/**********************************************************************//**
209 
 * @name Address space sections
210 
 **************************************************************************/
211 
/**@{*/
212 
/** instruction memory base address (r/w/x) */
213 
#define INSTR_MEM_BASE_ADDR 0x00000000
214 
/** data memory base address (r/w/x) */
215 
#define DATA_MEM_BASE_ADDR 0x80000000
216 
/** bootloader memory base address (r/-/x) */
217 
#define BOOTLOADER_BASE_ADDRESS 0xFFFF0000
218 
/** peripheral/IO devices memory base address (r/w/x) */
219 
#define IO_BASE_ADDRESS 0xFFFFFF80
220 
/**@}*/
221 
 
222 
 
223 
/**********************************************************************//**
224 
 * @name IO Device: General Purpose Input/Output Port Unit (GPIO)
225 
 **************************************************************************/
226 
/**@{*/
227 
/** GPIO parallel input port (r/-) */
228 
#define GPIO_INPUT  (*(IO_ROM32 0xFFFFFF80))
229 
/** GPIO parallel output port (r/w) */
230 
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84))
231 
/**@}*/
232 
 
233 
 
234 
/**********************************************************************//**
235 
 * @name IO Device: Core Local Interrupts Controller (CLIC)
236 
 **************************************************************************/
237 
/**@{*/
238 
/** CLIC control register (r/w) */
239 
#define CLIC_CT (*(IO_REG32 0xFFFFFF88))
240 
 
241 
/** CLIC control register bits */
242 
enum NEORV32_CLIC_CT_enum {
243 
  CLIC_CT_SRC0        =  0, /**< CLIC control register(0) (r/-): IRQ source bit 0 */
244 
  CLIC_CT_SRC1        =  1, /**< CLIC control register(1) (r/-): IRQ source bit 1 */
245 
  CLIC_CT_SRC2        =  2, /**< CLIC control register(2) (r/-): IRQ source bit 2 */
246 
  CLIC_CT_ACK         =  3, /**< CLIC control register(3) (-/w): Acknowledge current IRQ when set, auto-clears when set */
247 
  CLIC_CT_EN          =  4, /**< CLIC control register(4) (r/w): Unit enable */
248 
 
249 
  CLIC_CT_IRQ0_EN     =  8, /**< CLIC control register(8)  (r/w): Enable IRQ channel 0 */
250 
  CLIC_CT_IRQ1_EN     =  9, /**< CLIC control register(9)  (r/w): Enable IRQ channel 1 */
251 
  CLIC_CT_IRQ2_EN     = 10, /**< CLIC control register(10) (r/w): Enable IRQ channel 2 */
252 
  CLIC_CT_IRQ3_EN     = 11, /**< CLIC control register(11) (r/w): Enable IRQ channel 3 */
253 
  CLIC_CT_IRQ4_EN     = 12, /**< CLIC control register(12) (r/w): Enable IRQ channel 4 */
254 
  CLIC_CT_IRQ5_EN     = 13, /**< CLIC control register(13) (r/w): Enable IRQ channel 5 */
255 
  CLIC_CT_IRQ6_EN     = 14, /**< CLIC control register(14) (r/w): Enable IRQ channel 6 */
256 
  CLIC_CT_IRQ7_EN     = 15, /**< CLIC control register(15) (r/w): Enable IRQ channel 7 */
257 
 
258 
  CLIC_CT_SW_IRQ_SRC0 = 16, /**< CLIC control register(16) (-/w): SW IRQ trigger, IRQ select bit 0, auto-clears when set */
259 
  CLIC_CT_SW_IRQ_SRC1 = 17, /**< CLIC control register(17) (-/w): SW IRQ trigger, IRQ select bit 1, auto-clears when set */
260 
  CLIC_CT_SW_IRQ_SRC2 = 18, /**< CLIC control register(18) (-/w): SW IRQ trigger, IRQ select bit 2, auto-clears when set */
261 
  CLIC_CT_SW_IRQ_EN   = 19  /**< CLIC control register(19) (-/w): SW IRQ trigger enable, auto-clears when set */
262 
};
263 
/**@}*/
264 
 
265 
 
266 
/**********************************************************************//**
267 
 * Core-local interrupt controller IRQ channel
268 
 **************************************************************************/
269 
enum NEORV32_CLIC_CHANNELS_enum {
270 
  CLIC_CH_WDT   = 0, /**< CLIC channel 0: Watchdog timer overflow interrupt */
271 
  CLIC_CH_RES   = 1, /**< CLIC channel 1: reserved */
272 
  CLIC_CH_GPIO  = 2, /**< CLIC channel 2: GPIO pin-change interrupt */
273 
  CLIC_CH_UART  = 3, /**< CLIC channel 3: UART RX available or TX done interrupt */
274 
  CLIC_CH_SPI   = 4, /**< CLIC channel 4: SPI transmission done interrupt */
275 
  CLIC_CH_TWI   = 5, /**< CLIC channel 5: TWI transmission done interrupt */
276 
  CLIC_CH_EXT0  = 6, /**< CLIC channel 6: Processor-external interrupt request 0 */
277 
  CLIC_CH_EXT1  = 7  /**< CLIC channel 7: Processor-external interrupt request 1 */
278 
};
279 
 
280 
 
281 
/**********************************************************************//**
282 
 * @name IO Device: Watchdog Timer (WDT)
283 
 **************************************************************************/
284 
/**@{*/
285 
/** Watchdog control register (r/w) */
286 
#define WDT_CT (*(IO_REG32 0xFFFFFF8C))
287 
 
288 
/** WTD control register bits */
289 
enum NEORV32_WDT_CT_enum {
290 
  WDT_CT_CLK_SEL0     =  0, /**< WDT control register(0) (r/w): Clock prescaler select bit 0 */
291 
  WDT_CT_CLK_SEL1     =  1, /**< WDT control register(1) (r/w): Clock prescaler select bit 1 */
292 
  WDT_CT_CLK_SEL2     =  2, /**< WDT control register(2) (r/w): Clock prescaler select bit 2 */
293 
  WDT_CT_EN           =  3, /**< WDT control register(3) (r/w): Watchdog enable */
294 
  WDT_CT_MODE         =  4, /**< WDT control register(4) (r/w): Watchdog mode; when 0: timeout causes interrupt; when 1: timeout causes processor reset */
295 
  WDT_CT_CAUSE        =  5, /**< WDT control register(5) (r/-): Last action (reset/IRQ) cause (0: external reset, 1: watchdog timeout) */
296 
  WDT_CT_PWFAIL       =  6, /**< WDT control register(6) (r/-): Last Watchdog action (reset/IRQ) caused by wrong password when 1 */
297 
 
298 
  WDT_CT_PASSWORD_LSB =  8, /**< WDT control register(8)  (-/w): First bit / position begin for watchdog access password */
299 
  WDT_CT_PASSWORD_MSB = 15  /**< WDT control register(15) (-/w): Last bit / position end for watchdog access password */
300 
};
301 
 
302 
/** Watchdog access passwort, must be set in WDT_CT bits 15:8 for every control register access */
303 
#define WDT_PASSWORD 0x47
304 
/**@}*/
305 
 
306 
 
307 
/**********************************************************************//**
308 
 * @name IO Device: Machine System Timer (MTIME)
309 
 **************************************************************************/
310 
/**@{*/
311 
/** MTIME (time register) low word (r/w) */
312 
#define MTIME_LO     (*(IO_REG32 0xFFFFFF90))
313 
/** MTIME (time register) high word (r/w) */
314 
#define MTIME_HI     (*(IO_REG32 0xFFFFFF94))
315 
/** MTIMECMP (time compare register) low word (r/w) */
316 
#define MTIMECMP_LO  (*(IO_REG32 0xFFFFFF98))
317 
/** MTIMECMP (time register) high word (r/w) */
318 
#define MTIMECMP_HI  (*(IO_REG32 0xFFFFFF9C))
319 
 
320 
/** MTIME (time register) 64-bit access (r/w) */
321 
#define MTIME        (*(IO_REG64 (&MTIME_LO)))
322 
/** MTIMECMP (time compare register) low word (r/w) */
323 
#define MTIMECMP     (*(IO_REG64 (&MTIMECMP_LO)))
324 
/**@}*/
325 
 
326 
 
327 
/**********************************************************************//**
328 
 * @name IO Device: Universal Asynchronous Receiver and Transmitter (UART)
329 
 **************************************************************************/
330 
/**@{*/
331 
/** UART control register (r/w) */
332 
#define UART_CT  (*(IO_REG32 0xFFFFFFA0))
333 
/** UART receive/transmit data register (r/w) */
334 
#define UART_DATA (*(IO_REG32 0xFFFFFFA4))
335 
 
336 
/** UART control register bits */
337 
enum NEORV32_UART_CT_enum {
338 
  UART_CT_BAUD00  =  0, /**< UART control register(0)  (r/w): BAUD rate config value lsb (12-bi, bit 0) */
339 
  UART_CT_BAUD01  =  1, /**< UART control register(1)  (r/w): BAUD rate config value (12-bi, bit 1) */
340 
  UART_CT_BAUD02  =  2, /**< UART control register(2)  (r/w): BAUD rate config value (12-bi, bit 2) */
341 
  UART_CT_BAUD03  =  3, /**< UART control register(3)  (r/w): BAUD rate config value (12-bi, bit 3) */
342 
  UART_CT_BAUD04  =  4, /**< UART control register(4)  (r/w): BAUD rate config value (12-bi, bit 4) */
343 
  UART_CT_BAUD05  =  5, /**< UART control register(5)  (r/w): BAUD rate config value (12-bi, bit 4) */
344 
  UART_CT_BAUD06  =  6, /**< UART control register(6)  (r/w): BAUD rate config value (12-bi, bit 5) */
345 
  UART_CT_BAUD07  =  7, /**< UART control register(7)  (r/w): BAUD rate config value (12-bi, bit 6) */
346 
  UART_CT_BAUD08  =  8, /**< UART control register(8)  (r/w): BAUD rate config value (12-bi, bit 7) */
347 
  UART_CT_BAUD09  =  9, /**< UART control register(9)  (r/w): BAUD rate config value (12-bi, bit 8) */
348 
  UART_CT_BAUD10  = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bi, bit 9) */
349 
  UART_CT_BAUD11  = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bi, bit 0)*/
350 
 
351 
  UART_CT_PRSC0   = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
352 
  UART_CT_PRSC1   = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
353 
  UART_CT_PRSC2   = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
354 
  UART_CT_RXOR    = 27, /**< UART control register(27) (r/-): RX data overrun when set */
355 
  UART_CT_EN      = 28, /**< UART control register(28) (r/w): UART global enable */
356 
  UART_CT_RX_IRQ  = 29, /**< UART control register(29) (r/w): Activate interrupt on RX done */
357 
  UART_CT_TX_IRQ  = 30, /**< UART control register(30) (r/w): Activate interrupt on TX done */
358 
  UART_CT_TX_BUSY = 31  /**< UART control register(31) (r/-): Transmitter is busy when set */
359 
};
360 
 
361 
/** UART receive/transmit data register bits */
362 
enum NEORV32_UART_DATA_enum {
363 
  UART_DATA_LSB   =  0, /**< UART receive/transmit data register(0)  (r/w): Receive/transmit data LSB (bit 0) */
364 
  UART_DATA_MSB   =  7, /**< UART receive/transmit data register(7)  (r/w): Receive/transmit data MSB (bit 7) */
365 
  UART_DATA_AVAIL = 31  /**< UART receive/transmit data register(31) (r/-): RX data available when set */
366 
};
367 
/**@}*/
368 
 
369 
 
370 
/**********************************************************************//**
371 
 * @name IO Device: Serial Peripheral Interface Master (SPI)
372 
 **************************************************************************/
373 
/**@{*/
374 
/** SPI control register (r/w) */
375 
#define SPI_CT  (*(IO_REG32 0xFFFFFFA8))
376 
/** SPI receive/transmit data register (r/w) */
377 
#define SPI_DATA (*(IO_REG32 0xFFFFFFAC))
378 
 
379 
/** SPI control register bits */
380 
enum NEORV32_SPI_CT_enum {
381 
  SPI_CT_CS0    =  0, /**< UART control register(0) (r/w): Direct chip select line 0 (output is low when set) */
382 
  SPI_CT_CS1    =  1, /**< UART control register(1) (r/w): Direct chip select line 1 (output is low when set) */
383 
  SPI_CT_CS2    =  2, /**< UART control register(2) (r/w): Direct chip select line 2 (output is low when set) */
384 
  SPI_CT_CS3    =  3, /**< UART control register(3) (r/w): Direct chip select line 3 (output is low when set) */
385 
  SPI_CT_CS4    =  4, /**< UART control register(4) (r/w): Direct chip select line 4 (output is low when set) */
386 
  SPI_CT_CS5    =  5, /**< UART control register(5) (r/w): Direct chip select line 5 (output is low when set) */
387 
  SPI_CT_CS6    =  6, /**< UART control register(6) (r/w): Direct chip select line 6 (output is low when set) */
388 
  SPI_CT_CS7    =  7, /**< UART control register(7) (r/w): Direct chip select line 7 (output is low when set) */
389 
 
390 
  SPI_CT_EN     =  8, /**< UART control register(8) (r/w): SPI unit enable */
391 
  SPI_CT_CPHA   =  9, /**< UART control register(9) (r/w): Clock polarity (idle polarity) */
392 
  SPI_CT_PRSC0  = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */
393 
  SPI_CT_PRSC1  = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */
394 
  SPI_CT_PRSC2  = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */
395 
  SPI_CT_DIR    = 13, /**< UART control register(13) (r/w): Shift direction (0: MSB first, 1: LSB first) */
396 
  SPI_CT_SIZE0  = 14, /**< UART control register(14) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
397 
  SPI_CT_SIZE1  = 15, /**< UART control register(15) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
398 
 
399 
  SPI_CT_IRQ_EN = 16, /**< UART control register(16) (r/w): Transfer done interrupt enable */
400 
 
401 
  SPI_CT_BUSY   = 31  /**< UART control register(31) (r/-): SPI busy flag */
402 
};
403 
/**@}*/
404 
 
405 
 
406 
/**********************************************************************//**
407 
 * @name IO Device: Two-Wire Interface Master (TWI)
408 
 **************************************************************************/
409 
/**@{*/
410 
/** TWI control register (r/w) */
411 
#define TWI_CT   (*(IO_REG32 0xFFFFFFB0))
412 
/** TWI receive/transmit data register (r/w) */
413 
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4))
414 
 
415 
/** TWI control register bits */
416 
enum NEORV32_TWI_CT_enum {
417 
  TWI_CT_EN     =  0, /**< TWI control register(0) (r/w): TWI enable */
418 
  TWI_CT_START  =  1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
419 
  TWI_CT_STOP   =  2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
420 
  TWI_CT_IRQ_EN =  3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
421 
  TWI_CT_PRSC0  =  4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
422 
  TWI_CT_PRSC1  =  5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
423 
  TWI_CT_PRSC2  =  6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
424 
  TWI_CT_MACK   =  7, /**< TWI control register(7) (r/w): Generate master ACK for each transmission */
425 
 
426 
  TWI_CT_ACK    = 30, /**< TWI control register(30) (r/-): ACK received when set */
427 
  TWI_CT_BUSY   = 31  /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
428 
};
429 
 
430 
/** WTD receive/transmit data register bits */
431 
enum NEORV32_TWI_DATA_enum {
432 
  TWI_DATA_LSB = 0, /**< TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB */
433 
  TWI_DATA_MSB = 7  /**< TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB */
434 
};
435 
/**@}*/
436 
 
437 
 
438 
/**********************************************************************//**
439 
 * @name IO Device: Pulse Width Modulation Controller (PWM)
440 
 **************************************************************************/
441 
/**@{*/
442 
/** PWM control register (r/w) */
443 
#define PWM_CT   (*(IO_REG32 0xFFFFFFB8)) // r/w: control register
444 
/** PWM duty cycle register (4-channels) (r/w) */
445 
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBC)) // r/w: duty cycle channel 1 and 0
446 
 
447 
/** PWM control register bits */
448 
enum NEORV32_PWM_CT_enum {
449 
  PWM_CT_EN    =  0, /**< PWM control register(0) (r/w): PWM controller enable */
450 
  PWM_CT_PRSC0 =  1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
451 
  PWM_CT_PRSC1 =  2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
452 
  PWM_CT_PRSC2 =  3  /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
453 
};
454 
 
455 
/**PWM duty cycle register bits */
456 
enum NEORV32_PWM_DUTY_enum {
457 
  PWM_DUTY_CH0_LSB =  0, /**< PWM duty cycle register(0)  (r/w): Channel 0 duty cycle (8-bit) LSB */
458 
  PWM_DUTY_CH0_MSB =  7, /**< PWM duty cycle register(7)  (r/w): Channel 0 duty cycle (8-bit) MSB */
459 
  PWM_DUTY_CH1_LSB =  8, /**< PWM duty cycle register(8)  (r/w): Channel 1 duty cycle (8-bit) LSB */
460 
  PWM_DUTY_CH1_MSB = 15, /**< PWM duty cycle register(15) (r/w): Channel 1 duty cycle (8-bit) MSB */
461 
  PWM_DUTY_CH2_LSB = 16, /**< PWM duty cycle register(16) (r/w): Channel 2 duty cycle (8-bit) LSB */
462 
  PWM_DUTY_CH2_MSB = 23, /**< PWM duty cycle register(23) (r/w): Channel 2 duty cycle (8-bit) MSB */
463 
  PWM_DUTY_CH3_LSB = 24, /**< PWM duty cycle register(24) (r/w): Channel 3 duty cycle (8-bit) LSB */
464 
  PWM_DUTY_CH3_MSB = 31  /**< PWM duty cycle register(31) (r/w): Channel 3 duty cycle (8-bit) MSB */
465 
};
466 
/**@}*/
467 
 
468 
 
469 
/**********************************************************************//**
470 
 * @name IO Device: True Random Number Generator (TRNG)
471 
 **************************************************************************/
472 
/**@{*/
473 
/** TRNG control register (r/w) */
474 
#define TRNG_CT   (*(IO_REG32 0xFFFFFFC0))
475 
/** TRNG data register (r/-) */
476 
#define TRNG_DATA (*(IO_ROM32 0xFFFFFFC4))
477 
 
478 
/** TRNG control register bits */
479 
enum NEORV32_TRNG_CT_enum {
480 
  TRNG_CT_TAP_LSB =  0, /**< TRNG control register(0)  (r/w): TAP mask (16-bit) LSB */
481 
  TRNG_CT_TAP_MSB = 15, /**< TRNG control register(15) (r/w): TAP mask (16-bit) MSB */
482 
  TRNG_CT_EN      = 31  /**< TRNG control register(31) (r/w): TRNG enable */
483 
};
484 
 
485 
/** WTD data register bits */
486 
enum NEORV32_TRNG_DUTY_enum {
487 
  TRNG_DATA_LSB   =  0, /**< TRNG data register(0)  (r/-): Random data (16-bit) LSB */
488 
  TRNG_DATA_MSB   = 15, /**< TRNG data register(15) (r/-): Random data (16-bit) MSB */
489 
  TRNG_DATA_VALID = 31  /**< TRNG data register(31) (r/-): Random data output valid */
490 
};
491 
/**@}*/
492 
 
493 
 
494 
// ----------------------------------------------------------------------------
495 
// Include all IO driver headers
496 
// ----------------------------------------------------------------------------
497 
// cpu core
498 
#include "neorv32_cpu.h"
499 
 
500 
// neorv32 runtime environment
501 
#include "neorv32_rte.h"
502 
 
503 
// io/peripheral devices
504 
#include "neorv32_clic.h"
505 
#include "neorv32_gpio.h"
506 
#include "neorv32_mtime.h"
507 
#include "neorv32_pwm.h"
508 
#include "neorv32_spi.h"
509 
#include "neorv32_trng.h"
510 
#include "neorv32_twi.h"
511 
#include "neorv32_uart.h"
512 
#include "neorv32_wdt.h"
513 
 
514 
#endif // neorv32_h

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