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1 2 zero_gravi 
// #################################################################################################
2 
// # << NEORV32: neorv32.h - Main Core Library File >>                                             #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License                                                                          #
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// #                                                                                               #
6 42 zero_gravi 
// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
// #                                                                                               #
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// # Redistribution and use in source and binary forms, with or without modification, are          #
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// # permitted provided that the following conditions are met:                                     #
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// #                                                                                               #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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// #    conditions and the following disclaimer.                                                   #
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// #                                                                                               #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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// #    conditions and the following disclaimer in the documentation and/or other materials        #
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// #    provided with the distribution.                                                            #
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// #                                                                                               #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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// #    endorse or promote products derived from this software without specific prior written      #
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// #    permission.                                                                                #
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// #                                                                                               #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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// #################################################################################################
34 
 
35 
 
36 
/**********************************************************************//**
37 
 * @file neorv32.h
38 
 * @author Stephan Nolting
39 
 *
40 20 zero_gravi 
 * @brief Main NEORV32 core library include file.
41 2 zero_gravi 
 **************************************************************************/
42 
 
43 
#ifndef neorv32_h
44 
#define neorv32_h
45 
 
46 
// Standard libraries
47 
#include <stdint.h>
48 
#include <inttypes.h>
49 
#include <limits.h>
50 
 
51 
 
52 
/**********************************************************************//**
53 
 * Available CPU Control and Status Registers (CSRs)
54 
 **************************************************************************/
55 42 zero_gravi 
enum NEORV32_CSR_enum {
56 
  CSR_MSTATUS        = 0x300, /**< 0x300 - mstatus    (r/w): Machine status register */
57 
  CSR_MISA           = 0x301, /**< 0x301 - misa       (r/-): CPU ISA and extensions (read-only in NEORV32) */
58 
  CSR_MIE            = 0x304, /**< 0x304 - mie        (r/w): Machine interrupt-enable register */
59 
  CSR_MTVEC          = 0x305, /**< 0x305 - mtvec      (r/w): Machine trap-handler base address (for ALL traps) */
60 
  CSR_MCOUNTEREN     = 0x306, /**< 0x305 - mcounteren (r/w): Machine counter enable register (controls access rights from U-mode) */
61 
  CSR_MSTATUSH       = 0x310, /**< 0x310 - mstatush   (r/-): Machine status register - high word */
62 2 zero_gravi 
 
63 42 zero_gravi 
  CSR_MCOUNTINHIBIT  = 0x320, /**< 0x320 - mcountinhibit (r/w): Machine counter-inhibit register */
64 2 zero_gravi 
 
65 42 zero_gravi 
  CSR_MHPMEVENT3     = 0x323, /**< 0x323 - mhpmevent3  (r/w): Machine hardware performance monitor event selector 3  */
66 
  CSR_MHPMEVENT4     = 0x324, /**< 0x324 - mhpmevent4  (r/w): Machine hardware performance monitor event selector 4  */
67 
  CSR_MHPMEVENT5     = 0x325, /**< 0x325 - mhpmevent5  (r/w): Machine hardware performance monitor event selector 5  */
68 
  CSR_MHPMEVENT6     = 0x326, /**< 0x326 - mhpmevent6  (r/w): Machine hardware performance monitor event selector 6  */
69 
  CSR_MHPMEVENT7     = 0x327, /**< 0x327 - mhpmevent7  (r/w): Machine hardware performance monitor event selector 7  */
70 
  CSR_MHPMEVENT8     = 0x328, /**< 0x328 - mhpmevent8  (r/w): Machine hardware performance monitor event selector 8  */
71 
  CSR_MHPMEVENT9     = 0x329, /**< 0x329 - mhpmevent9  (r/w): Machine hardware performance monitor event selector 9  */
72 
  CSR_MHPMEVENT10    = 0x32a, /**< 0x32a - mhpmevent10 (r/w): Machine hardware performance monitor event selector 10 */
73 
  CSR_MHPMEVENT11    = 0x32b, /**< 0x32b - mhpmevent11 (r/w): Machine hardware performance monitor event selector 11 */
74 
  CSR_MHPMEVENT12    = 0x32c, /**< 0x32c - mhpmevent12 (r/w): Machine hardware performance monitor event selector 12 */
75 
  CSR_MHPMEVENT13    = 0x32d, /**< 0x32d - mhpmevent13 (r/w): Machine hardware performance monitor event selector 13 */
76 
  CSR_MHPMEVENT14    = 0x32e, /**< 0x32e - mhpmevent14 (r/w): Machine hardware performance monitor event selector 14 */
77 
  CSR_MHPMEVENT15    = 0x32f, /**< 0x32f - mhpmevent15 (r/w): Machine hardware performance monitor event selector 15 */
78 
  CSR_MHPMEVENT16    = 0x330, /**< 0x330 - mhpmevent16 (r/w): Machine hardware performance monitor event selector 16 */
79 
  CSR_MHPMEVENT17    = 0x331, /**< 0x331 - mhpmevent17 (r/w): Machine hardware performance monitor event selector 17 */
80 
  CSR_MHPMEVENT18    = 0x332, /**< 0x332 - mhpmevent18 (r/w): Machine hardware performance monitor event selector 18 */
81 
  CSR_MHPMEVENT19    = 0x333, /**< 0x333 - mhpmevent19 (r/w): Machine hardware performance monitor event selector 19 */
82 
  CSR_MHPMEVENT20    = 0x334, /**< 0x334 - mhpmevent20 (r/w): Machine hardware performance monitor event selector 20 */
83 
  CSR_MHPMEVENT21    = 0x335, /**< 0x335 - mhpmevent21 (r/w): Machine hardware performance monitor event selector 21 */
84 
  CSR_MHPMEVENT22    = 0x336, /**< 0x336 - mhpmevent22 (r/w): Machine hardware performance monitor event selector 22 */
85 
  CSR_MHPMEVENT23    = 0x337, /**< 0x337 - mhpmevent23 (r/w): Machine hardware performance monitor event selector 23 */
86 
  CSR_MHPMEVENT24    = 0x338, /**< 0x338 - mhpmevent24 (r/w): Machine hardware performance monitor event selector 24 */
87 
  CSR_MHPMEVENT25    = 0x339, /**< 0x339 - mhpmevent25 (r/w): Machine hardware performance monitor event selector 25 */
88 
  CSR_MHPMEVENT26    = 0x33a, /**< 0x33a - mhpmevent26 (r/w): Machine hardware performance monitor event selector 26 */
89 
  CSR_MHPMEVENT27    = 0x33b, /**< 0x33b - mhpmevent27 (r/w): Machine hardware performance monitor event selector 27 */
90 
  CSR_MHPMEVENT28    = 0x33c, /**< 0x33c - mhpmevent28 (r/w): Machine hardware performance monitor event selector 28 */
91 
  CSR_MHPMEVENT29    = 0x33d, /**< 0x33d - mhpmevent29 (r/w): Machine hardware performance monitor event selector 29 */
92 
  CSR_MHPMEVENT30    = 0x33e, /**< 0x33e - mhpmevent30 (r/w): Machine hardware performance monitor event selector 30 */
93 
  CSR_MHPMEVENT31    = 0x33f, /**< 0x33f - mhpmevent31 (r/w): Machine hardware performance monitor event selector 31 */
94 15 zero_gravi 
 
95 42 zero_gravi 
  CSR_MSCRATCH       = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
96 
  CSR_MEPC           = 0x341, /**< 0x341 - mepc     (r/w): Machine exception program counter */
97 
  CSR_MCAUSE         = 0x342, /**< 0x342 - mcause   (r/w): Machine trap cause */
98 
  CSR_MTVAL          = 0x343, /**< 0x343 - mtval    (r/w): Machine bad address or instruction */
99 
  CSR_MIP            = 0x344, /**< 0x344 - mip      (r/w): Machine interrupt pending register */
100 15 zero_gravi 
 
101 42 zero_gravi 
  CSR_PMPCFG0        = 0x3a0, /**< 0x3a0 - pmpcfg0  (r/w): Physical memory protection configuration register 0  */
102 
  CSR_PMPCFG1        = 0x3a1, /**< 0x3a1 - pmpcfg1  (r/w): Physical memory protection configuration register 1  */
103 
  CSR_PMPCFG2        = 0x3a2, /**< 0x3a2 - pmpcfg2  (r/w): Physical memory protection configuration register 2  */
104 
  CSR_PMPCFG3        = 0x3a3, /**< 0x3a3 - pmpcfg3  (r/w): Physical memory protection configuration register 3  */
105 
  CSR_PMPCFG4        = 0x3a4, /**< 0x3a4 - pmpcfg4  (r/w): Physical memory protection configuration register 4  */
106 
  CSR_PMPCFG5        = 0x3a5, /**< 0x3a5 - pmpcfg5  (r/w): Physical memory protection configuration register 5  */
107 
  CSR_PMPCFG6        = 0x3a6, /**< 0x3a6 - pmpcfg6  (r/w): Physical memory protection configuration register 6  */
108 
  CSR_PMPCFG7        = 0x3a7, /**< 0x3a7 - pmpcfg7  (r/w): Physical memory protection configuration register 7  */
109 
  CSR_PMPCFG8        = 0x3a8, /**< 0x3a8 - pmpcfg8  (r/w): Physical memory protection configuration register 8  */
110 
  CSR_PMPCFG9        = 0x3a9, /**< 0x3a9 - pmpcfg9  (r/w): Physical memory protection configuration register 9  */
111 
  CSR_PMPCFG10       = 0x3aa, /**< 0x3aa - pmpcfg10 (r/w): Physical memory protection configuration register 10 */
112 
  CSR_PMPCFG11       = 0x3ab, /**< 0x3ab - pmpcfg11 (r/w): Physical memory protection configuration register 11 */
113 
  CSR_PMPCFG12       = 0x3ac, /**< 0x3ac - pmpcfg12 (r/w): Physical memory protection configuration register 12 */
114 
  CSR_PMPCFG13       = 0x3ad, /**< 0x3ad - pmpcfg13 (r/w): Physical memory protection configuration register 13 */
115 
  CSR_PMPCFG14       = 0x3ae, /**< 0x3ae - pmpcfg14 (r/w): Physical memory protection configuration register 14 */
116 
  CSR_PMPCFG15       = 0x3af, /**< 0x3af - pmpcfg15 (r/w): Physical memory protection configuration register 15 */
117 18 zero_gravi 
 
118 42 zero_gravi 
  CSR_PMPADDR0       = 0x3b0, /**< 0x3b0 - pmpaddr0  (r/w): Physical memory protection address register 0  */
119 
  CSR_PMPADDR1       = 0x3b1, /**< 0x3b1 - pmpaddr1  (r/w): Physical memory protection address register 1  */
120 
  CSR_PMPADDR2       = 0x3b2, /**< 0x3b2 - pmpaddr2  (r/w): Physical memory protection address register 2  */
121 
  CSR_PMPADDR3       = 0x3b3, /**< 0x3b3 - pmpaddr3  (r/w): Physical memory protection address register 3  */
122 
  CSR_PMPADDR4       = 0x3b4, /**< 0x3b4 - pmpaddr4  (r/w): Physical memory protection address register 4  */
123 
  CSR_PMPADDR5       = 0x3b5, /**< 0x3b5 - pmpaddr5  (r/w): Physical memory protection address register 5  */
124 
  CSR_PMPADDR6       = 0x3b6, /**< 0x3b6 - pmpaddr6  (r/w): Physical memory protection address register 6  */
125 
  CSR_PMPADDR7       = 0x3b7, /**< 0x3b7 - pmpaddr7  (r/w): Physical memory protection address register 7  */
126 
  CSR_PMPADDR8       = 0x3b8, /**< 0x3b8 - pmpaddr8  (r/w): Physical memory protection address register 8  */
127 
  CSR_PMPADDR9       = 0x3b9, /**< 0x3b9 - pmpaddr9  (r/w): Physical memory protection address register 9  */
128 
  CSR_PMPADDR10      = 0x3ba, /**< 0x3ba - pmpaddr10 (r/w): Physical memory protection address register 10 */
129 
  CSR_PMPADDR11      = 0x3bb, /**< 0x3bb - pmpaddr11 (r/w): Physical memory protection address register 11 */
130 
  CSR_PMPADDR12      = 0x3bc, /**< 0x3bc - pmpaddr12 (r/w): Physical memory protection address register 12 */
131 
  CSR_PMPADDR13      = 0x3bd, /**< 0x3bd - pmpaddr13 (r/w): Physical memory protection address register 13 */
132 
  CSR_PMPADDR14      = 0x3be, /**< 0x3be - pmpaddr14 (r/w): Physical memory protection address register 14 */
133 
  CSR_PMPADDR15      = 0x3bf, /**< 0x3bf - pmpaddr15 (r/w): Physical memory protection address register 15 */
134 
  CSR_PMPADDR16      = 0x3c0, /**< 0x3c0 - pmpaddr16 (r/w): Physical memory protection address register 16 */
135 
  CSR_PMPADDR17      = 0x3c1, /**< 0x3c1 - pmpaddr17 (r/w): Physical memory protection address register 17 */
136 
  CSR_PMPADDR18      = 0x3c2, /**< 0x3c2 - pmpaddr18 (r/w): Physical memory protection address register 18 */
137 
  CSR_PMPADDR19      = 0x3c3, /**< 0x3c3 - pmpaddr19 (r/w): Physical memory protection address register 19 */
138 
  CSR_PMPADDR20      = 0x3c4, /**< 0x3c4 - pmpaddr20 (r/w): Physical memory protection address register 20 */
139 
  CSR_PMPADDR21      = 0x3c5, /**< 0x3c5 - pmpaddr21 (r/w): Physical memory protection address register 21 */
140 
  CSR_PMPADDR22      = 0x3c6, /**< 0x3c6 - pmpaddr22 (r/w): Physical memory protection address register 22 */
141 
  CSR_PMPADDR23      = 0x3c7, /**< 0x3c7 - pmpaddr23 (r/w): Physical memory protection address register 23 */
142 
  CSR_PMPADDR24      = 0x3c8, /**< 0x3c8 - pmpaddr24 (r/w): Physical memory protection address register 24 */
143 
  CSR_PMPADDR25      = 0x3c9, /**< 0x3c9 - pmpaddr25 (r/w): Physical memory protection address register 25 */
144 
  CSR_PMPADDR26      = 0x3ca, /**< 0x3ca - pmpaddr26 (r/w): Physical memory protection address register 26 */
145 
  CSR_PMPADDR27      = 0x3cb, /**< 0x3cb - pmpaddr27 (r/w): Physical memory protection address register 27 */
146 
  CSR_PMPADDR28      = 0x3cc, /**< 0x3cc - pmpaddr28 (r/w): Physical memory protection address register 28 */
147 
  CSR_PMPADDR29      = 0x3cd, /**< 0x3cd - pmpaddr29 (r/w): Physical memory protection address register 29 */
148 
  CSR_PMPADDR30      = 0x3ce, /**< 0x3ce - pmpaddr30 (r/w): Physical memory protection address register 30 */
149 
  CSR_PMPADDR31      = 0x3cf, /**< 0x3cf - pmpaddr31 (r/w): Physical memory protection address register 31 */
150 
  CSR_PMPADDR32      = 0x3d0, /**< 0x3d0 - pmpaddr32 (r/w): Physical memory protection address register 32 */
151 
  CSR_PMPADDR33      = 0x3d1, /**< 0x3d1 - pmpaddr33 (r/w): Physical memory protection address register 33 */
152 
  CSR_PMPADDR34      = 0x3d2, /**< 0x3d2 - pmpaddr34 (r/w): Physical memory protection address register 34 */
153 
  CSR_PMPADDR35      = 0x3d3, /**< 0x3d3 - pmpaddr35 (r/w): Physical memory protection address register 35 */
154 
  CSR_PMPADDR36      = 0x3d4, /**< 0x3d4 - pmpaddr36 (r/w): Physical memory protection address register 36 */
155 
  CSR_PMPADDR37      = 0x3d5, /**< 0x3d5 - pmpaddr37 (r/w): Physical memory protection address register 37 */
156 
  CSR_PMPADDR38      = 0x3d6, /**< 0x3d6 - pmpaddr38 (r/w): Physical memory protection address register 38 */
157 
  CSR_PMPADDR39      = 0x3d7, /**< 0x3d7 - pmpaddr39 (r/w): Physical memory protection address register 39 */
158 
  CSR_PMPADDR40      = 0x3d8, /**< 0x3d8 - pmpaddr40 (r/w): Physical memory protection address register 40 */
159 
  CSR_PMPADDR41      = 0x3d9, /**< 0x3d9 - pmpaddr41 (r/w): Physical memory protection address register 41 */
160 
  CSR_PMPADDR42      = 0x3da, /**< 0x3da - pmpaddr42 (r/w): Physical memory protection address register 42 */
161 
  CSR_PMPADDR43      = 0x3db, /**< 0x3db - pmpaddr43 (r/w): Physical memory protection address register 43 */
162 
  CSR_PMPADDR44      = 0x3dc, /**< 0x3dc - pmpaddr44 (r/w): Physical memory protection address register 44 */
163 
  CSR_PMPADDR45      = 0x3dd, /**< 0x3dd - pmpaddr45 (r/w): Physical memory protection address register 45 */
164 
  CSR_PMPADDR46      = 0x3de, /**< 0x3de - pmpaddr46 (r/w): Physical memory protection address register 46 */
165 
  CSR_PMPADDR47      = 0x3df, /**< 0x3df - pmpaddr47 (r/w): Physical memory protection address register 47 */
166 
  CSR_PMPADDR48      = 0x3e0, /**< 0x3e0 - pmpaddr48 (r/w): Physical memory protection address register 48 */
167 
  CSR_PMPADDR49      = 0x3e1, /**< 0x3e1 - pmpaddr49 (r/w): Physical memory protection address register 49 */
168 
  CSR_PMPADDR50      = 0x3e2, /**< 0x3e2 - pmpaddr50 (r/w): Physical memory protection address register 50 */
169 
  CSR_PMPADDR51      = 0x3e3, /**< 0x3e3 - pmpaddr51 (r/w): Physical memory protection address register 51 */
170 
  CSR_PMPADDR52      = 0x3e4, /**< 0x3e4 - pmpaddr52 (r/w): Physical memory protection address register 52 */
171 
  CSR_PMPADDR53      = 0x3e5, /**< 0x3e5 - pmpaddr53 (r/w): Physical memory protection address register 53 */
172 
  CSR_PMPADDR54      = 0x3e6, /**< 0x3e6 - pmpaddr54 (r/w): Physical memory protection address register 54 */
173 
  CSR_PMPADDR55      = 0x3e7, /**< 0x3e7 - pmpaddr55 (r/w): Physical memory protection address register 55 */
174 
  CSR_PMPADDR56      = 0x3e8, /**< 0x3e8 - pmpaddr56 (r/w): Physical memory protection address register 56 */
175 
  CSR_PMPADDR57      = 0x3e9, /**< 0x3e9 - pmpaddr57 (r/w): Physical memory protection address register 57 */
176 
  CSR_PMPADDR58      = 0x3ea, /**< 0x3ea - pmpaddr58 (r/w): Physical memory protection address register 58 */
177 
  CSR_PMPADDR59      = 0x3eb, /**< 0x3eb - pmpaddr59 (r/w): Physical memory protection address register 59 */
178 
  CSR_PMPADDR60      = 0x3ec, /**< 0x3ec - pmpaddr60 (r/w): Physical memory protection address register 60 */
179 
  CSR_PMPADDR61      = 0x3ed, /**< 0x3ed - pmpaddr61 (r/w): Physical memory protection address register 61 */
180 
  CSR_PMPADDR62      = 0x3ee, /**< 0x3ee - pmpaddr62 (r/w): Physical memory protection address register 62 */
181 
  CSR_PMPADDR63      = 0x3ef, /**< 0x3ef - pmpaddr63 (r/w): Physical memory protection address register 63 */
182 2 zero_gravi 
 
183 42 zero_gravi 
  CSR_MCYCLE         = 0xb00, /**< 0xb00 - mcycle        (r/w): Machine cycle counter low word */
184 
  CSR_MINSTRET       = 0xb02, /**< 0xb02 - minstret      (r/w): Machine instructions-retired counter low word */
185 2 zero_gravi 
 
186 42 zero_gravi 
  CSR_MHPMCOUNTER3   = 0xb03, /**< 0xb03 - mhpmcounter3  (r/w): Machine hardware performance monitor 3  counter low word */
187 
  CSR_MHPMCOUNTER4   = 0xb04, /**< 0xb04 - mhpmcounter4  (r/w): Machine hardware performance monitor 4  counter low word */
188 
  CSR_MHPMCOUNTER5   = 0xb05, /**< 0xb05 - mhpmcounter5  (r/w): Machine hardware performance monitor 5  counter low word */
189 
  CSR_MHPMCOUNTER6   = 0xb06, /**< 0xb06 - mhpmcounter6  (r/w): Machine hardware performance monitor 6  counter low word */
190 
  CSR_MHPMCOUNTER7   = 0xb07, /**< 0xb07 - mhpmcounter7  (r/w): Machine hardware performance monitor 7  counter low word */
191 
  CSR_MHPMCOUNTER8   = 0xb08, /**< 0xb08 - mhpmcounter8  (r/w): Machine hardware performance monitor 8  counter low word */
192 
  CSR_MHPMCOUNTER9   = 0xb09, /**< 0xb09 - mhpmcounter9  (r/w): Machine hardware performance monitor 9  counter low word */
193 
  CSR_MHPMCOUNTER10  = 0xb0a, /**< 0xb0a - mhpmcounter10 (r/w): Machine hardware performance monitor 10 counter low word */
194 
  CSR_MHPMCOUNTER11  = 0xb0b, /**< 0xb0b - mhpmcounter11 (r/w): Machine hardware performance monitor 11 counter low word */
195 
  CSR_MHPMCOUNTER12  = 0xb0c, /**< 0xb0c - mhpmcounter12 (r/w): Machine hardware performance monitor 12 counter low word */
196 
  CSR_MHPMCOUNTER13  = 0xb0d, /**< 0xb0d - mhpmcounter13 (r/w): Machine hardware performance monitor 13 counter low word */
197 
  CSR_MHPMCOUNTER14  = 0xb0e, /**< 0xb0e - mhpmcounter14 (r/w): Machine hardware performance monitor 14 counter low word */
198 
  CSR_MHPMCOUNTER15  = 0xb0f, /**< 0xb0f - mhpmcounter15 (r/w): Machine hardware performance monitor 15 counter low word */
199 
  CSR_MHPMCOUNTER16  = 0xb10, /**< 0xb10 - mhpmcounter16 (r/w): Machine hardware performance monitor 16 counter low word */
200 
  CSR_MHPMCOUNTER17  = 0xb11, /**< 0xb11 - mhpmcounter17 (r/w): Machine hardware performance monitor 17 counter low word */
201 
  CSR_MHPMCOUNTER18  = 0xb12, /**< 0xb12 - mhpmcounter18 (r/w): Machine hardware performance monitor 18 counter low word */
202 
  CSR_MHPMCOUNTER19  = 0xb13, /**< 0xb13 - mhpmcounter19 (r/w): Machine hardware performance monitor 19 counter low word */
203 
  CSR_MHPMCOUNTER20  = 0xb14, /**< 0xb14 - mhpmcounter20 (r/w): Machine hardware performance monitor 20 counter low word */
204 
  CSR_MHPMCOUNTER21  = 0xb15, /**< 0xb15 - mhpmcounter21 (r/w): Machine hardware performance monitor 21 counter low word */
205 
  CSR_MHPMCOUNTER22  = 0xb16, /**< 0xb16 - mhpmcounter22 (r/w): Machine hardware performance monitor 22 counter low word */
206 
  CSR_MHPMCOUNTER23  = 0xb17, /**< 0xb17 - mhpmcounter23 (r/w): Machine hardware performance monitor 23 counter low word */
207 
  CSR_MHPMCOUNTER24  = 0xb18, /**< 0xb18 - mhpmcounter24 (r/w): Machine hardware performance monitor 24 counter low word */
208 
  CSR_MHPMCOUNTER25  = 0xb19, /**< 0xb19 - mhpmcounter25 (r/w): Machine hardware performance monitor 25 counter low word */
209 
  CSR_MHPMCOUNTER26  = 0xb1a, /**< 0xb1a - mhpmcounter26 (r/w): Machine hardware performance monitor 26 counter low word */
210 
  CSR_MHPMCOUNTER27  = 0xb1b, /**< 0xb1b - mhpmcounter27 (r/w): Machine hardware performance monitor 27 counter low word */
211 
  CSR_MHPMCOUNTER28  = 0xb1c, /**< 0xb1c - mhpmcounter28 (r/w): Machine hardware performance monitor 28 counter low word */
212 
  CSR_MHPMCOUNTER29  = 0xb1d, /**< 0xb1d - mhpmcounter29 (r/w): Machine hardware performance monitor 29 counter low word */
213 
  CSR_MHPMCOUNTER30  = 0xb1e, /**< 0xb1e - mhpmcounter30 (r/w): Machine hardware performance monitor 30 counter low word */
214 
  CSR_MHPMCOUNTER31  = 0xb1f, /**< 0xb1f - mhpmcounter31 (r/w): Machine hardware performance monitor 31 counter low word */
215 2 zero_gravi 
 
216 42 zero_gravi 
  CSR_MCYCLEH        = 0xb80, /**< 0xb80 - mcycleh        (r/w): Machine cycle counter high word */
217 
  CSR_MINSTRETH      = 0xb82, /**< 0xb82 - minstreth      (r/w): Machine instructions-retired counter high word */
218 22 zero_gravi 
 
219 42 zero_gravi 
  CSR_MHPMCOUNTER3H  = 0xb83, /**< 0xb83 - mhpmcounter3h  (r/w): Machine hardware performance monitor 3  counter high word */
220 
  CSR_MHPMCOUNTER4H  = 0xb84, /**< 0xb84 - mhpmcounter4h  (r/w): Machine hardware performance monitor 4  counter high word */
221 
  CSR_MHPMCOUNTER5H  = 0xb85, /**< 0xb85 - mhpmcounter5h  (r/w): Machine hardware performance monitor 5  counter high word */
222 
  CSR_MHPMCOUNTER6H  = 0xb86, /**< 0xb86 - mhpmcounter6h  (r/w): Machine hardware performance monitor 6  counter high word */
223 
  CSR_MHPMCOUNTER7H  = 0xb87, /**< 0xb87 - mhpmcounter7h  (r/w): Machine hardware performance monitor 7  counter high word */
224 
  CSR_MHPMCOUNTER8H  = 0xb88, /**< 0xb88 - mhpmcounter8h  (r/w): Machine hardware performance monitor 8  counter high word */
225 
  CSR_MHPMCOUNTER9H  = 0xb89, /**< 0xb89 - mhpmcounter9h  (r/w): Machine hardware performance monitor 9  counter high word */
226 
  CSR_MHPMCOUNTER10H = 0xb8a, /**< 0xb8a - mhpmcounter10h (r/w): Machine hardware performance monitor 10 counter high word */
227 
  CSR_MHPMCOUNTER11H = 0xb8b, /**< 0xb8b - mhpmcounter11h (r/w): Machine hardware performance monitor 11 counter high word */
228 
  CSR_MHPMCOUNTER12H = 0xb8c, /**< 0xb8c - mhpmcounter12h (r/w): Machine hardware performance monitor 12 counter high word */
229 
  CSR_MHPMCOUNTER13H = 0xb8d, /**< 0xb8d - mhpmcounter13h (r/w): Machine hardware performance monitor 13 counter high word */
230 
  CSR_MHPMCOUNTER14H = 0xb8e, /**< 0xb8e - mhpmcounter14h (r/w): Machine hardware performance monitor 14 counter high word */
231 
  CSR_MHPMCOUNTER15H = 0xb8f, /**< 0xb8f - mhpmcounter15h (r/w): Machine hardware performance monitor 15 counter high word */
232 
  CSR_MHPMCOUNTER16H = 0xb90, /**< 0xb90 - mhpmcounter16h (r/w): Machine hardware performance monitor 16 counter high word */
233 
  CSR_MHPMCOUNTER17H = 0xb91, /**< 0xb91 - mhpmcounter17h (r/w): Machine hardware performance monitor 17 counter high word */
234 
  CSR_MHPMCOUNTER18H = 0xb92, /**< 0xb92 - mhpmcounter18h (r/w): Machine hardware performance monitor 18 counter high word */
235 
  CSR_MHPMCOUNTER19H = 0xb93, /**< 0xb93 - mhpmcounter19h (r/w): Machine hardware performance monitor 19 counter high word */
236 
  CSR_MHPMCOUNTER20H = 0xb94, /**< 0xb94 - mhpmcounter20h (r/w): Machine hardware performance monitor 20 counter high word */
237 
  CSR_MHPMCOUNTER21H = 0xb95, /**< 0xb95 - mhpmcounter21h (r/w): Machine hardware performance monitor 21 counter high word */
238 
  CSR_MHPMCOUNTER22H = 0xb96, /**< 0xb96 - mhpmcounter22h (r/w): Machine hardware performance monitor 22 counter high word */
239 
  CSR_MHPMCOUNTER23H = 0xb97, /**< 0xb97 - mhpmcounter23h (r/w): Machine hardware performance monitor 23 counter high word */
240 
  CSR_MHPMCOUNTER24H = 0xb98, /**< 0xb98 - mhpmcounter24h (r/w): Machine hardware performance monitor 24 counter high word */
241 
  CSR_MHPMCOUNTER25H = 0xb99, /**< 0xb99 - mhpmcounter25h (r/w): Machine hardware performance monitor 25 counter high word */
242 
  CSR_MHPMCOUNTER26H = 0xb9a, /**< 0xb9a - mhpmcounter26h (r/w): Machine hardware performance monitor 26 counter high word */
243 
  CSR_MHPMCOUNTER27H = 0xb9b, /**< 0xb9b - mhpmcounter27h (r/w): Machine hardware performance monitor 27 counter high word */
244 
  CSR_MHPMCOUNTER28H = 0xb9c, /**< 0xb9c - mhpmcounter28h (r/w): Machine hardware performance monitor 28 counter high word */
245 
  CSR_MHPMCOUNTER29H = 0xb9d, /**< 0xb9d - mhpmcounter29h (r/w): Machine hardware performance monitor 29 counter high word */
246 
  CSR_MHPMCOUNTER30H = 0xb9e, /**< 0xb9e - mhpmcounter30h (r/w): Machine hardware performance monitor 30 counter high word */
247 
  CSR_MHPMCOUNTER31H = 0xb9f, /**< 0xb9f - mhpmcounter31h (r/w): Machine hardware performance monitor 31 counter high word */
248 41 zero_gravi 
 
249 42 zero_gravi 
  CSR_CYCLE          = 0xc00, /**< 0xc00 - cycle        (r/-): Cycle counter low word (from MCYCLE) */
250 
  CSR_TIME           = 0xc01, /**< 0xc01 - time         (r/-): Timer low word (from MTIME.TIME_LO) */
251 
  CSR_INSTRET        = 0xc02, /**< 0xc02 - instret      (r/-): Instructions-retired counter low word (from MINSTRET) */
252 
 
253 
  CSR_HPMCOUNTER3    = 0xc03, /**< 0xc03 - hpmcounter3  (r/w): Hardware performance monitor 3  counter low word */
254 
  CSR_HPMCOUNTER4    = 0xc04, /**< 0xc04 - hpmcounter4  (r/w): Hardware performance monitor 4  counter low word */
255 
  CSR_HPMCOUNTER5    = 0xc05, /**< 0xc05 - hpmcounter5  (r/w): Hardware performance monitor 5  counter low word */
256 
  CSR_HPMCOUNTER6    = 0xc06, /**< 0xc06 - hpmcounter6  (r/w): Hardware performance monitor 6  counter low word */
257 
  CSR_HPMCOUNTER7    = 0xc07, /**< 0xc07 - hpmcounter7  (r/w): Hardware performance monitor 7  counter low word */
258 
  CSR_HPMCOUNTER8    = 0xc08, /**< 0xc08 - hpmcounter8  (r/w): Hardware performance monitor 8  counter low word */
259 
  CSR_HPMCOUNTER9    = 0xc09, /**< 0xc09 - hpmcounter9  (r/w): Hardware performance monitor 9  counter low word */
260 
  CSR_HPMCOUNTER10   = 0xc0a, /**< 0xc0a - hpmcounter10 (r/w): Hardware performance monitor 10 counter low word */
261 
  CSR_HPMCOUNTER11   = 0xc0b, /**< 0xc0b - hpmcounter11 (r/w): Hardware performance monitor 11 counter low word */
262 
  CSR_HPMCOUNTER12   = 0xc0c, /**< 0xc0c - hpmcounter12 (r/w): Hardware performance monitor 12 counter low word */
263 
  CSR_HPMCOUNTER13   = 0xc0d, /**< 0xc0d - hpmcounter13 (r/w): Hardware performance monitor 13 counter low word */
264 
  CSR_HPMCOUNTER14   = 0xc0e, /**< 0xc0e - hpmcounter14 (r/w): Hardware performance monitor 14 counter low word */
265 
  CSR_HPMCOUNTER15   = 0xc0f, /**< 0xc0f - hpmcounter15 (r/w): Hardware performance monitor 15 counter low word */
266 
  CSR_HPMCOUNTER16   = 0xc10, /**< 0xc10 - hpmcounter16 (r/w): Hardware performance monitor 16 counter low word */
267 
  CSR_HPMCOUNTER17   = 0xc11, /**< 0xc11 - hpmcounter17 (r/w): Hardware performance monitor 17 counter low word */
268 
  CSR_HPMCOUNTER18   = 0xc12, /**< 0xc12 - hpmcounter18 (r/w): Hardware performance monitor 18 counter low word */
269 
  CSR_HPMCOUNTER19   = 0xc13, /**< 0xc13 - hpmcounter19 (r/w): Hardware performance monitor 19 counter low word */
270 
  CSR_HPMCOUNTER20   = 0xc14, /**< 0xc14 - hpmcounter20 (r/w): Hardware performance monitor 20 counter low word */
271 
  CSR_HPMCOUNTER21   = 0xc15, /**< 0xc15 - hpmcounter21 (r/w): Hardware performance monitor 21 counter low word */
272 
  CSR_HPMCOUNTER22   = 0xc16, /**< 0xc16 - hpmcounter22 (r/w): Hardware performance monitor 22 counter low word */
273 
  CSR_HPMCOUNTER23   = 0xc17, /**< 0xc17 - hpmcounter23 (r/w): Hardware performance monitor 23 counter low word */
274 
  CSR_HPMCOUNTER24   = 0xc18, /**< 0xc18 - hpmcounter24 (r/w): Hardware performance monitor 24 counter low word */
275 
  CSR_HPMCOUNTER25   = 0xc19, /**< 0xc19 - hpmcounter25 (r/w): Hardware performance monitor 25 counter low word */
276 
  CSR_HPMCOUNTER26   = 0xc1a, /**< 0xc1a - hpmcounter26 (r/w): Hardware performance monitor 26 counter low word */
277 
  CSR_HPMCOUNTER27   = 0xc1b, /**< 0xc1b - hpmcounter27 (r/w): Hardware performance monitor 27 counter low word */
278 
  CSR_HPMCOUNTER28   = 0xc1c, /**< 0xc1c - hpmcounter28 (r/w): Hardware performance monitor 28 counter low word */
279 
  CSR_HPMCOUNTER29   = 0xc1d, /**< 0xc1d - hpmcounter29 (r/w): Hardware performance monitor 29 counter low word */
280 
  CSR_HPMCOUNTER30   = 0xc1e, /**< 0xc1e - hpmcounter30 (r/w): Hardware performance monitor 30 counter low word */
281 
  CSR_HPMCOUNTER31   = 0xc1f, /**< 0xc1f - hpmcounter31 (r/w): Hardware performance monitor 31 counter low word */
282 
 
283 
  CSR_CYCLEH         = 0xc80, /**< 0xc80 - cycleh        (r/-): Cycle counter high word (from MCYCLEH) */
284 
  CSR_TIMEH          = 0xc81, /**< 0xc81 - timeh         (r/-): Timer high word (from MTIME.TIME_HI) */
285 
  CSR_INSTRETH       = 0xc82, /**< 0xc82 - instreth      (r/-): Instructions-retired counter high word (from MINSTRETH) */
286 
 
287 
  CSR_HPMCOUNTER3H   = 0xc83, /**< 0xc83 - hpmcounter3h  (r/w): Hardware performance monitor 3  counter high word */
288 
  CSR_HPMCOUNTER4H   = 0xc84, /**< 0xc84 - hpmcounter4h  (r/w): Hardware performance monitor 4  counter high word */
289 
  CSR_HPMCOUNTER5H   = 0xc85, /**< 0xc85 - hpmcounter5h  (r/w): Hardware performance monitor 5  counter high word */
290 
  CSR_HPMCOUNTER6H   = 0xc86, /**< 0xc86 - hpmcounter6h  (r/w): Hardware performance monitor 6  counter high word */
291 
  CSR_HPMCOUNTER7H   = 0xc87, /**< 0xc87 - hpmcounter7h  (r/w): Hardware performance monitor 7  counter high word */
292 
  CSR_HPMCOUNTER8H   = 0xc88, /**< 0xc88 - hpmcounter8h  (r/w): Hardware performance monitor 8  counter high word */
293 
  CSR_HPMCOUNTER9H   = 0xc89, /**< 0xc89 - hpmcounter9h  (r/w): Hardware performance monitor 9  counter high word */
294 
  CSR_HPMCOUNTER10H  = 0xc8a, /**< 0xc8a - hpmcounter10h (r/w): Hardware performance monitor 10 counter high word */
295 
  CSR_HPMCOUNTER11H  = 0xc8b, /**< 0xc8b - hpmcounter11h (r/w): Hardware performance monitor 11 counter high word */
296 
  CSR_HPMCOUNTER12H  = 0xc8c, /**< 0xc8c - hpmcounter12h (r/w): Hardware performance monitor 12 counter high word */
297 
  CSR_HPMCOUNTER13H  = 0xc8d, /**< 0xc8d - hpmcounter13h (r/w): Hardware performance monitor 13 counter high word */
298 
  CSR_HPMCOUNTER14H  = 0xc8e, /**< 0xc8e - hpmcounter14h (r/w): Hardware performance monitor 14 counter high word */
299 
  CSR_HPMCOUNTER15H  = 0xc8f, /**< 0xc8f - hpmcounter15h (r/w): Hardware performance monitor 15 counter high word */
300 
  CSR_HPMCOUNTER16H  = 0xc90, /**< 0xc90 - hpmcounter16h (r/w): Hardware performance monitor 16 counter high word */
301 
  CSR_HPMCOUNTER17H  = 0xc91, /**< 0xc91 - hpmcounter17h (r/w): Hardware performance monitor 17 counter high word */
302 
  CSR_HPMCOUNTER18H  = 0xc92, /**< 0xc92 - hpmcounter18h (r/w): Hardware performance monitor 18 counter high word */
303 
  CSR_HPMCOUNTER19H  = 0xc93, /**< 0xc93 - hpmcounter19h (r/w): Hardware performance monitor 19 counter high word */
304 
  CSR_HPMCOUNTER20H  = 0xc94, /**< 0xc94 - hpmcounter20h (r/w): Hardware performance monitor 20 counter high word */
305 
  CSR_HPMCOUNTER21H  = 0xc95, /**< 0xc95 - hpmcounter21h (r/w): Hardware performance monitor 21 counter high word */
306 
  CSR_HPMCOUNTER22H  = 0xc96, /**< 0xc96 - hpmcounter22h (r/w): Hardware performance monitor 22 counter high word */
307 
  CSR_HPMCOUNTER23H  = 0xc97, /**< 0xc97 - hpmcounter23h (r/w): Hardware performance monitor 23 counter high word */
308 
  CSR_HPMCOUNTER24H  = 0xc98, /**< 0xc98 - hpmcounter24h (r/w): Hardware performance monitor 24 counter high word */
309 
  CSR_HPMCOUNTER25H  = 0xc99, /**< 0xc99 - hpmcounter25h (r/w): Hardware performance monitor 25 counter high word */
310 
  CSR_HPMCOUNTER26H  = 0xc9a, /**< 0xc9a - hpmcounter26h (r/w): Hardware performance monitor 26 counter high word */
311 
  CSR_HPMCOUNTER27H  = 0xc9b, /**< 0xc9b - hpmcounter27h (r/w): Hardware performance monitor 27 counter high word */
312 
  CSR_HPMCOUNTER28H  = 0xc9c, /**< 0xc9c - hpmcounter28h (r/w): Hardware performance monitor 28 counter high word */
313 
  CSR_HPMCOUNTER29H  = 0xc9d, /**< 0xc9d - hpmcounter29h (r/w): Hardware performance monitor 29 counter high word */
314 
  CSR_HPMCOUNTER30H  = 0xc9e, /**< 0xc9e - hpmcounter30h (r/w): Hardware performance monitor 30 counter high word */
315 
  CSR_HPMCOUNTER31H  = 0xc9f, /**< 0xc9f - hpmcounter31h (r/w): Hardware performance monitor 31 counter high word */
316 
 
317 
  CSR_MVENDORID      = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
318 
  CSR_MARCHID        = 0xf12, /**< 0xf12 - marchid   (r/-): Architecture ID */
319 
  CSR_MIMPID         = 0xf13, /**< 0xf13 - mimpid    (r/-): Implementation ID/version */
320 
  CSR_MHARTID        = 0xf14, /**< 0xf14 - mhartid   (r/-): Hardware thread ID (always 0) */
321 
 
322 
  CSR_MZEXT          = 0xfc0  /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */
323 2 zero_gravi 
};
324 
 
325 
 
326 
/**********************************************************************//**
327 
 * CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
328 
 **************************************************************************/
329 42 zero_gravi 
enum NEORV32_CSR_MSTATUS_enum {
330 44 zero_gravi 
  CSR_MSTATUS_MIE   =  3, /**< CPU mstatus CSR  (3): MIE - Machine interrupt enable bit (r/w) */
331 
  CSR_MSTATUS_UBE   =  6, /**< CPU mstatus CSR  (6): UBE - User-mode endianness (little-endian=0, big-endian=1) (r/-) */
332 
  CSR_MSTATUS_MPIE  =  7, /**< CPU mstatus CSR  (7): MPIE - Machine previous interrupt enable bit (r/w) */
333 42 zero_gravi 
  CSR_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
334 
  CSR_MSTATUS_MPP_H = 12  /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
335 2 zero_gravi 
};
336 
 
337 
 
338 
/**********************************************************************//**
339 41 zero_gravi 
 * CPU <b>mstatush</b> CSR (r/-): Machine status - high word (RISC-V spec.)
340 40 zero_gravi 
 **************************************************************************/
341 42 zero_gravi 
enum NEORV32_CSR_MSTATUSH_enum {
342 
  CSR_MSTATUSH_MBE = 5 /**< CPU mstatush CSR (5): MBE - Machine-mode endianness (little-endian=0, big-endian=1) (r/-) */
343 40 zero_gravi 
};
344 
 
345 
 
346 
/**********************************************************************//**
347 41 zero_gravi 
 * CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
348 
 **************************************************************************/
349 42 zero_gravi 
enum NEORV32_CSR_MCOUNTEREN_enum {
350 
  CSR_MCOUNTEREN_CY = 0, /**< CPU mcounteren CSR (0): CY - Allow access to cycle[h] CSRs from U-mode when set (r/w) */
351 
  CSR_MCOUNTEREN_TM = 1, /**< CPU mcounteren CSR (1): TM - Allow access to time[h] CSRs from U-mode when set (r/w) */
352 
  CSR_MCOUNTEREN_IR = 2  /**< CPU mcounteren CSR (2): IR - Allow access to instret[h] CSRs from U-mode when set (r/w) */
353 41 zero_gravi 
};
354 
 
355 
 
356 
/**********************************************************************//**
357 
 * CPU <b>mcountinhibit</b> CSR (r/w): Machine counter-inhibit (RISC-V spec.)
358 
 **************************************************************************/
359 42 zero_gravi 
enum NEORV32_CSR_MCOUNTINHIBIT_enum {
360 
  CSR_MCOUNTINHIBIT_CY = 0, /**< CPU mcountinhibit CSR (0): CY - Enable auto-increment of [m]cycle[h] CSR when set (r/w) */
361 
  CSR_MCOUNTINHIBIT_IR = 2  /**< CPU mcountinhibit CSR (2): IR - Enable auto-increment of [m]instret[h] CSR when set (r/w) */
362 41 zero_gravi 
};
363 
 
364 
 
365 
/**********************************************************************//**
366 2 zero_gravi 
 * CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.)
367 
 **************************************************************************/
368 42 zero_gravi 
enum NEORV32_CSR_MIE_enum {
369 48 zero_gravi 
  CSR_MIE_MSIE    =  3, /**< CPU mie CSR  (3): MSIE - Machine software interrupt enable (r/w) */
370 
  CSR_MIE_MTIE    =  7, /**< CPU mie CSR  (7): MTIE - Machine timer interrupt enable bit (r/w) */
371 
  CSR_MIE_MEIE    = 11, /**< CPU mie CSR (11): MEIE - Machine external interrupt enable bit (r/w) */
372 
 
373 
  CSR_MIE_FIRQ0E  = 16, /**< CPU mie CSR (16): FIRQ0E - Fast interrupt channel 0 enable bit (r/w) */
374 
  CSR_MIE_FIRQ1E  = 17, /**< CPU mie CSR (17): FIRQ1E - Fast interrupt channel 1 enable bit (r/w) */
375 
  CSR_MIE_FIRQ2E  = 18, /**< CPU mie CSR (18): FIRQ2E - Fast interrupt channel 2 enable bit (r/w) */
376 
  CSR_MIE_FIRQ3E  = 19, /**< CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w) */
377 
  CSR_MIE_FIRQ4E  = 20, /**< CPU mie CSR (20): FIRQ4E - Fast interrupt channel 4 enable bit (r/w) */
378 
  CSR_MIE_FIRQ5E  = 21, /**< CPU mie CSR (21): FIRQ5E - Fast interrupt channel 5 enable bit (r/w) */
379 
  CSR_MIE_FIRQ6E  = 22, /**< CPU mie CSR (22): FIRQ6E - Fast interrupt channel 6 enable bit (r/w) */
380 
  CSR_MIE_FIRQ7E  = 23, /**< CPU mie CSR (23): FIRQ7E - Fast interrupt channel 7 enable bit (r/w) */
381 
  CSR_MIE_FIRQ8E  = 24, /**< CPU mie CSR (24): FIRQ8E - Fast interrupt channel 8 enable bit (r/w) */
382 
  CSR_MIE_FIRQ9E  = 25, /**< CPU mie CSR (25): FIRQ9E - Fast interrupt channel 9 enable bit (r/w) */
383 
  CSR_MIE_FIRQ10E = 26, /**< CPU mie CSR (26): FIRQ10E - Fast interrupt channel 10 enable bit (r/w) */
384 
  CSR_MIE_FIRQ11E = 27, /**< CPU mie CSR (27): FIRQ11E - Fast interrupt channel 11 enable bit (r/w) */
385 
  CSR_MIE_FIRQ12E = 28, /**< CPU mie CSR (28): FIRQ12E - Fast interrupt channel 12 enable bit (r/w) */
386 
  CSR_MIE_FIRQ13E = 29, /**< CPU mie CSR (29): FIRQ13E - Fast interrupt channel 13 enable bit (r/w) */
387 
  CSR_MIE_FIRQ14E = 30, /**< CPU mie CSR (30): FIRQ14E - Fast interrupt channel 14 enable bit (r/w) */
388 
  CSR_MIE_FIRQ15E = 31  /**< CPU mie CSR (31): FIRQ15E - Fast interrupt channel 15 enable bit (r/w) */
389 2 zero_gravi 
};
390 
 
391 
 
392 
/**********************************************************************//**
393 12 zero_gravi 
 * CPU <b>mip</b> CSR (r/-): Machine interrupt pending (RISC-V spec.)
394 2 zero_gravi 
 **************************************************************************/
395 42 zero_gravi 
enum NEORV32_CSR_MIP_enum {
396 48 zero_gravi 
  CSR_MIP_MSIP    =  3, /**< CPU mip CSR  (3): MSIP - Machine software interrupt pending (r/-) */
397 
  CSR_MIP_MTIP    =  7, /**< CPU mip CSR  (7): MTIP - Machine timer interrupt pending (r/-) */
398 
  CSR_MIP_MEIP    = 11, /**< CPU mip CSR (11): MEIP - Machine external interrupt pending (r/-) */
399 14 zero_gravi 
 
400 48 zero_gravi 
  CSR_MIP_FIRQ0P  = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/-) */
401 
  CSR_MIP_FIRQ1P  = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/-) */
402 
  CSR_MIP_FIRQ2P  = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/-) */
403 
  CSR_MIP_FIRQ3P  = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */
404 
  CSR_MIP_FIRQ4P  = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/-) */
405 
  CSR_MIP_FIRQ5P  = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/-) */
406 
  CSR_MIP_FIRQ6P  = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/-) */
407 
  CSR_MIP_FIRQ7P  = 23, /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/-) */
408 
 
409 
  CSR_MIP_FIRQ8P  = 24, /**< CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/-) */
410 
  CSR_MIP_FIRQ9P  = 25, /**< CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/-) */
411 
  CSR_MIP_FIRQ10P = 26, /**< CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/-) */
412 
  CSR_MIP_FIRQ11P = 27, /**< CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/-) */
413 
  CSR_MIP_FIRQ12P = 28, /**< CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/-) */
414 
  CSR_MIP_FIRQ13P = 29, /**< CPU mip CSR (29): FIRQ13P - Fast interrupt channel 13 pending (r/-) */
415 
  CSR_MIP_FIRQ14P = 30, /**< CPU mip CSR (30): FIRQ14P - Fast interrupt channel 14 pending (r/-) */
416 
  CSR_MIP_FIRQ15P = 31  /**< CPU mip CSR (31): FIRQ15P - Fast interrupt channel 15 pending (r/-) */
417 2 zero_gravi 
};
418 
 
419 
 
420 
/**********************************************************************//**
421 16 zero_gravi 
 * CPU <b>misa</b> CSR (r/-): Machine instruction set extensions (RISC-V spec.)
422 6 zero_gravi 
 **************************************************************************/
423 42 zero_gravi 
enum NEORV32_CSR_MISA_enum {
424 
  CSR_MISA_A_EXT      =  0, /**< CPU misa CSR  (0): A: Atomic instructions CPU extension available (r/-)*/
425 
  CSR_MISA_B_EXT      =  1, /**< CPU misa CSR  (1): B: Bit manipulation CPU extension available (r/-)*/
426 
  CSR_MISA_C_EXT      =  2, /**< CPU misa CSR  (2): C: Compressed instructions CPU extension available (r/-)*/
427 52 zero_gravi 
  CSR_MISA_D_EXT      =  3, /**< CPU misa CSR  (3): D: Double-precision floating-point extension available (r/-)*/
428 42 zero_gravi 
  CSR_MISA_E_EXT      =  4, /**< CPU misa CSR  (4): E: Embedded CPU extension available (r/-) */
429 52 zero_gravi 
  CSR_MISA_F_EXT      =  5, /**< CPU misa CSR  (5): F: Single-precision floating-point extension available (r/-)*/
430 42 zero_gravi 
  CSR_MISA_I_EXT      =  8, /**< CPU misa CSR  (8): I: Base integer ISA CPU extension available (r/-) */
431 
  CSR_MISA_M_EXT      = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
432 
  CSR_MISA_U_EXT      = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
433 
  CSR_MISA_X_EXT      = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
434 
  CSR_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
435 
  CSR_MISA_MXL_HI_EXT = 31  /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
436 6 zero_gravi 
};
437 
 
438 
 
439 
/**********************************************************************//**
440 33 zero_gravi 
 * CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
441 
 **************************************************************************/
442 42 zero_gravi 
enum NEORV32_CSR_MZEXT_enum {
443 
  CSR_MZEXT_ZICSR    = 0, /**< CPU mzext CSR (0): Zicsr extension available when set (r/-) */
444 44 zero_gravi 
  CSR_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension available when set (r/-) */
445 51 zero_gravi 
  CSR_MZEXT_ZBB      = 2, /**< CPU mzext CSR (2): Zbb extension available when set (r/-) */
446 
  CSR_MZEXT_ZBS      = 3  /**< CPU mzext CSR (3): Zbs extension available when set (r/-) */
447 33 zero_gravi 
};
448 
 
449 
 
450 
/**********************************************************************//**
451 42 zero_gravi 
 * CPU <b>mhpmevent</b> hardware performance monitor events
452 
 **************************************************************************/
453 
enum NEORV32_HPMCNT_EVENT_enum {
454 
  HPMCNT_EVENT_CY      = 0,  /**< CPU mhpmevent CSR (0):  Active cycle */
455 
  HPMCNT_EVENT_IR      = 2,  /**< CPU mhpmevent CSR (2):  Retired instruction */
456 
 
457 
  HPMCNT_EVENT_CIR     = 3,  /**< CPU mhpmevent CSR (3):  Retired compressed instruction */
458 
  HPMCNT_EVENT_WAIT_IF = 4,  /**< CPU mhpmevent CSR (4):  Instruction fetch memory wait cycle */
459 
  HPMCNT_EVENT_WAIT_II = 5,  /**< CPU mhpmevent CSR (5):  Instruction issue wait cycle */
460 45 zero_gravi 
  HPMCNT_EVENT_WAIT_MC = 6,  /**< CPU mhpmevent CSR (6):  Multi-cycle ALU-operation wait cycle */
461 
  HPMCNT_EVENT_LOAD    = 7,  /**< CPU mhpmevent CSR (7):  Load operation */
462 
  HPMCNT_EVENT_STORE   = 8,  /**< CPU mhpmevent CSR (8):  Store operation */
463 
  HPMCNT_EVENT_WAIT_LS = 9,  /**< CPU mhpmevent CSR (9):  Load/store memory wait cycle */
464 42 zero_gravi 
 
465 45 zero_gravi 
  HPMCNT_EVENT_JUMP    = 10, /**< CPU mhpmevent CSR (10): Unconditional jump */
466 
  HPMCNT_EVENT_BRANCH  = 11, /**< CPU mhpmevent CSR (11): Conditional branch (taken or not taken) */
467 
  HPMCNT_EVENT_TBRANCH = 12, /**< CPU mhpmevent CSR (12): Conditional taken branch */
468 42 zero_gravi 
 
469 45 zero_gravi 
  HPMCNT_EVENT_TRAP    = 13, /**< CPU mhpmevent CSR (13): Entered trap */
470 
  HPMCNT_EVENT_ILLEGAL = 14  /**< CPU mhpmevent CSR (14): Illegal instruction exception */
471 42 zero_gravi 
};
472 
 
473 
 
474 
/**********************************************************************//**
475 14 zero_gravi 
 * Trap codes from mcause CSR.
476 2 zero_gravi 
 **************************************************************************/
477 12 zero_gravi 
enum NEORV32_EXCEPTION_CODES_enum {
478 31 zero_gravi 
  TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0:  Instruction address misaligned */
479 
  TRAP_CODE_I_ACCESS     = 0x00000001, /**< 0.1:  Instruction (bus) access fault */
480 
  TRAP_CODE_I_ILLEGAL    = 0x00000002, /**< 0.2:  Illegal instruction */
481 
  TRAP_CODE_BREAKPOINT   = 0x00000003, /**< 0.3:  Breakpoint (EBREAK instruction) */
482 
  TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4:  Load address misaligned */
483 
  TRAP_CODE_L_ACCESS     = 0x00000005, /**< 0.5:  Load (bus) access fault */
484 
  TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6:  Store address misaligned */
485 
  TRAP_CODE_S_ACCESS     = 0x00000007, /**< 0.7:  Store (bus) access fault */
486 40 zero_gravi 
  TRAP_CODE_UENV_CALL    = 0x00000008, /**< 0.8:  Environment call from user mode (ECALL instruction) */
487 14 zero_gravi 
  TRAP_CODE_MENV_CALL    = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */
488 40 zero_gravi 
  TRAP_CODE_RESET        = 0x80000000, /**< 1.0:  Hardware reset */
489 31 zero_gravi 
  TRAP_CODE_MSI          = 0x80000003, /**< 1.3:  Machine software interrupt */
490 
  TRAP_CODE_MTI          = 0x80000007, /**< 1.7:  Machine timer interrupt */
491 14 zero_gravi 
  TRAP_CODE_MEI          = 0x8000000b, /**< 1.11: Machine external interrupt */
492 
  TRAP_CODE_FIRQ_0       = 0x80000010, /**< 1.16: Fast interrupt channel 0 */
493 
  TRAP_CODE_FIRQ_1       = 0x80000011, /**< 1.17: Fast interrupt channel 1 */
494 
  TRAP_CODE_FIRQ_2       = 0x80000012, /**< 1.18: Fast interrupt channel 2 */
495 47 zero_gravi 
  TRAP_CODE_FIRQ_3       = 0x80000013, /**< 1.19: Fast interrupt channel 3 */
496 
  TRAP_CODE_FIRQ_4       = 0x80000014, /**< 1.20: Fast interrupt channel 4 */
497 
  TRAP_CODE_FIRQ_5       = 0x80000015, /**< 1.21: Fast interrupt channel 5 */
498 
  TRAP_CODE_FIRQ_6       = 0x80000016, /**< 1.22: Fast interrupt channel 6 */
499 48 zero_gravi 
  TRAP_CODE_FIRQ_7       = 0x80000017, /**< 1.23: Fast interrupt channel 7 */
500 
  TRAP_CODE_FIRQ_8       = 0x80000018, /**< 1.24: Fast interrupt channel 8 */
501 
  TRAP_CODE_FIRQ_9       = 0x80000019, /**< 1.25: Fast interrupt channel 9 */
502 
  TRAP_CODE_FIRQ_10      = 0x8000001a, /**< 1.26: Fast interrupt channel 10 */
503 
  TRAP_CODE_FIRQ_11      = 0x8000001b, /**< 1.27: Fast interrupt channel 11 */
504 
  TRAP_CODE_FIRQ_12      = 0x8000001c, /**< 1.28: Fast interrupt channel 12 */
505 
  TRAP_CODE_FIRQ_13      = 0x8000001d, /**< 1.29: Fast interrupt channel 13 */
506 
  TRAP_CODE_FIRQ_14      = 0x8000001e, /**< 1.30: Fast interrupt channel 14 */
507 
  TRAP_CODE_FIRQ_15      = 0x8000001f  /**< 1.31: Fast interrupt channel 15 */
508 12 zero_gravi 
};
509 
 
510 
 
511 
/**********************************************************************//**
512 52 zero_gravi 
 * Processor clock prescalers select
513 2 zero_gravi 
 **************************************************************************/
514 
enum NEORV32_CLOCK_PRSC_enum {
515 47 zero_gravi 
  CLK_PRSC_2    = 0, /**< CPU_CLK (from clk_i top signal) / 2 */
516 
  CLK_PRSC_4    = 1, /**< CPU_CLK (from clk_i top signal) / 4 */
517 
  CLK_PRSC_8    = 2, /**< CPU_CLK (from clk_i top signal) / 8 */
518 
  CLK_PRSC_64   = 3, /**< CPU_CLK (from clk_i top signal) / 64 */
519 
  CLK_PRSC_128  = 4, /**< CPU_CLK (from clk_i top signal) / 128 */
520 
  CLK_PRSC_1024 = 5, /**< CPU_CLK (from clk_i top signal) / 1024 */
521 
  CLK_PRSC_2048 = 6, /**< CPU_CLK (from clk_i top signal) / 2048 */
522 
  CLK_PRSC_4096 = 7  /**< CPU_CLK (from clk_i top signal) / 4096 */
523 2 zero_gravi 
};
524 
 
525 
 
526 
/**********************************************************************//**
527 34 zero_gravi 
 * Official NEORV32 >RISC-V open-source architecture ID<
528 
 * https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
529 32 zero_gravi 
 **************************************************************************/
530 
#define NEORV32_ARCHID 19
531 
 
532 
 
533 
/**********************************************************************//**
534 2 zero_gravi 
 * @name Helper macros for easy memory-mapped register access
535 
 **************************************************************************/
536 
/**@{*/
537 
/** memory-mapped byte (8-bit) read/write register */
538 
#define IO_REG8  (volatile uint8_t*)
539 
/** memory-mapped half-word (16-bit) read/write register */
540 
#define IO_REG16 (volatile uint16_t*)
541 
/** memory-mapped word (32-bit) read/write register */
542 
#define IO_REG32 (volatile uint32_t*)
543 
/** memory-mapped double-word (64-bit) read/write register */
544 
#define IO_REG64 (volatile uint64_t*)
545 
/** memory-mapped byte (8-bit) read-only register */
546 
#define IO_ROM8  (const volatile uint8_t*)
547 
/** memory-mapped half-word (16-bit) read-only register */
548 
#define IO_ROM16 (const volatile uint16_t*)
549 
/** memory-mapped word (32-bit) read-only register */
550 
#define IO_ROM32 (const volatile uint32_t*)
551 
/** memory-mapped double-word (64-bit) read-only register */
552 
#define IO_ROM64 (const volatile uint64_t*)
553 
/**@}*/
554 
 
555 
 
556 
/**********************************************************************//**
557 
 * @name Address space sections
558 
 **************************************************************************/
559 
/**@{*/
560 
/** instruction memory base address (r/w/x) */
561 23 zero_gravi 
// -> configured via ispace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
562 2 zero_gravi 
/** data memory base address (r/w/x) */
563 23 zero_gravi 
// -> configured via dspace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
564 2 zero_gravi 
/** bootloader memory base address (r/-/x) */
565 6 zero_gravi 
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
566 2 zero_gravi 
/** peripheral/IO devices memory base address (r/w/x) */
567 47 zero_gravi 
#define IO_BASE_ADDRESS (0xFFFFFF00UL)
568 2 zero_gravi 
/**@}*/
569 
 
570 
 
571 
/**********************************************************************//**
572 47 zero_gravi 
 * @name IO Device: Custom Functions Subsystem (CFS)
573 
 **************************************************************************/
574 
/**@{*/
575 
/** custom CFS register 0 */
576 
#define CFS_REG_0  (*(IO_REG32 0xFFFFFF00UL)) // /**< (r)/(w): CFS register 0, user-defined */
577 
/** custom CFS register 1 */
578 
#define CFS_REG_1  (*(IO_REG32 0xFFFFFF04UL)) // /**< (r)/(w): CFS register 1, user-defined */
579 
/** custom CFS register 2 */
580 
#define CFS_REG_2  (*(IO_REG32 0xFFFFFF08UL)) // /**< (r)/(w): CFS register 2, user-defined */
581 
/** custom CFS register 3 */
582 
#define CFS_REG_3  (*(IO_REG32 0xFFFFFF0CUL)) // /**< (r)/(w): CFS register 3, user-defined */
583 
/** custom CFS register 4 */
584 
#define CFS_REG_4  (*(IO_REG32 0xFFFFFF10UL)) // /**< (r)/(w): CFS register 4, user-defined */
585 
/** custom CFS register 5 */
586 
#define CFS_REG_5  (*(IO_REG32 0xFFFFFF14UL)) // /**< (r)/(w): CFS register 5, user-defined */
587 
/** custom CFS register 6 */
588 
#define CFS_REG_6  (*(IO_REG32 0xFFFFFF18UL)) // /**< (r)/(w): CFS register 6, user-defined */
589 
/** custom CFS register 7 */
590 
#define CFS_REG_7  (*(IO_REG32 0xFFFFFF1CUL)) // /**< (r)/(w): CFS register 7, user-defined */
591 
/** custom CFS register 8 */
592 
#define CFS_REG_8  (*(IO_REG32 0xFFFFFF20UL)) // /**< (r)/(w): CFS register 8, user-defined */
593 
/** custom CFS register 9 */
594 
#define CFS_REG_9  (*(IO_REG32 0xFFFFFF24UL)) // /**< (r)/(w): CFS register 9, user-defined */
595 
/** custom CFS register 10 */
596 
#define CFS_REG_10 (*(IO_REG32 0xFFFFFF28UL)) // /**< (r)/(w): CFS register 10, user-defined */
597 
/** custom CFS register 11 */
598 
#define CFS_REG_11 (*(IO_REG32 0xFFFFFF2CUL)) // /**< (r)/(w): CFS register 11, user-defined */
599 
/** custom CFS register 12 */
600 
#define CFS_REG_12 (*(IO_REG32 0xFFFFFF30UL)) // /**< (r)/(w): CFS register 12, user-defined */
601 
/** custom CFS register 13 */
602 
#define CFS_REG_13 (*(IO_REG32 0xFFFFFF34UL)) // /**< (r)/(w): CFS register 13, user-defined */
603 
/** custom CFS register 14 */
604 
#define CFS_REG_14 (*(IO_REG32 0xFFFFFF38UL)) // /**< (r)/(w): CFS register 14, user-defined */
605 
/** custom CFS register 15 */
606 
#define CFS_REG_15 (*(IO_REG32 0xFFFFFF3CUL)) // /**< (r)/(w): CFS register 15, user-defined */
607 
/** custom CFS register 16 */
608 
#define CFS_REG_16 (*(IO_REG32 0xFFFFFF40UL)) // /**< (r)/(w): CFS register 16, user-defined */
609 
/** custom CFS register 17 */
610 
#define CFS_REG_17 (*(IO_REG32 0xFFFFFF44UL)) // /**< (r)/(w): CFS register 17, user-defined */
611 
/** custom CFS register 18 */
612 
#define CFS_REG_18 (*(IO_REG32 0xFFFFFF48UL)) // /**< (r)/(w): CFS register 18, user-defined */
613 
/** custom CFS register 19 */
614 
#define CFS_REG_19 (*(IO_REG32 0xFFFFFF4CUL)) // /**< (r)/(w): CFS register 19, user-defined */
615 
/** custom CFS register 20 */
616 
#define CFS_REG_20 (*(IO_REG32 0xFFFFFF50UL)) // /**< (r)/(w): CFS register 20, user-defined */
617 
/** custom CFS register 21 */
618 
#define CFS_REG_21 (*(IO_REG32 0xFFFFFF54UL)) // /**< (r)/(w): CFS register 21, user-defined */
619 
/** custom CFS register 22 */
620 
#define CFS_REG_22 (*(IO_REG32 0xFFFFFF58UL)) // /**< (r)/(w): CFS register 22, user-defined */
621 
/** custom CFS register 23 */
622 
#define CFS_REG_23 (*(IO_REG32 0xFFFFFF5CUL)) // /**< (r)/(w): CFS register 23, user-defined */
623 
/** custom CFS register 24 */
624 
#define CFS_REG_24 (*(IO_REG32 0xFFFFFF60UL)) // /**< (r)/(w): CFS register 24, user-defined */
625 
/** custom CFS register 25 */
626 
#define CFS_REG_25 (*(IO_REG32 0xFFFFFF64UL)) // /**< (r)/(w): CFS register 25, user-defined */
627 
/** custom CFS register 26 */
628 
#define CFS_REG_26 (*(IO_REG32 0xFFFFFF68UL)) // /**< (r)/(w): CFS register 26, user-defined */
629 
/** custom CFS register 27 */
630 
#define CFS_REG_27 (*(IO_REG32 0xFFFFFF6CUL)) // /**< (r)/(w): CFS register 27, user-defined */
631 
/** custom CFS register 28 */
632 
#define CFS_REG_28 (*(IO_REG32 0xFFFFFF70UL)) // /**< (r)/(w): CFS register 28, user-defined */
633 
/** custom CFS register 29 */
634 
#define CFS_REG_29 (*(IO_REG32 0xFFFFFF74UL)) // /**< (r)/(w): CFS register 29, user-defined */
635 
/** custom CFS register 30 */
636 
#define CFS_REG_30 (*(IO_REG32 0xFFFFFF78UL)) // /**< (r)/(w): CFS register 30, user-defined */
637 
/** custom CFS register 31 */
638 
#define CFS_REG_31 (*(IO_REG32 0xFFFFFF7CUL)) // /**< (r)/(w): CFS register 31, user-defined */
639 
/**@}*/
640 
 
641 
 
642 
/**********************************************************************//**
643 2 zero_gravi 
 * @name IO Device: General Purpose Input/Output Port Unit (GPIO)
644 
 **************************************************************************/
645 
/**@{*/
646 23 zero_gravi 
/** read access: GPIO parallel input port 32-bit (r/-), write_access: pin-change IRQ for each input pin (-/w) */
647 
#define GPIO_INPUT  (*(IO_REG32 0xFFFFFF80UL))
648 22 zero_gravi 
/** GPIO parallel output port 32-bit (r/w) */
649 6 zero_gravi 
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
650 2 zero_gravi 
/**@}*/
651 
 
652 
 
653 
/**********************************************************************//**
654 30 zero_gravi 
 * @name IO Device: True Random Number Generator (TRNG)
655 18 zero_gravi 
 **************************************************************************/
656 
/**@{*/
657 30 zero_gravi 
/** TRNG control/data register (r/w) */
658 
#define TRNG_CT (*(IO_REG32 0xFFFFFF88UL))
659 
 
660 
/** TRNG control/data register bits */
661 
enum NEORV32_TRNG_CT_enum {
662 47 zero_gravi 
  TRNG_CT_DATA_LSB =  0, /**< TRNG data/control register(0)  (r/-): Random data byte LSB */
663 
  TRNG_CT_DATA_MSB =  7, /**< TRNG data/control register(7)  (r/-): Random data byte MSB */
664 
 
665 
  TRNG_CT_EN       = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */
666 
  TRNG_CT_VALID    = 31  /**< TRNG data/control register(31) (r/-): Random data output valid */
667 30 zero_gravi 
};
668 18 zero_gravi 
/**@}*/
669 
 
670 
 
671 
/**********************************************************************//**
672 2 zero_gravi 
 * @name IO Device: Watchdog Timer (WDT)
673 
 **************************************************************************/
674 
/**@{*/
675 
/** Watchdog control register (r/w) */
676 6 zero_gravi 
#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL))
677 2 zero_gravi 
 
678 
/** WTD control register bits */
679 
enum NEORV32_WDT_CT_enum {
680 47 zero_gravi 
  WDT_CT_EN       = 0, /**< WDT control register(0) (r/w): Watchdog enable */
681 
  WDT_CT_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */
682 
  WDT_CT_CLK_SEL1 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 1 */
683 
  WDT_CT_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */
684 
  WDT_CT_MODE     = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */
685 
  WDT_CT_RCAUSE   = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */
686 
  WDT_CT_RESET    = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */
687 
  WDT_CT_FORCE    = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */
688 
  WDT_CT_LOCK     = 8  /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */
689 2 zero_gravi 
};
690 
/**@}*/
691 
 
692 
 
693 
/**********************************************************************//**
694 
 * @name IO Device: Machine System Timer (MTIME)
695 
 **************************************************************************/
696 
/**@{*/
697 11 zero_gravi 
/** MTIME (time register) low word (r/w) */
698 
#define MTIME_LO     (*(IO_REG32 0xFFFFFF90UL))
699 
/** MTIME (time register) high word (r/w) */
700 
#define MTIME_HI     (*(IO_REG32 0xFFFFFF94UL))
701 2 zero_gravi 
/** MTIMECMP (time compare register) low word (r/w) */
702 6 zero_gravi 
#define MTIMECMP_LO  (*(IO_REG32 0xFFFFFF98UL))
703 2 zero_gravi 
/** MTIMECMP (time register) high word (r/w) */
704 6 zero_gravi 
#define MTIMECMP_HI  (*(IO_REG32 0xFFFFFF9CUL))
705 2 zero_gravi 
 
706 11 zero_gravi 
/** MTIME (time register) 64-bit access (r/w) */
707 
#define MTIME        (*(IO_REG64 (&MTIME_LO)))
708 2 zero_gravi 
/** MTIMECMP (time compare register) low word (r/w) */
709 
#define MTIMECMP     (*(IO_REG64 (&MTIMECMP_LO)))
710 
/**@}*/
711 
 
712 
 
713 
/**********************************************************************//**
714 50 zero_gravi 
 * @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1)
715 2 zero_gravi 
 **************************************************************************/
716 
/**@{*/
717 50 zero_gravi 
/** UART0 control register (r/w) */
718 
#define UART0_CT  (*(IO_REG32 0xFFFFFFA0UL))
719 
/** UART0 receive/transmit data register (r/w) */
720 
#define UART0_DATA (*(IO_REG32 0xFFFFFFA4UL))
721 2 zero_gravi 
 
722 50 zero_gravi 
/** UART1 control register (r/w) */
723 
#define UART1_CT  (*(IO_REG32 0xFFFFFFD0UL))
724 
/** UART1 receive/transmit data register (r/w) */
725 
#define UART1_DATA (*(IO_REG32 0xFFFFFFD4UL))
726 
 
727 
/** UART0/UART1 control register bits */
728 2 zero_gravi 
enum NEORV32_UART_CT_enum {
729 50 zero_gravi 
  UART_CT_BAUD00   =  0, /**< UART control register(0)  (r/w): BAUD rate config value lsb (12-bit, bit 0) */
730 
  UART_CT_BAUD01   =  1, /**< UART control register(1)  (r/w): BAUD rate config value (12-bit, bit 1) */
731 
  UART_CT_BAUD02   =  2, /**< UART control register(2)  (r/w): BAUD rate config value (12-bit, bit 2) */
732 
  UART_CT_BAUD03   =  3, /**< UART control register(3)  (r/w): BAUD rate config value (12-bit, bit 3) */
733 
  UART_CT_BAUD04   =  4, /**< UART control register(4)  (r/w): BAUD rate config value (12-bit, bit 4) */
734 
  UART_CT_BAUD05   =  5, /**< UART control register(5)  (r/w): BAUD rate config value (12-bit, bit 4) */
735 
  UART_CT_BAUD06   =  6, /**< UART control register(6)  (r/w): BAUD rate config value (12-bit, bit 5) */
736 
  UART_CT_BAUD07   =  7, /**< UART control register(7)  (r/w): BAUD rate config value (12-bit, bit 6) */
737 
  UART_CT_BAUD08   =  8, /**< UART control register(8)  (r/w): BAUD rate config value (12-bit, bit 7) */
738 
  UART_CT_BAUD09   =  9, /**< UART control register(9)  (r/w): BAUD rate config value (12-bit, bit 8) */
739 
  UART_CT_BAUD10   = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bit, bit 9) */
740 
  UART_CT_BAUD11   = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bit, bit 0) */
741 30 zero_gravi 
  UART_CT_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */
742 
 
743 51 zero_gravi 
  UART_CT_RTS_EN   = 20, /**< UART control register(20) (r/w): Enable hardware flow control: Assert RTS output if UART.RX is ready to receive */
744 
  UART_CT_CTS_EN   = 21, /**< UART control register(21) (r/w): Enable hardware flow control: UART.TX starts sending only if CTS input is asserted */
745 42 zero_gravi 
  UART_CT_PMODE0   = 22, /**< UART control register(22) (r/w): Parity configuration (0=even; 1=odd) */
746 
  UART_CT_PMODE1   = 23, /**< UART control register(23) (r/w): Parity bit enabled when set */
747 30 zero_gravi 
  UART_CT_PRSC0    = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
748 
  UART_CT_PRSC1    = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
749 
  UART_CT_PRSC2    = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
750 51 zero_gravi 
  UART_CT_CTS      = 27, /**< UART control register(27) (r/-): current state of CTS input */
751 
  UART_CT_EN       = 28, /**< UART control register(28) (r/w): UART global enable */
752 42 zero_gravi 
 
753 30 zero_gravi 
  UART_CT_TX_BUSY  = 31  /**< UART control register(31) (r/-): Transmitter is busy when set */
754 2 zero_gravi 
};
755 
 
756 51 zero_gravi 
/** UART0/UART1 parity configuration */
757 
enum NEORV32_UART_PARITY_enum {
758 
  PARITY_NONE = 0b00, /**< 0b00: No parity bit at all */
759 
  PARITY_EVEN = 0b10, /**< 0b10: Even parity */
760 
  PARITY_ODD  = 0b11  /**< 0b11: Odd parity */
761 
};
762 
 
763 
/** UART0/UART1 hardware flow control configuration */
764 
enum NEORV32_UART_FLOW_CONTROL_enum {
765 
  FLOW_CONTROL_NONE   = 0b00, /**< 0b00: No hardware flow control */
766 
  FLOW_CONTROL_RTS    = 0b01, /**< 0b01: Assert RTS output if UART.RX is ready to receive */
767 
  FLOW_CONTROL_CTS    = 0b10, /**< 0b10: UART.TX starts sending only if CTS input is asserted */
768 
  FLOW_CONTROL_RTSCTS = 0b11  /**< 0b11: Assert RTS output if UART.RX is ready to receive & UART.TX starts sending only if CTS input is asserted */
769 
};
770 
 
771 50 zero_gravi 
/** UART0/UART1 receive/transmit data register bits */
772 2 zero_gravi 
enum NEORV32_UART_DATA_enum {
773 
  UART_DATA_LSB   =  0, /**< UART receive/transmit data register(0)  (r/w): Receive/transmit data LSB (bit 0) */
774 
  UART_DATA_MSB   =  7, /**< UART receive/transmit data register(7)  (r/w): Receive/transmit data MSB (bit 7) */
775 47 zero_gravi 
 
776 42 zero_gravi 
  UART_DATA_PERR  = 28, /**< UART receive/transmit data register(18) (r/-): RX parity error detected when set */
777 
  UART_DATA_FERR  = 29, /**< UART receive/transmit data register(29) (r/-): RX frame error (not valid stop bit) wdetected when set */
778 
  UART_DATA_OVERR = 30, /**< UART receive/transmit data register(30) (r/-): RX data overrun when set */
779 
  UART_DATA_AVAIL = 31  /**< UART receive/transmit data register(31) (r/-): RX data available when set  */
780 2 zero_gravi 
};
781 
/**@}*/
782 
 
783 
 
784 
/**********************************************************************//**
785 10 zero_gravi 
 * @name IO Device: Serial Peripheral Interface Controller (SPI)
786 2 zero_gravi 
 **************************************************************************/
787 
/**@{*/
788 
/** SPI control register (r/w) */
789 6 zero_gravi 
#define SPI_CT  (*(IO_REG32 0xFFFFFFA8UL))
790 2 zero_gravi 
/** SPI receive/transmit data register (r/w) */
791 6 zero_gravi 
#define SPI_DATA (*(IO_REG32 0xFFFFFFACUL))
792 2 zero_gravi 
 
793 
/** SPI control register bits */
794 
enum NEORV32_SPI_CT_enum {
795 51 zero_gravi 
  SPI_CT_CS0    =  0, /**< UART control register(0)  (r/w): Direct chip select line 0 (output is low when set) */
796 
  SPI_CT_CS1    =  1, /**< UART control register(1)  (r/w): Direct chip select line 1 (output is low when set) */
797 
  SPI_CT_CS2    =  2, /**< UART control register(2)  (r/w): Direct chip select line 2 (output is low when set) */
798 
  SPI_CT_CS3    =  3, /**< UART control register(3)  (r/w): Direct chip select line 3 (output is low when set) */
799 
  SPI_CT_CS4    =  4, /**< UART control register(4)  (r/w): Direct chip select line 4 (output is low when set) */
800 
  SPI_CT_CS5    =  5, /**< UART control register(5)  (r/w): Direct chip select line 5 (output is low when set) */
801 
  SPI_CT_CS6    =  6, /**< UART control register(6)  (r/w): Direct chip select line 6 (output is low when set) */
802 
  SPI_CT_CS7    =  7, /**< UART control register(7)  (r/w): Direct chip select line 7 (output is low when set) */
803 
  SPI_CT_EN     =  8, /**< UART control register(8)  (r/w): SPI unit enable */
804 
  SPI_CT_CPHA   =  9, /**< UART control register(9)  (r/w): Clock polarity (idle polarity) */
805 2 zero_gravi 
  SPI_CT_PRSC0  = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */
806 
  SPI_CT_PRSC1  = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */
807 
  SPI_CT_PRSC2  = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */
808 36 zero_gravi 
  SPI_CT_SIZE0  = 13, /**< UART control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
809 
  SPI_CT_SIZE1  = 14, /**< UART control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
810 2 zero_gravi 
 
811 
  SPI_CT_BUSY   = 31  /**< UART control register(31) (r/-): SPI busy flag */
812 
};
813 
/**@}*/
814 
 
815 
 
816 
/**********************************************************************//**
817 10 zero_gravi 
 * @name IO Device: Two-Wire Interface Controller (TWI)
818 2 zero_gravi 
 **************************************************************************/
819 
/**@{*/
820 
/** TWI control register (r/w) */
821 6 zero_gravi 
#define TWI_CT   (*(IO_REG32 0xFFFFFFB0UL))
822 2 zero_gravi 
/** TWI receive/transmit data register (r/w) */
823 6 zero_gravi 
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4UL))
824 2 zero_gravi 
 
825 
/** TWI control register bits */
826 
enum NEORV32_TWI_CT_enum {
827 
  TWI_CT_EN     =  0, /**< TWI control register(0) (r/w): TWI enable */
828 
  TWI_CT_START  =  1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
829 
  TWI_CT_STOP   =  2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
830 48 zero_gravi 
  TWI_CT_PRSC0  =  3, /**< TWI control register(3) (r/w): Clock prescaler select bit 0 */
831 
  TWI_CT_PRSC1  =  4, /**< TWI control register(4) (r/w): Clock prescaler select bit 1 */
832 
  TWI_CT_PRSC2  =  5, /**< TWI control register(5) (r/w): Clock prescaler select bit 2 */
833 
  TWI_CT_MACK   =  6, /**< TWI control register(6) (r/w): Generate controller ACK for each transmission */
834 
  TWI_CT_CKSTEN =  7, /**< TWI control register(7) (r/w): Enable clock stretching (by peripheral) */
835 2 zero_gravi 
 
836 
  TWI_CT_ACK    = 30, /**< TWI control register(30) (r/-): ACK received when set */
837 
  TWI_CT_BUSY   = 31  /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
838 
};
839 
 
840 
/** WTD receive/transmit data register bits */
841 
enum NEORV32_TWI_DATA_enum {
842 
  TWI_DATA_LSB = 0, /**< TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB */
843 
  TWI_DATA_MSB = 7  /**< TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB */
844 
};
845 
/**@}*/
846 
 
847 
 
848 
/**********************************************************************//**
849 
 * @name IO Device: Pulse Width Modulation Controller (PWM)
850 
 **************************************************************************/
851 
/**@{*/
852 
/** PWM control register (r/w) */
853 6 zero_gravi 
#define PWM_CT   (*(IO_REG32 0xFFFFFFB8UL)) // r/w: control register
854 2 zero_gravi 
/** PWM duty cycle register (4-channels) (r/w) */
855 6 zero_gravi 
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBCUL)) // r/w: duty cycle channel 1 and 0
856 2 zero_gravi 
 
857 
/** PWM control register bits */
858 
enum NEORV32_PWM_CT_enum {
859 
  PWM_CT_EN    =  0, /**< PWM control register(0) (r/w): PWM controller enable */
860 
  PWM_CT_PRSC0 =  1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
861 
  PWM_CT_PRSC1 =  2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
862 
  PWM_CT_PRSC2 =  3  /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
863 
};
864 
 
865 
/**PWM duty cycle register bits */
866 
enum NEORV32_PWM_DUTY_enum {
867 
  PWM_DUTY_CH0_LSB =  0, /**< PWM duty cycle register(0)  (r/w): Channel 0 duty cycle (8-bit) LSB */
868 
  PWM_DUTY_CH0_MSB =  7, /**< PWM duty cycle register(7)  (r/w): Channel 0 duty cycle (8-bit) MSB */
869 
  PWM_DUTY_CH1_LSB =  8, /**< PWM duty cycle register(8)  (r/w): Channel 1 duty cycle (8-bit) LSB */
870 
  PWM_DUTY_CH1_MSB = 15, /**< PWM duty cycle register(15) (r/w): Channel 1 duty cycle (8-bit) MSB */
871 
  PWM_DUTY_CH2_LSB = 16, /**< PWM duty cycle register(16) (r/w): Channel 2 duty cycle (8-bit) LSB */
872 
  PWM_DUTY_CH2_MSB = 23, /**< PWM duty cycle register(23) (r/w): Channel 2 duty cycle (8-bit) MSB */
873 
  PWM_DUTY_CH3_LSB = 24, /**< PWM duty cycle register(24) (r/w): Channel 3 duty cycle (8-bit) LSB */
874 
  PWM_DUTY_CH3_MSB = 31  /**< PWM duty cycle register(31) (r/w): Channel 3 duty cycle (8-bit) MSB */
875 
};
876 
/**@}*/
877 
 
878 
 
879 
/**********************************************************************//**
880 49 zero_gravi 
 * @name IO Device: Numerically-Controlled Oscillator (NCO)
881 
 **************************************************************************/
882 
/**@{*/
883 
/** NCO control register (r/w) */
884 
#define NCO_CT       (*(IO_REG32 0xFFFFFFC0UL)) // r/w: control register
885 
/** NCO channel 0 tuning word (r/w) */
886 
#define NCO_TUNE_CH0 (*(IO_REG32 0xFFFFFFC4UL)) // r/w: tuning word channel 0
887 
/** NCO channel 1 tuning word (r/w) */
888 
#define NCO_TUNE_CH1 (*(IO_REG32 0xFFFFFFC8UL)) // r/w: tuning word channel 1
889 
/** NCO channel 2 tuning word (r/w) */
890 
#define NCO_TUNE_CH2 (*(IO_REG32 0xFFFFFFCCUL)) // r/w: tuning word channel 2
891 
 
892 
/** NCO control register bits */
893 
enum NEORV32_NCO_CT_enum {
894 
  NCO_CT_EN           =  0, /**< NCO control register(0) (r/w): NCO global enable */
895 
  // channel 0
896 
  NCO_CT_CH0_MODE     =  1, /**< NCO control register(1)  - channel 0 (r/w): Output mode (0=fixed 50% duty cycle; 1=pulse mode) */
897 
  NCO_CT_CH0_IDLE_POL =  2, /**< NCO control register(2)  - channel 0 (r/w): Output idle polarity (0=low, 1=high) */
898 
  NCO_CT_CH0_OE       =  3, /**< NCO control register(3)  - channel 0 (r/w): Enable processor output pin */
899 
  NCO_CT_CH0_OUTPUT   =  4, /**< NCO control register(4)  - channel 0 (r/-): Current channel output state */
900 
  NCO_CT_CH0_PRSC0    =  5, /**< NCO control register(5)  - channel 0 (r/w): Clock prescaler select bit 0 */
901 
  NCO_CT_CH0_PRSC1    =  6, /**< NCO control register(6)  - channel 0 (r/w): Clock prescaler select bit 1 */
902 
  NCO_CT_CH0_PRSC2    =  7, /**< NCO control register(7)  - channel 0 (r/w): Clock prescaler select bit 2 */
903 
  NCO_CT_CH0_PULSE0   =  8, /**< NCO control register(8)  - channel 0 (r/w): Pulse-mode: Pulse length select bit 0 */
904 
  NCO_CT_CH0_PULSE1   =  9, /**< NCO control register(9)  - channel 0 (r/w): Pulse-mode: Pulse length select bit 1 */
905 
  NCO_CT_CH0_PULSE2   = 10, /**< NCO control register(10) - channel 0 (r/w): Pulse-mode: Pulse length select bit 2 */
906 
  // channel 1
907 
  NCO_CT_CH1_MODE     = 11, /**< NCO control register(11) - channel 1 (r/w): Output mode (0=fixed 50% duty cycle; 1=pulse mode) */
908 
  NCO_CT_CH1_IDLE_POL = 12, /**< NCO control register(12) - channel 1 (r/w): Output idle polarity (0=low, 1=high) */
909 
  NCO_CT_CH1_OE       = 13, /**< NCO control register(13) - channel 1 (r/w): Enable processor output pin */
910 
  NCO_CT_CH1_OUTPUT   = 14, /**< NCO control register(14) - channel 1 (r/-): Current channel output state */
911 
  NCO_CT_CH1_PRSC0    = 15, /**< NCO control register(15) - channel 1 (r/w): Clock prescaler select bit 0 */
912 
  NCO_CT_CH1_PRSC1    = 16, /**< NCO control register(16) - channel 1 (r/w): Clock prescaler select bit 1 */
913 
  NCO_CT_CH1_PRSC2    = 17, /**< NCO control register(17) - channel 1 (r/w): Clock prescaler select bit 2 */
914 
  NCO_CT_CH1_PULSE0   = 18, /**< NCO control register(18) - channel 1 (r/w): Pulse-mode: Pulse length select bit 0 */
915 
  NCO_CT_CH1_PULSE1   = 19, /**< NCO control register(19) - channel 1 (r/w): Pulse-mode: Pulse length select bit 1 */
916 
  NCO_CT_CH1_PULSE2   = 20, /**< NCO control register(20) - channel 1 (r/w): Pulse-mode: Pulse length select bit 2 */
917 
  // channel 2
918 
  NCO_CT_CH2_MODE     = 21, /**< NCO control register(21) - channel 2 (r/w): Output mode (0=fixed 50% duty cycle; 1=pulse mode) */
919 
  NCO_CT_CH2_IDLE_POL = 22, /**< NCO control register(22) - channel 2 (r/w): Output idle polarity (0=low, 1=high) */
920 
  NCO_CT_CH2_OE       = 23, /**< NCO control register(23) - channel 2 (r/w): Enable processor output pin */
921 
  NCO_CT_CH2_OUTPUT   = 24, /**< NCO control register(24) - channel 2 (r/-): Current channel output state */
922 
  NCO_CT_CH2_PRSC0    = 25, /**< NCO control register(25) - channel 2 (r/w): Clock prescaler select bit 0 */
923 
  NCO_CT_CH2_PRSC1    = 26, /**< NCO control register(26) - channel 2 (r/w): Clock prescaler select bit 1 */
924 
  NCO_CT_CH2_PRSC2    = 27, /**< NCO control register(27) - channel 2 (r/w): Clock prescaler select bit 2 */
925 
  NCO_CT_CH2_PULSE0   = 28, /**< NCO control register(28) - channel 2 (r/w): Pulse-mode: Pulse length select bit 0 */
926 
  NCO_CT_CH2_PULSE1   = 29, /**< NCO control register(29) - channel 2 (r/w): Pulse-mode: Pulse length select bit 1 */
927 
  NCO_CT_CH2_PULSE2   = 20  /**< NCO control register(30) - channel 2 (r/w): Pulse-mode: Pulse length select bit 2 */
928 
};
929 
 
930 
/** Size of one "channel entry" in control register in bits */
931 
#define NCO_CHX_WIDTH 10 // Size of one "channel entry" in control register in bits
932 
/**@}*/
933 
 
934 
 
935 
/**********************************************************************//**
936 52 zero_gravi 
 * @name IO Device: Smart LED Hardware Interface (NEOLED)
937 
 **************************************************************************/
938 
/**@{*/
939 
/** NEOLED control register (r/w) */
940 
#define NEOLED_CT   (*(IO_REG32 0xFFFFFFD8UL)) // r/w: control register
941 
/** NEOLED TX data register (-/w) */
942 
#define NEOLED_DATA (*(IO_REG32 0xFFFFFFDCUL)) // -/w: TX data register
943 
 
944 
/** NEOLED control register bits */
945 
enum NEORV32_NEOLED_CT_enum {
946 
  NEOLED_CT_EN         =  0, /**< NEOLED control register(0) (r/w): NEOLED global enable */
947 
  NEOLED_CT_MODE       =  1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */
948 
  NEOLED_CT_BSCON      =  2, /**< NEOLED control register(2) (r/w): buffer status configuration -> busy_flag/IRQ config (0=at least one free entry, 1=whole buffer empty) */
949 
  NEOLED_CT_PRSC0      =  3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */
950 
  NEOLED_CT_PRSC1      =  4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */
951 
  NEOLED_CT_PRSC2      =  5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */
952 
  //
953 
  NEOLED_CT_BUFS_0     =  6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */
954 
  NEOLED_CT_BUFS_1     =  7, /**< NEOLED control register(7) (r/-): log2(tx buffer size) bit 1 */
955 
  NEOLED_CT_BUFS_2     =  8, /**< NEOLED control register(8) (r/-): log2(tx buffer size) bit 2 */
956 
  NEOLED_CT_BUFS_3     =  9, /**< NEOLED control register(9) (r/-): log2(tx buffer size) bit 3 */
957 
  //
958 
  NEOLED_CT_T_TOT_0    = 10, /**< NEOLED control register(10) (r/w): pulse-clock ticks per total period bit 0 */
959 
  NEOLED_CT_T_TOT_1    = 11, /**< NEOLED control register(11) (r/w): pulse-clock ticks per total period bit 1 */
960 
  NEOLED_CT_T_TOT_2    = 12, /**< NEOLED control register(12) (r/w): pulse-clock ticks per total period bit 2 */
961 
  NEOLED_CT_T_TOT_3    = 13, /**< NEOLED control register(13) (r/w): pulse-clock ticks per total period bit 3 */
962 
  NEOLED_CT_T_TOT_4    = 14, /**< NEOLED control register(14) (r/w): pulse-clock ticks per total period bit 4 */
963 
  //
964 
  NEOLED_CT_T_ZERO_H_0 = 15, /**< NEOLED control register(15) (r/w): pulse-clock ticks per ZERO high-time bit 0 */
965 
  NEOLED_CT_T_ZERO_H_1 = 16, /**< NEOLED control register(16) (r/w): pulse-clock ticks per ZERO high-time bit 1 */
966 
  NEOLED_CT_T_ZERO_H_2 = 17, /**< NEOLED control register(17) (r/w): pulse-clock ticks per ZERO high-time bit 2 */
967 
  NEOLED_CT_T_ZERO_H_3 = 18, /**< NEOLED control register(18) (r/w): pulse-clock ticks per ZERO high-time bit 3 */
968 
  NEOLED_CT_T_ZERO_H_4 = 19, /**< NEOLED control register(19) (r/w): pulse-clock ticks per ZERO high-time bit 4 */
969 
  //
970 
  NEOLED_CT_T_ONE_H_0  = 20, /**< NEOLED control register(20) (r/w): pulse-clock ticks per ONE high-time bit 0 */
971 
  NEOLED_CT_T_ONE_H_1  = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */
972 
  NEOLED_CT_T_ONE_H_2  = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */
973 
  NEOLED_CT_T_ONE_H_3  = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */
974 
  NEOLED_CT_T_ONE_H_4  = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */
975 
  //
976 
  NEOLED_CT_TX_STATUS  = 30, /**< NEOLED control register(30) (r/-): serial transmit engine still busy when set */
977 
  NEOLED_CT_BUSY       = 31  /**< NEOLED control register(31) (r/-): busy / buffer status flag (configured via #NEOLED_CT_BSCON) */
978 
};
979 
/**@}*/
980 
 
981 
 
982 
/**********************************************************************//**
983 12 zero_gravi 
 * @name IO Device: System Configuration Info Memory (SYSINFO)
984 
 **************************************************************************/
985 
/**@{*/
986 
/** SYSINFO(0): Clock speed */
987 
#define SYSINFO_CLK         (*(IO_ROM32 0xFFFFFFE0UL))
988 
/** SYSINFO(1): Custom user code (via "USER_CODE" generic) */
989 
#define SYSINFO_USER_CODE   (*(IO_ROM32 0xFFFFFFE4UL))
990 
/** SYSINFO(2): Clock speed */
991 
#define SYSINFO_FEATURES    (*(IO_ROM32 0xFFFFFFE8UL))
992 41 zero_gravi 
/** SYSINFO(3): Cache configuration */
993 
#define SYSINFO_CACHE       (*(IO_ROM32 0xFFFFFFECUL))
994 12 zero_gravi 
/** SYSINFO(4): Instruction memory address space base */
995 
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL))
996 
/** SYSINFO(5): Data memory address space base */
997 
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 0xFFFFFFF4UL))
998 23 zero_gravi 
/** SYSINFO(6): Internal instruction memory (IMEM) size in bytes */
999 
#define SYSINFO_IMEM_SIZE   (*(IO_ROM32 0xFFFFFFF8UL))
1000 
/** SYSINFO(7): Internal data memory (DMEM) size in bytes */
1001 
#define SYSINFO_DMEM_SIZE   (*(IO_ROM32 0xFFFFFFFCUL))
1002 12 zero_gravi 
/**@}*/
1003 
 
1004 
/**********************************************************************//**
1005 
 * SYSINFO_FEATURES (r/-): Implemented processor devices/features
1006 
 **************************************************************************/
1007 
 enum NEORV32_SYSINFO_FEATURES_enum {
1008 44 zero_gravi 
  SYSINFO_FEATURES_BOOTLOADER       =  0, /**< SYSINFO_FEATURES  (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_EN generic) */
1009 
  SYSINFO_FEATURES_MEM_EXT          =  1, /**< SYSINFO_FEATURES  (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
1010 
  SYSINFO_FEATURES_MEM_INT_IMEM     =  2, /**< SYSINFO_FEATURES  (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
1011 12 zero_gravi 
  SYSINFO_FEATURES_MEM_INT_IMEM_ROM =  3, /**< SYSINFO_FEATURES  (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
1012 44 zero_gravi 
  SYSINFO_FEATURES_MEM_INT_DMEM     =  4, /**< SYSINFO_FEATURES  (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
1013 40 zero_gravi 
  SYSINFO_FEATURES_MEM_EXT_ENDIAN   =  5, /**< SYSINFO_FEATURES  (5) (r/-): External bus interface uses BIG-endian byte-order when 1 (via package.xbus_big_endian_c constant) */
1014 44 zero_gravi 
  SYSINFO_FEATURES_ICACHE           =  6, /**< SYSINFO_FEATURES  (6) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
1015 12 zero_gravi 
 
1016 44 zero_gravi 
  SYSINFO_FEATURES_IO_GPIO          = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
1017 
  SYSINFO_FEATURES_IO_MTIME         = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */
1018 50 zero_gravi 
  SYSINFO_FEATURES_IO_UART0         = 18, /**< SYSINFO_FEATURES (18) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */
1019 44 zero_gravi 
  SYSINFO_FEATURES_IO_SPI           = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) */
1020 
  SYSINFO_FEATURES_IO_TWI           = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */
1021 
  SYSINFO_FEATURES_IO_PWM           = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
1022 
  SYSINFO_FEATURES_IO_WDT           = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
1023 47 zero_gravi 
  SYSINFO_FEATURES_IO_CFS           = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
1024 49 zero_gravi 
  SYSINFO_FEATURES_IO_TRNG          = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
1025 50 zero_gravi 
  SYSINFO_FEATURES_IO_NCO           = 25, /**< SYSINFO_FEATURES (25) (r/-): Numerically-controlled oscillator implemented when 1 (via IO_NCO_EN generic) */
1026 52 zero_gravi 
  SYSINFO_FEATURES_IO_UART1         = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
1027 
  SYSINFO_FEATURES_IO_NEOLED        = 27  /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
1028 12 zero_gravi 
};
1029 
 
1030 41 zero_gravi 
/**********************************************************************//**
1031 
 * SYSINFO_CACHE (r/-): Cache configuration
1032 
 **************************************************************************/
1033 
 enum NEORV32_SYSINFO_CACHE_enum {
1034 
  SYSINFO_CACHE_IC_BLOCK_SIZE_0    =  0, /**< SYSINFO_CACHE  (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) */
1035 
  SYSINFO_CACHE_IC_BLOCK_SIZE_1    =  1, /**< SYSINFO_CACHE  (1) (r/-): i-cache: log2(Block size in bytes), bit 1 (via ICACHE_BLOCK_SIZE generic) */
1036 
  SYSINFO_CACHE_IC_BLOCK_SIZE_2    =  2, /**< SYSINFO_CACHE  (2) (r/-): i-cache: log2(Block size in bytes), bit 2 (via ICACHE_BLOCK_SIZE generic) */
1037 
  SYSINFO_CACHE_IC_BLOCK_SIZE_3    =  3, /**< SYSINFO_CACHE  (3) (r/-): i-cache: log2(Block size in bytes), bit 3 (via ICACHE_BLOCK_SIZE generic) */
1038 12 zero_gravi 
 
1039 41 zero_gravi 
  SYSINFO_CACHE_IC_NUM_BLOCKS_0    =  4, /**< SYSINFO_CACHE  (4) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 0 (via ICACHE_NUM_BLOCKS generic) */
1040 
  SYSINFO_CACHE_IC_NUM_BLOCKS_1    =  5, /**< SYSINFO_CACHE  (5) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 1 (via ICACHE_NUM_BLOCKS generic) */
1041 
  SYSINFO_CACHE_IC_NUM_BLOCKS_2    =  6, /**< SYSINFO_CACHE  (6) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 2 (via ICACHE_NUM_BLOCKS generic) */
1042 
  SYSINFO_CACHE_IC_NUM_BLOCKS_3    =  7, /**< SYSINFO_CACHE  (7) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 3 (via ICACHE_NUM_BLOCKS generic) */
1043 
 
1044 45 zero_gravi 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_0 =  8, /**< SYSINFO_CACHE  (8) (r/-): i-cache: log2(associativity), bit 0 (via ICACHE_ASSOCIATIVITY generic) */
1045 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_1 =  9, /**< SYSINFO_CACHE  (9) (r/-): i-cache: log2(associativity), bit 1 (via ICACHE_ASSOCIATIVITY generic) */
1046 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_2 = 10, /**< SYSINFO_CACHE (10) (r/-): i-cache: log2(associativity), bit 2 (via ICACHE_ASSOCIATIVITY generic) */
1047 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_3 = 11, /**< SYSINFO_CACHE (11) (r/-): i-cache: log2(associativity), bit 3 (via ICACHE_ASSOCIATIVITY generic) */
1048 
 
1049 
  SYSINFO_CACHE_IC_REPLACEMENT_0   = 12, /**< SYSINFO_CACHE (12) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 0 */
1050 
  SYSINFO_CACHE_IC_REPLACEMENT_1   = 13, /**< SYSINFO_CACHE (13) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 1 */
1051 
  SYSINFO_CACHE_IC_REPLACEMENT_2   = 14, /**< SYSINFO_CACHE (14) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 2 */
1052 
  SYSINFO_CACHE_IC_REPLACEMENT_3   = 15, /**< SYSINFO_CACHE (15) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 3 */
1053 41 zero_gravi 
};
1054 
 
1055 
 
1056 2 zero_gravi 
// ----------------------------------------------------------------------------
1057 
// Include all IO driver headers
1058 
// ----------------------------------------------------------------------------
1059 
// cpu core
1060 
#include "neorv32_cpu.h"
1061 
 
1062 
// neorv32 runtime environment
1063 
#include "neorv32_rte.h"
1064 
 
1065 
// io/peripheral devices
1066 47 zero_gravi 
#include "neorv32_cfs.h"
1067 2 zero_gravi 
#include "neorv32_gpio.h"
1068 
#include "neorv32_mtime.h"
1069 49 zero_gravi 
#include "neorv32_nco.h"
1070 52 zero_gravi 
#include "neorv32_neoled.h"
1071 2 zero_gravi 
#include "neorv32_pwm.h"
1072 
#include "neorv32_spi.h"
1073 
#include "neorv32_trng.h"
1074 
#include "neorv32_twi.h"
1075 
#include "neorv32_uart.h"
1076 
#include "neorv32_wdt.h"
1077 
 
1078 
#endif // neorv32_h

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