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[/] [neorv32/] [trunk/] [sw/] [lib/] [include/] [neorv32_cpu.h] - Blame information for rev 61

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// #################################################################################################
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// # << NEORV32: neorv32_cpu.h - CPU Core Functions HW Driver >>                                   #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License                                                                          #
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// #                                                                                               #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
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// #                                                                                               #
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// # Redistribution and use in source and binary forms, with or without modification, are          #
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// # permitted provided that the following conditions are met:                                     #
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// #                                                                                               #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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// #    conditions and the following disclaimer.                                                   #
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// #                                                                                               #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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// #    conditions and the following disclaimer in the documentation and/or other materials        #
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// #    provided with the distribution.                                                            #
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// #                                                                                               #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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// #    endorse or promote products derived from this software without specific prior written      #
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// #    permission.                                                                                #
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// #                                                                                               #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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 * @file neorv32_cpu.h
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 * @author Stephan Nolting
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 * @brief CPU Core Functions HW driver header file.
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 **************************************************************************/
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#ifndef neorv32_cpu_h
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#define neorv32_cpu_h
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// prototypes
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int neorv32_cpu_irq_enable(uint8_t irq_sel);
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int neorv32_cpu_irq_disable(uint8_t irq_sel);
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uint64_t neorv32_cpu_get_cycle(void);
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void neorv32_cpu_set_mcycle(uint64_t value);
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uint64_t neorv32_cpu_get_instret(void);
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void neorv32_cpu_set_minstret(uint64_t value);
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uint64_t neorv32_cpu_get_systime(void);
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void neorv32_cpu_delay_ms(int16_t time_ms);
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void __attribute__((naked)) neorv32_cpu_goto_user_mode(void);
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uint32_t neorv32_cpu_pmp_get_num_regions(void);
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uint32_t neorv32_cpu_pmp_get_granularity(void);
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int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config);
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uint32_t neorv32_cpu_hpm_get_counters(void);
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uint32_t neorv32_cpu_hpm_get_size(void);
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int neorv32_cpu_check_zext(uint8_t flag_id);
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62
 
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/**********************************************************************//**
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 * Prototype for "after-main handler". This function is called if main() returns.
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 *
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 * @param[in] return_code Return value of main() function.
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 * @return Return value is irrelevant (there is no one left to check for it...).
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 **************************************************************************/
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extern int __neorv32_crt0_after_main(int32_t return_code);
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/**********************************************************************//**
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 * Store unsigned word to address space.
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 *
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 * @note An unaligned access address will raise an alignment exception.
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 *
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 * @param[in] addr Address (32-bit).
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 * @param[in] wdata Data word (32-bit) to store.
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 * @return Operation status (32-bit).
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 **************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_store_conditional(uint32_t addr, uint32_t wdata) {
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#if defined __riscv_atomic || defined __riscv_a
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  register uint32_t reg_addr = addr;
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  register uint32_t reg_data = wdata;
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  register uint32_t reg_status;
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  asm volatile ("sc.w %[status], %[da], (%[ad])" : [status] "=r" (reg_status) : [da] "r" (reg_data), [ad] "r" (reg_addr));
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  return reg_status;
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#else
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  return 1; // always failing
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#endif
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}
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/**********************************************************************//**
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 * Conditional store unsigned word to address space if atomic access reservation is valid.
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 *
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 * @note An unaligned access address will raise an alignment exception.
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 *
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 * @param[in] addr Address (32-bit).
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 * @param[in] wdata Data word (32-bit) to store.
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 **************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_word(uint32_t addr, uint32_t wdata) {
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  register uint32_t reg_addr = addr;
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  register uint32_t reg_data = wdata;
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  asm volatile ("sw %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr));
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}
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/**********************************************************************//**
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 * Store unsigned half-word to address space.
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 *
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 * @note An unaligned access address will raise an alignment exception.
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 *
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 * @param[in] addr Address (32-bit).
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 * @param[in] wdata Data half-word (16-bit) to store.
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 **************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_half(uint32_t addr, uint16_t wdata) {
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  register uint32_t reg_addr = addr;
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  register uint32_t reg_data = (uint32_t)wdata;
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  asm volatile ("sh %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr));
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}
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/**********************************************************************//**
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 * Store unsigned byte to address space.
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 *
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 * @param[in] addr Address (32-bit).
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 * @param[in] wdata Data byte (8-bit) to store.
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 **************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_byte(uint32_t addr, uint8_t wdata) {
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  register uint32_t reg_addr = addr;
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  register uint32_t reg_data = (uint32_t)wdata;
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  asm volatile ("sb %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr));
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}
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/**********************************************************************//**
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 * Load unsigned word from address space and make reservation for atomic access.
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 *
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 * @note An unaligned access address will raise an alignment exception.
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 *
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 * @param[in] addr Address (32-bit).
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 * @return Read data word (32-bit).
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 **************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_load_reservate_word(uint32_t addr) {
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  register uint32_t reg_addr = addr;
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  register uint32_t reg_data;
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#if defined __riscv_atomic || defined __riscv_a
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  asm volatile ("lr.w %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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#else
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  asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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#endif
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  return (uint32_t)reg_data;
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}
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/**********************************************************************//**
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 * Load unsigned word from address space.
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 *
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 * @note An unaligned access address will raise an alignment exception.
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 *
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 * @param[in] addr Address (32-bit).
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 * @return Read data word (32-bit).
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 **************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_word(uint32_t addr) {
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  register uint32_t reg_addr = addr;
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  register uint32_t reg_data;
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  asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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  return (uint32_t)reg_data;
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}
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188
 
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/**********************************************************************//**
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 * Load unsigned half-word from address space.
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 *
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 * @note An unaligned access address will raise an alignment exception.
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 *
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 * @param[in] addr Address (32-bit).
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 * @return Read data half-word (16-bit).
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 **************************************************************************/
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inline uint16_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_half(uint32_t addr) {
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  register uint32_t reg_addr = addr;
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  register uint32_t reg_data;
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  asm volatile ("lhu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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  return (uint16_t)reg_data;
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}
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/**********************************************************************//**
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 * Load unsigned byte from address space.
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 *
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 * @param[in] addr Address (32-bit).
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 * @return Read data byte (8-bit).
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 **************************************************************************/
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inline uint8_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_byte(uint32_t addr) {
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  register uint32_t reg_addr = addr;
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  register uint32_t reg_data;
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  asm volatile ("lbu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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  return (uint8_t)reg_data;
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}
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/**********************************************************************//**
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 * Read data from CPU configuration and status register (CSR).
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 *
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 * @param[in] csr_id ID of CSR to read. See #NEORV32_CSR_enum.
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 * @return Read data (uint32_t).
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 **************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_csr_read(const int csr_id) {
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  register uint32_t csr_data;
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  asm volatile ("csrr %[result], %[input_i]" : [result] "=r" (csr_data) : [input_i] "i" (csr_id));
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  return csr_data;
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}
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/**********************************************************************//**
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 * Write data to CPU configuration and status register (CSR).
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 *
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 * @param[in] csr_id ID of CSR to write. See #NEORV32_CSR_enum.
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 * @param[in] data Data to write (uint32_t).
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 **************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_csr_write(const int csr_id, uint32_t data) {
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  register uint32_t csr_data = data;
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  asm volatile ("csrw %[input_i], %[input_j]" :  : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
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}
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/**********************************************************************//**
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 * Put CPU into "sleep" mode.
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 *
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 * @note This function executes the WFI insstruction.
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 * The WFI (wait for interrupt) instruction will make the CPU stall until
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 * an interupt request is detected. Interrupts have to be globally enabled
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 * and at least one external source must be enabled (like the MTI machine
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 * timer interrupt) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,
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 * this will permanently stall the CPU.
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 **************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) {
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  asm volatile ("wfi");
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}
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/**********************************************************************//**
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 * Enable global CPU interrupts (via MIE flag in mstatus CSR).
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 **************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_eint(void) {
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  asm volatile ("csrrsi zero, mstatus, %0" : : "i" (1 << CSR_MSTATUS_MIE));
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  asm volatile ("nop");
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  asm volatile ("nop");
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}
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/**********************************************************************//**
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 * Disable global CPU interrupts (via MIE flag in mstatus CSR).
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 **************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_dint(void) {
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  asm volatile ("csrrci zero, mstatus, %0" : : "i" (1 << CSR_MSTATUS_MIE));
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  asm volatile ("nop");
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  asm volatile ("nop");
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}
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293
/**********************************************************************//**
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 * Trigger breakpoint exception (via EBREAK instruction).
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 **************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_breakpoint(void) {
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298
  asm volatile ("ebreak");
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}
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/**********************************************************************//**
303
 * Trigger "environment call" exception (via ECALL instruction).
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 **************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_env_call(void) {
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  asm volatile ("ecall");
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}
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#endif // neorv32_cpu_h

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