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[/] [neorv32/] [trunk/] [sw/] [lib/] [include/] [neorv32_cpu.h] - Blame information for rev 9

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// #################################################################################################
// # << NEORV32: neorv32_cpu.h - CPU Core Functions HW Driver >>                                   #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
// #                                                                                               #
// # Redistribution and use in source and binary forms, with or without modification, are          #
// # permitted provided that the following conditions are met:                                     #
// #                                                                                               #
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
// #    conditions and the following disclaimer.                                                   #
// #                                                                                               #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
// #    conditions and the following disclaimer in the documentation and/or other materials        #
// #    provided with the distribution.                                                            #
// #                                                                                               #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
// #    endorse or promote products derived from this software without specific prior written      #
// #    permission.                                                                                #
// #                                                                                               #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
 * @file neorv32_cpu.h
 * @author Stephan Nolting
 * @brief CPU Core Functions HW driver header file.
 **************************************************************************/
 
#ifndef neorv32_cpu_h
#define neorv32_cpu_h
 
// prototypes
int neorv32_cpu_switch_extension(int sel, int state);
int neorv32_cpu_irq_enable(uint8_t irq_sel);
int neorv32_cpu_irq_disable(uint8_t irq_sel);
void neorv32_cpu_delay_ms(uint32_t time_ms);
 
 
/**********************************************************************//**
 * Read data from CPU configuration and status register (CSR).
 *
 * @param[in] csr_id ID of CSR to read. See #NEORV32_CPU_CSRS_enum.
 * @return Read data (uint32_t).
 **************************************************************************/
inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_csr_read(const int csr_id) {
 
  register uint32_t csr_data;
 
  asm volatile ("csrr %[result], %[input_i]" : [result] "=r" (csr_data) : [input_i] "i" (csr_id));
 
  return csr_data;
}
 
 
/**********************************************************************//**
 * Write data to CPU configuration and status register (CSR).
 *
 * @param[in] csr_id ID of CSR to write. See #NEORV32_CPU_CSRS_enum.
 * @param[in] data Data to write (uint32_t).
 **************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_csr_write(const int csr_id, uint32_t data) {
 
  register uint32_t csr_data = data;
 
  asm volatile ("csrw %[input_i], %[input_j]" :  : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
}
 
 
/**********************************************************************//**
 * Put CPU into "sleep" mode.
 *
 * @note This function executes the WFI insstruction.
 * The WFI (wait for interrupt) instruction will make the CPU stall until
 * an interupt request is detected. Interrupts have to be globally enabled
 * and at least one external source must be enabled (e.g., the CLIC or the machine
 * timer) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,
 * this will permanently stall the CPU.
 **************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) {
 
  asm volatile ("wfi");
}
 
 
/**********************************************************************//**
 * Enable global CPU interrupts (via MIE flag in mstatus CSR).
 **************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_eint(void) {
 
  asm volatile ("csrrsi zero, mstatus, %0" : : "i" (1 << CPU_MSTATUS_MIE));
}
 
 
/**********************************************************************//**
 * Disable global CPU interrupts (via MIE flag in mstatus CSR).
 **************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_dint(void) {
 
  asm volatile ("csrrci zero, mstatus, %0" : : "i" (1 << CPU_MSTATUS_MIE));
}
 
 
/**********************************************************************//**
 * Trigger machine software interrupt.
 *
 * @note The according IRQ has to be enabled via neorv32_cpu_irq_enable(uint8_t irq_sel) and
 * global interrupts must be enabled via neorv32_cpu_eint(void) to trigger an IRQ via software.
 * The MSI becomes active after 3 clock cycles.
 **************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_sw_irq(void) {
 
  asm volatile ("csrrsi zero, mip, %0" : : "i" (1 << CPU_MIP_MSIP));
 
  // the MSI becomes active 3 clock cycles afters issueing
  asm volatile ("nop"); // these nops are not required, they just make sure the MSI becomes active
  asm volatile ("nop"); // before the "real" next operation is executed
}
 
 
/**********************************************************************//**
 * Trigger breakpoint exception (via EBREAK instruction).
 **************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_breakpoint(void) {
 
  asm volatile ("ebreak");
}
 
 
/**********************************************************************//**
 * Trigger "environment call" exception (via ECALL instruction).
 **************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_env_call(void) {
 
  asm volatile ("ecall");
}
 
 
#endif // neorv32_cpu_h

Line No.	Rev	Author	Line
1	2	zero_gravi	`// #################################################################################################`
2			`// # << NEORV32: neorv32_cpu.h - CPU Core Functions HW Driver >> #`
3			`// # ********************************************************************************************* #`
4			`// # BSD 3-Clause License #`
5			`// # #`
6			`// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #`
7			`// # #`
8			`// # Redistribution and use in source and binary forms, with or without modification, are #`
9			`// # permitted provided that the following conditions are met: #`
10			`// # #`
11			`// # 1. Redistributions of source code must retain the above copyright notice, this list of #`
12			`// # conditions and the following disclaimer. #`
13			`// # #`
14			`// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #`
15			`// # conditions and the following disclaimer in the documentation and/or other materials #`
16			`// # provided with the distribution. #`
17			`// # #`
18			`// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #`
19			`// # endorse or promote products derived from this software without specific prior written #`
20			`// # permission. #`
21			`// # #`
22			`// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #`
23			`// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #`
24			`// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #`
25			`// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #`
26			`// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #`
27			`// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #`
28			`// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #`
29			`// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #`
30			`// # OF THE POSSIBILITY OF SUCH DAMAGE. #`
31			`// # ********************************************************************************************* #`
32			`// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #`
33			`// #################################################################################################`
34
35
36			`/********************************************************************//`
37			`* @file neorv32_cpu.h`
38			`* @author Stephan Nolting`
39			`* @brief CPU Core Functions HW driver header file.`
40			`**************************************************************************/`
41
42			`#ifndef neorv32_cpu_h`
43			`#define neorv32_cpu_h`
44
45			`// prototypes`
46	9	zero_gravi	`int neorv32_cpu_switch_extension(int sel, int state);`
47	2	zero_gravi	`int neorv32_cpu_irq_enable(uint8_t irq_sel);`
48			`int neorv32_cpu_irq_disable(uint8_t irq_sel);`
49			`void neorv32_cpu_delay_ms(uint32_t time_ms);`
50
51
52			`/********************************************************************//`
53			`* Read data from CPU configuration and status register (CSR).`
54			`*`
55			`* @param[in] csr_id ID of CSR to read. See #NEORV32_CPU_CSRS_enum.`
56			`* @return Read data (uint32_t).`
57			`**************************************************************************/`
58			`inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_csr_read(const int csr_id) {`
59
60			`register uint32_t csr_data;`
61
62	6	zero_gravi	`asm volatile ("csrr %[result], %[input_i]" : [result] "=r" (csr_data) : [input_i] "i" (csr_id));`
63	2	zero_gravi
64			`return csr_data;`
65			`}`
66
67
68			`/********************************************************************//`
69			`* Write data to CPU configuration and status register (CSR).`
70			`*`
71			`* @param[in] csr_id ID of CSR to write. See #NEORV32_CPU_CSRS_enum.`
72			`* @param[in] data Data to write (uint32_t).`
73			`**************************************************************************/`
74			`inline void __attribute__ ((always_inline)) neorv32_cpu_csr_write(const int csr_id, uint32_t data) {`
75
76			`register uint32_t csr_data = data;`
77
78	6	zero_gravi	`asm volatile ("csrw %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data));`
79	2	zero_gravi	`}`
80
81	9	zero_gravi
82			`/********************************************************************//`
83			`* Put CPU into "sleep" mode.`
84			`*`
85			`* @note This function executes the WFI insstruction.`
86			`* The WFI (wait for interrupt) instruction will make the CPU stall until`
87			`* an interupt request is detected. Interrupts have to be globally enabled`
88			`* and at least one external source must be enabled (e.g., the CLIC or the machine`
89			`* timer) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,`
90			`* this will permanently stall the CPU.`
91			`**************************************************************************/`
92			`inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) {`
93
94			`asm volatile ("wfi");`
95			`}`
96
97
98			`/********************************************************************//`
99			`* Enable global CPU interrupts (via MIE flag in mstatus CSR).`
100			`**************************************************************************/`
101			`inline void __attribute__ ((always_inline)) neorv32_cpu_eint(void) {`
102
103			`asm volatile ("csrrsi zero, mstatus, %0" : : "i" (1 << CPU_MSTATUS_MIE));`
104			`}`
105
106
107			`/********************************************************************//`
108			`* Disable global CPU interrupts (via MIE flag in mstatus CSR).`
109			`**************************************************************************/`
110			`inline void __attribute__ ((always_inline)) neorv32_cpu_dint(void) {`
111
112			`asm volatile ("csrrci zero, mstatus, %0" : : "i" (1 << CPU_MSTATUS_MIE));`
113			`}`
114
115
116			`/********************************************************************//`
117			`* Trigger machine software interrupt.`
118			`*`
119			`* @note The according IRQ has to be enabled via neorv32_cpu_irq_enable(uint8_t irq_sel) and`
120			`* global interrupts must be enabled via neorv32_cpu_eint(void) to trigger an IRQ via software.`
121			`* The MSI becomes active after 3 clock cycles.`
122			`**************************************************************************/`
123			`inline void __attribute__ ((always_inline)) neorv32_cpu_sw_irq(void) {`
124
125			`asm volatile ("csrrsi zero, mip, %0" : : "i" (1 << CPU_MIP_MSIP));`
126
127			`// the MSI becomes active 3 clock cycles afters issueing`
128			`asm volatile ("nop"); // these nops are not required, they just make sure the MSI becomes active`
129			`asm volatile ("nop"); // before the "real" next operation is executed`
130			`}`
131
132
133			`/********************************************************************//`
134			`* Trigger breakpoint exception (via EBREAK instruction).`
135			`**************************************************************************/`
136			`inline void __attribute__ ((always_inline)) neorv32_cpu_breakpoint(void) {`
137
138			`asm volatile ("ebreak");`
139			`}`
140
141
142			`/********************************************************************//`
143			`* Trigger "environment call" exception (via ECALL instruction).`
144			`**************************************************************************/`
145			`inline void __attribute__ ((always_inline)) neorv32_cpu_env_call(void) {`
146
147			`asm volatile ("ecall");`
148			`}`
149
150
151	2	zero_gravi	`#endif // neorv32_cpu_h`

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[/] [neorv32/] [trunk/] [sw/] [lib/] [include/] [neorv32_cpu.h] - Blame information for rev 9