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// #################################################################################################
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// # << NEORV32: neorv32_intrinsics.h - Helper functions/macros for (custom) "intrinsics" >>         #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License                                                                          #
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// #                                                                                               #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
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// #                                                                                               #
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// # Redistribution and use in source and binary forms, with or without modification, are          #
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// # permitted provided that the following conditions are met:                                     #
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// #                                                                                               #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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// #    conditions and the following disclaimer.                                                   #
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// #                                                                                               #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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// #    conditions and the following disclaimer in the documentation and/or other materials        #
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// #    provided with the distribution.                                                            #
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// #                                                                                               #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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// #    endorse or promote products derived from this software without specific prior written      #
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// #    permission.                                                                                #
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// #                                                                                               #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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 * @file neorv32_intrinsics.h
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 * @author Stephan Nolting
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 * @brief Helper functions and macros for custom "intrinsics" / instructions.
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 **************************************************************************/
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#ifndef neorv32_intrinsics_h
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#define neorv32_intrinsics_h
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/**********************************************************************//**
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 * @name Custom instructions / intrinsics helper macros
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 **************************************************************************/
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/**@{*/
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//** Selection helper macro */
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#define STR1(x) #x
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//** Selection helper macro 2 */
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#define STR(x) STR1(x)
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//** Register address converter */
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#define GET_REG_ADDR(x) REG_ADDR_##x
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#define REG_ADDR_x0   0 /**< register  0 */
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#define REG_ADDR_x1   1 /**< register  1 */
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#define REG_ADDR_x2   2 /**< register  2 */
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#define REG_ADDR_x3   3 /**< register  3 */
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#define REG_ADDR_x4   4 /**< register  4 */
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#define REG_ADDR_x5   5 /**< register  5 */
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#define REG_ADDR_x6   6 /**< register  6 */
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#define REG_ADDR_x7   7 /**< register  7 */
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#define REG_ADDR_x8   8 /**< register  8 */
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#define REG_ADDR_x9   9 /**< register  9 */
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#define REG_ADDR_x10 10 /**< register 10 */
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#define REG_ADDR_x11 11 /**< register 11 */
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#define REG_ADDR_x12 12 /**< register 12 */
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#define REG_ADDR_x13 13 /**< register 13 */
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#define REG_ADDR_x14 14 /**< register 14 */
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#define REG_ADDR_x15 15 /**< register 15 */
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#define REG_ADDR_x16 16 /**< register 16 */
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#define REG_ADDR_x17 17 /**< register 17 */
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#define REG_ADDR_x18 18 /**< register 18 */
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#define REG_ADDR_x19 19 /**< register 19 */
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#define REG_ADDR_x20 20 /**< register 20 */
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#define REG_ADDR_x21 21 /**< register 21 */
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#define REG_ADDR_x22 22 /**< register 22 */
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#define REG_ADDR_x23 23 /**< register 23 */
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#define REG_ADDR_x24 24 /**< register 24 */
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#define REG_ADDR_x25 25 /**< register 25 */
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#define REG_ADDR_x26 26 /**< register 26 */
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#define REG_ADDR_x27 27 /**< register 27 */
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#define REG_ADDR_x28 28 /**< register 28 */
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#define REG_ADDR_x29 29 /**< register 29 */
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#define REG_ADDR_x30 30 /**< register 30 */
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#define REG_ADDR_x31 31 /**< register 31 */
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#define REG_ADDR_zero 0 /**< register  0 - according to calling convention */
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#define REG_ADDR_ra   1 /**< register  1 - according to calling convention */
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#define REG_ADDR_sp   2 /**< register  2 - according to calling convention */
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#define REG_ADDR_gp   3 /**< register  3 - according to calling convention */
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#define REG_ADDR_tp   4 /**< register  4 - according to calling convention */
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#define REG_ADDR_t0   5 /**< register  5 - according to calling convention */
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#define REG_ADDR_t1   6 /**< register  6 - according to calling convention */
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#define REG_ADDR_t2   7 /**< register  7 - according to calling convention */
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#define REG_ADDR_s0   8 /**< register  8 - according to calling convention */
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#define REG_ADDR_s1   9 /**< register  9 - according to calling convention */
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#define REG_ADDR_a0  10 /**< register 10 - according to calling convention */
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#define REG_ADDR_a1  11 /**< register 11 - according to calling convention */
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#define REG_ADDR_a2  12 /**< register 12 - according to calling convention */
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#define REG_ADDR_a3  13 /**< register 13 - according to calling convention */
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#define REG_ADDR_a4  14 /**< register 14 - according to calling convention */
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#define REG_ADDR_a5  15 /**< register 15 - according to calling convention */
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#define REG_ADDR_a6  16 /**< register 16 - according to calling convention */
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#define REG_ADDR_a7  17 /**< register 17 - according to calling convention */
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#define REG_ADDR_s2  18 /**< register 18 - according to calling convention */
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#define REG_ADDR_s3  19 /**< register 19 - according to calling convention */
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#define REG_ADDR_s4  20 /**< register 20 - according to calling convention */
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#define REG_ADDR_s5  21 /**< register 21 - according to calling convention */
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#define REG_ADDR_s6  22 /**< register 22 - according to calling convention */
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#define REG_ADDR_s7  23 /**< register 23 - according to calling convention */
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#define REG_ADDR_s8  24 /**< register 24 - according to calling convention */
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#define REG_ADDR_s9  25 /**< register 25 - according to calling convention */
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#define REG_ADDR_s10 26 /**< register 26 - according to calling convention */
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#define REG_ADDR_s11 27 /**< register 27 - according to calling convention */
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#define REG_ADDR_t3  28 /**< register 28 - according to calling convention */
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#define REG_ADDR_t4  29 /**< register 29 - according to calling convention */
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#define REG_ADDR_t5  30 /**< register 30 - according to calling convention */
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#define REG_ADDR_t6  31 /**< register 31 - according to calling convention */
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//** Construct instruction word (32-bit) for R-type instruction */
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#define CMD_WORD_R_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
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  ( (opcode & 0x7f) <<  0 ) + \
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  ( (rd     & 0x1f) <<  7 ) + \
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  ( (rs1    & 0x1f) << 15 ) + \
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  ( (rs2    & 0x1f) << 20 ) + \
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  ( (funct7 & 0x7f) << 25 ) + \
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  ( (funct3 & 0x1f) << 12 )
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//** Construct instruction word (32-bit) for I-type instruction */
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#define CMD_WORD_I_TYPE(imm12, rs1_f5, funct3, rd, opcode) \
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  ( (opcode & 0x7f)  <<  0 ) + \
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  ( (rd     & 0x1f)  <<  7 ) + \
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  ( (rs1_f5 & 0x1f)  << 15 ) + \
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  ( (imm12  & 0xfff) << 20 ) + \
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  ( (funct3 & 0x1f)  << 12 )
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//** Construct custom instruction for R-type instruction */
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#define CUSTOM_INSTR_R_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
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  asm volatile (".word "STR(CMD_WORD_R_TYPE(funct7, GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
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//** Construct custom instruction for R1-type instruction (register + 5-bit immediate/function_select) */
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#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, rd, opcode) \
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  asm volatile (".word "STR(CMD_WORD_R_TYPE(funct7, funct5, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
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//** Construct custom instruction for I-type instruction */
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#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, rd, opcode) \
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  asm volatile (".word "STR(CMD_WORD_I_TYPE(imm12, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
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/**@}*/
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#endif // neorv32_intrinsics_h

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