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// #################################################################################################
// # << NEORV32: neorv32_intrinsics.h - Helper functions/macros for (custom) "intrinsics" >>       #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
// #                                                                                               #
// # Redistribution and use in source and binary forms, with or without modification, are          #
// # permitted provided that the following conditions are met:                                     #
// #                                                                                               #
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
// #    conditions and the following disclaimer.                                                   #
// #                                                                                               #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
// #    conditions and the following disclaimer in the documentation and/or other materials        #
// #    provided with the distribution.                                                            #
// #                                                                                               #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
// #    endorse or promote products derived from this software without specific prior written      #
// #    permission.                                                                                #
// #                                                                                               #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
 * @file neorv32_intrinsics.h
 * @author Stephan Nolting, SaxonSoc contributors, Google-CFU
 * @brief Helper functions and macros for custom "intrinsics" / instructions.
 **************************************************************************/
 
#ifndef neorv32_intrinsics_h
#define neorv32_intrinsics_h
 
 
// ****************************************************************************************************************************
// Custom Instruction Intrinsics
// Derived from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h
// Original license header:
//
//   From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h
//
//   Copyright (c) 2019 SaxonSoc contributors
//
//   MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE
//
// LICENSE:
//  MIT License
//  
//  Copyright (c) 2019 SaxonSoc contributors
//  
//  Permission is hereby granted, free of charge, to any person obtaining a copy
//  of this software and associated documentation files (the "Software"), to deal
//  in the Software without restriction, including without limitation the rights
//  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
//  copies of the Software, and to permit persons to whom the Software is
//  furnished to do so, subject to the following conditions:
//  
//  The above copyright notice and this permission notice shall be included in all
//  copies or substantial portions of the Software.
//  
//  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
//  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
//  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
//  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
//  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
//  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
//  SOFTWARE.
// ****************************************************************************************************************************
 
/**********************************************************************//**
 * @name Custom Instruction Intrinsics
 * @note Copied from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h
 *       Original license header:
 * // From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h
 * //
 * // Copyright (c) 2019 SaxonSoc contributors
 * //
 * // MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE
 **************************************************************************/
/**@{*/
asm(".set regnum_x0  ,  0");
asm(".set regnum_x1  ,  1");
asm(".set regnum_x2  ,  2");
asm(".set regnum_x3  ,  3");
asm(".set regnum_x4  ,  4");
asm(".set regnum_x5  ,  5");
asm(".set regnum_x6  ,  6");
asm(".set regnum_x7  ,  7");
asm(".set regnum_x8  ,  8");
asm(".set regnum_x9  ,  9");
asm(".set regnum_x10 , 10");
asm(".set regnum_x11 , 11");
asm(".set regnum_x12 , 12");
asm(".set regnum_x13 , 13");
asm(".set regnum_x14 , 14");
asm(".set regnum_x15 , 15");
asm(".set regnum_x16 , 16");
asm(".set regnum_x17 , 17");
asm(".set regnum_x18 , 18");
asm(".set regnum_x19 , 19");
asm(".set regnum_x20 , 20");
asm(".set regnum_x21 , 21");
asm(".set regnum_x22 , 22");
asm(".set regnum_x23 , 23");
asm(".set regnum_x24 , 24");
asm(".set regnum_x25 , 25");
asm(".set regnum_x26 , 26");
asm(".set regnum_x27 , 27");
asm(".set regnum_x28 , 28");
asm(".set regnum_x29 , 29");
asm(".set regnum_x30 , 30");
asm(".set regnum_x31 , 31");
 
asm(".set regnum_zero,  0");
asm(".set regnum_ra  ,  1");
asm(".set regnum_sp  ,  2");
asm(".set regnum_gp  ,  3");
asm(".set regnum_tp  ,  4");
asm(".set regnum_t0  ,  5");
asm(".set regnum_t1  ,  6");
asm(".set regnum_t2  ,  7");
asm(".set regnum_s0  ,  8");
asm(".set regnum_s1  ,  9");
asm(".set regnum_a0  , 10");
asm(".set regnum_a1  , 11");
asm(".set regnum_a2  , 12");
asm(".set regnum_a3  , 13");
asm(".set regnum_a4  , 14");
asm(".set regnum_a5  , 15");
asm(".set regnum_a6  , 16");
asm(".set regnum_a7  , 17");
asm(".set regnum_s2  , 18");
asm(".set regnum_s3  , 19");
asm(".set regnum_s4  , 20");
asm(".set regnum_s5  , 21");
asm(".set regnum_s6  , 22");
asm(".set regnum_s7  , 23");
asm(".set regnum_s8  , 24");
asm(".set regnum_s9  , 25");
asm(".set regnum_s10 , 26");
asm(".set regnum_s11 , 27");
asm(".set regnum_t3  , 28");
asm(".set regnum_t4  , 29");
asm(".set regnum_t5  , 30");
asm(".set regnum_t6  , 31");
 
/** Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1) */
asm(".set RISCV_OPCODE_CUSTOM0 , 0b0001011");
asm(".set RISCV_OPCODE_CUSTOM1 , 0b0101011");
/**@}*/
 
 
/**********************************************************************//**
 * @name Custom instruction R1-type format
 **************************************************************************/
#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, opcode) \
({                                                                \
    register uint32_t __return;                                   \
    asm volatile (                                                \
      ""                                                          \
      : [output] "=r" (__return)                                  \
      : [input_i] "r" (rs1)                                       \
    );                                                            \
    asm volatile(                                                 \
      ".word (                                                    \
        (((" #funct7 ") & 0x7f) << 25) |                          \
        (((" #funct5 ") & 0x1f) << 20) |                          \
        ((( regnum_%1 ) & 0x1f) << 15) |                          \
        (((" #funct3 ") & 0x07) << 12) |                          \
        ((( regnum_%0 ) & 0x1f) <<  7) |                          \
        (((" #opcode ") & 0x7f) <<  0)                            \
      );"                                                         \
      : [rd] "=r" (__return)                                      \
      : "r" (rs1)                                                 \
    );                                                            \
    __return;                                                     \
})
 
 
/**********************************************************************//**
 * @name Custom instruction R2-type format
 **************************************************************************/
#define CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, funct3, opcode) \
({                                                             \
    register uint32_t __return;                                \
    asm volatile (                                             \
      ""                                                       \
      : [output] "=r" (__return)                               \
      : [input_i] "r" (rs1),                                   \
        [input_j] "r" (rs2)                                    \
    );                                                         \
    asm volatile (                                             \
      ".word (                                                 \
        (((" #funct7 ") & 0x7f) << 25) |                       \
        ((( regnum_%2 ) & 0x1f) << 20) |                       \
        ((( regnum_%1 ) & 0x1f) << 15) |                       \
        (((" #funct3 ") & 0x07) << 12) |                       \
        ((( regnum_%0 ) & 0x1f) <<  7) |                       \
        (((" #opcode ") & 0x7f) <<  0)                         \
      );"                                                      \
      : [rd] "=r" (__return)                                   \
      : "r" (rs1),                                             \
        "r" (rs2)                                              \
    );                                                         \
    __return;                                                  \
})
 
 
/**********************************************************************//**
 * @name Custom instruction R3-type format
 **************************************************************************/
#define CUSTOM_INSTR_R3_TYPE(rs3, rs2, rs1, funct3, opcode) \
({                                                          \
    register uint32_t __return;                             \
    asm volatile (                                          \
      ""                                                    \
      : [output] "=r" (__return)                            \
      : [input_i] "r" (rs1),                                \
        [input_j] "r" (rs2),                                \
        [input_k] "r" (rs3)                                 \
    );                                                      \
    asm volatile (                                          \
      ".word (                                              \
        ((( regnum_%3 ) & 0x1f) << 25) |                    \
        ((( regnum_%2 ) & 0x1f) << 20) |                    \
        ((( regnum_%1 ) & 0x1f) << 15) |                    \
        (((" #funct3 ") & 0x07) << 12) |                    \
        ((( regnum_%0 ) & 0x1f) <<  7) |                    \
        (((" #opcode ") & 0x7f) <<  0)                      \
      );"                                                   \
      : [rd] "=r" (__return)                                \
      : "r" (rs1),                                          \
        "r" (rs2),                                          \
        "r" (rs3)                                           \
    );                                                      \
    __return;                                               \
})
 
 
/**********************************************************************//**
 * @name Custom instruction I-type format
 **************************************************************************/
#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode) \
({                                                      \
    register uint32_t __return;                         \
    asm volatile (                                      \
      ""                                                \
      : [output] "=r" (__return)                        \
      : [input_i] "r" (rs1)                             \
    );                                                  \
    asm volatile (                                      \
      ".word (                                          \
        (((" #imm12 ")  & 0xfff) << 20) |               \
        ((( regnum_%1 ) &  0x1f) << 15) |               \
        (((" #funct3 ") &  0x07) << 12) |               \
        ((( regnum_%0 ) &  0x1f) <<  7) |               \
        (((" #opcode ") &  0x7f) <<  0)                 \
      );"                                               \
      : [rd] "=r" (__return)                            \
      : "r" (rs1)                                       \
    );                                                  \
    __return;                                           \
})
 
 
#endif // neorv32_intrinsics_h

Line No.	Rev	Author	Line
1	54	zero_gravi	`// #################################################################################################`
2	55	zero_gravi	`// # << NEORV32: neorv32_intrinsics.h - Helper functions/macros for (custom) "intrinsics" >> #`
3	54	zero_gravi	`// # ********************************************************************************************* #`
4			`// # BSD 3-Clause License #`
5			`// # #`
6	71	zero_gravi	`// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #`
7	54	zero_gravi	`// # #`
8			`// # Redistribution and use in source and binary forms, with or without modification, are #`
9			`// # permitted provided that the following conditions are met: #`
10			`// # #`
11			`// # 1. Redistributions of source code must retain the above copyright notice, this list of #`
12			`// # conditions and the following disclaimer. #`
13			`// # #`
14			`// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #`
15			`// # conditions and the following disclaimer in the documentation and/or other materials #`
16			`// # provided with the distribution. #`
17			`// # #`
18			`// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #`
19			`// # endorse or promote products derived from this software without specific prior written #`
20			`// # permission. #`
21			`// # #`
22			`// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #`
23			`// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #`
24			`// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #`
25			`// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #`
26			`// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #`
27			`// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #`
28			`// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #`
29			`// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #`
30			`// # OF THE POSSIBILITY OF SUCH DAMAGE. #`
31			`// # ********************************************************************************************* #`
32			`// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #`
33			`// #################################################################################################`
34
35
36			`/********************************************************************//`
37			`* @file neorv32_intrinsics.h`
38	71	zero_gravi	`* @author Stephan Nolting, SaxonSoc contributors, Google-CFU`
39	54	zero_gravi	`* @brief Helper functions and macros for custom "intrinsics" / instructions.`
40			`**************************************************************************/`
41
42			`#ifndef neorv32_intrinsics_h`
43			`#define neorv32_intrinsics_h`
44
45	71	zero_gravi
46			`// ****************************************************************************************************************************`
47			`// Custom Instruction Intrinsics`
48			`// Derived from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h`
49			`// Original license header:`
50			`//`
51			`// From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h`
52			`//`
53			`// Copyright (c) 2019 SaxonSoc contributors`
54			`//`
55			`// MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE`
56			`//`
57			`// LICENSE:`
58			`// MIT License`
59			`//`
60			`// Copyright (c) 2019 SaxonSoc contributors`
61			`//`
62			`// Permission is hereby granted, free of charge, to any person obtaining a copy`
63			`// of this software and associated documentation files (the "Software"), to deal`
64			`// in the Software without restriction, including without limitation the rights`
65			`// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell`
66			`// copies of the Software, and to permit persons to whom the Software is`
67			`// furnished to do so, subject to the following conditions:`
68			`//`
69			`// The above copyright notice and this permission notice shall be included in all`
70			`// copies or substantial portions of the Software.`
71			`//`
72			`// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
73			`// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
74			`// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
75			`// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
76			`// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
77			`// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
78			`// SOFTWARE.`
79			`// ****************************************************************************************************************************`
80
81	54	zero_gravi	`/********************************************************************//`
82	71	zero_gravi	`* @name Custom Instruction Intrinsics`
83			`* @note Copied from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h`
84			`* Original license header:`
85			`* // From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h`
86			`* //`
87			`* // Copyright (c) 2019 SaxonSoc contributors`
88			`* //`
89			`* // MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE`
90	54	zero_gravi	`**************************************************************************/`
91			`/*@{/`
92	71	zero_gravi	`asm(".set regnum_x0 , 0");`
93			`asm(".set regnum_x1 , 1");`
94			`asm(".set regnum_x2 , 2");`
95			`asm(".set regnum_x3 , 3");`
96			`asm(".set regnum_x4 , 4");`
97			`asm(".set regnum_x5 , 5");`
98			`asm(".set regnum_x6 , 6");`
99			`asm(".set regnum_x7 , 7");`
100			`asm(".set regnum_x8 , 8");`
101			`asm(".set regnum_x9 , 9");`
102			`asm(".set regnum_x10 , 10");`
103			`asm(".set regnum_x11 , 11");`
104			`asm(".set regnum_x12 , 12");`
105			`asm(".set regnum_x13 , 13");`
106			`asm(".set regnum_x14 , 14");`
107			`asm(".set regnum_x15 , 15");`
108			`asm(".set regnum_x16 , 16");`
109			`asm(".set regnum_x17 , 17");`
110			`asm(".set regnum_x18 , 18");`
111			`asm(".set regnum_x19 , 19");`
112			`asm(".set regnum_x20 , 20");`
113			`asm(".set regnum_x21 , 21");`
114			`asm(".set regnum_x22 , 22");`
115			`asm(".set regnum_x23 , 23");`
116			`asm(".set regnum_x24 , 24");`
117			`asm(".set regnum_x25 , 25");`
118			`asm(".set regnum_x26 , 26");`
119			`asm(".set regnum_x27 , 27");`
120			`asm(".set regnum_x28 , 28");`
121			`asm(".set regnum_x29 , 29");`
122			`asm(".set regnum_x30 , 30");`
123			`asm(".set regnum_x31 , 31");`
124	54	zero_gravi
125	71	zero_gravi	`asm(".set regnum_zero, 0");`
126			`asm(".set regnum_ra , 1");`
127			`asm(".set regnum_sp , 2");`
128			`asm(".set regnum_gp , 3");`
129			`asm(".set regnum_tp , 4");`
130			`asm(".set regnum_t0 , 5");`
131			`asm(".set regnum_t1 , 6");`
132			`asm(".set regnum_t2 , 7");`
133			`asm(".set regnum_s0 , 8");`
134			`asm(".set regnum_s1 , 9");`
135			`asm(".set regnum_a0 , 10");`
136			`asm(".set regnum_a1 , 11");`
137			`asm(".set regnum_a2 , 12");`
138			`asm(".set regnum_a3 , 13");`
139			`asm(".set regnum_a4 , 14");`
140			`asm(".set regnum_a5 , 15");`
141			`asm(".set regnum_a6 , 16");`
142			`asm(".set regnum_a7 , 17");`
143			`asm(".set regnum_s2 , 18");`
144			`asm(".set regnum_s3 , 19");`
145			`asm(".set regnum_s4 , 20");`
146			`asm(".set regnum_s5 , 21");`
147			`asm(".set regnum_s6 , 22");`
148			`asm(".set regnum_s7 , 23");`
149			`asm(".set regnum_s8 , 24");`
150			`asm(".set regnum_s9 , 25");`
151			`asm(".set regnum_s10 , 26");`
152			`asm(".set regnum_s11 , 27");`
153			`asm(".set regnum_t3 , 28");`
154			`asm(".set regnum_t4 , 29");`
155			`asm(".set regnum_t5 , 30");`
156			`asm(".set regnum_t6 , 31");`
157	72	zero_gravi
158			`/** Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1) */`
159			`asm(".set RISCV_OPCODE_CUSTOM0 , 0b0001011");`
160			`asm(".set RISCV_OPCODE_CUSTOM1 , 0b0101011");`
161	71	zero_gravi	`/*@}/`
162	54	zero_gravi
163
164	71	zero_gravi	`/********************************************************************//`
165			`* @name Custom instruction R1-type format`
166			`**************************************************************************/`
167			`#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, opcode) \`
168			`({ \`
169			`register uint32_t __return; \`
170			`asm volatile ( \`
171			`"" \`
172			`: [output] "=r" (__return) \`
173			`: [input_i] "r" (rs1) \`
174			`); \`
175			`asm volatile( \`
176			`".word ( \`
177			`(((" #funct7 ") & 0x7f) << 25) \| \`
178			`(((" #funct5 ") & 0x1f) << 20) \| \`
179			`((( regnum_%1 ) & 0x1f) << 15) \| \`
180			`(((" #funct3 ") & 0x07) << 12) \| \`
181			`((( regnum_%0 ) & 0x1f) << 7) \| \`
182			`(((" #opcode ") & 0x7f) << 0) \`
183			`);" \`
184			`: [rd] "=r" (__return) \`
185			`: "r" (rs1) \`
186			`); \`
187			`__return; \`
188			`})`
189	54	zero_gravi
190
191	71	zero_gravi	`/********************************************************************//`
192			`* @name Custom instruction R2-type format`
193			`**************************************************************************/`
194			`#define CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, funct3, opcode) \`
195			`({ \`
196			`register uint32_t __return; \`
197			`asm volatile ( \`
198			`"" \`
199			`: [output] "=r" (__return) \`
200	72	zero_gravi	`: [input_i] "r" (rs1), \`
201			`[input_j] "r" (rs2) \`
202	71	zero_gravi	`); \`
203			`asm volatile ( \`
204			`".word ( \`
205			`(((" #funct7 ") & 0x7f) << 25) \| \`
206			`((( regnum_%2 ) & 0x1f) << 20) \| \`
207			`((( regnum_%1 ) & 0x1f) << 15) \| \`
208			`(((" #funct3 ") & 0x07) << 12) \| \`
209			`((( regnum_%0 ) & 0x1f) << 7) \| \`
210			`(((" #opcode ") & 0x7f) << 0) \`
211			`);" \`
212			`: [rd] "=r" (__return) \`
213	72	zero_gravi	`: "r" (rs1), \`
214			`"r" (rs2) \`
215	71	zero_gravi	`); \`
216			`__return; \`
217			`})`
218	55	zero_gravi
219	54	zero_gravi
220	71	zero_gravi	`/********************************************************************//`
221			`* @name Custom instruction R3-type format`
222			`**************************************************************************/`
223			`#define CUSTOM_INSTR_R3_TYPE(rs3, rs2, rs1, funct3, opcode) \`
224			`({ \`
225			`register uint32_t __return; \`
226			`asm volatile ( \`
227			`"" \`
228			`: [output] "=r" (__return) \`
229	72	zero_gravi	`: [input_i] "r" (rs1), \`
230			`[input_j] "r" (rs2), \`
231			`[input_k] "r" (rs3) \`
232	71	zero_gravi	`); \`
233			`asm volatile ( \`
234			`".word ( \`
235			`((( regnum_%3 ) & 0x1f) << 25) \| \`
236			`((( regnum_%2 ) & 0x1f) << 20) \| \`
237			`((( regnum_%1 ) & 0x1f) << 15) \| \`
238			`(((" #funct3 ") & 0x07) << 12) \| \`
239			`((( regnum_%0 ) & 0x1f) << 7) \| \`
240			`(((" #opcode ") & 0x7f) << 0) \`
241			`);" \`
242			`: [rd] "=r" (__return) \`
243	72	zero_gravi	`: "r" (rs1), \`
244			`"r" (rs2), \`
245			`"r" (rs3) \`
246	71	zero_gravi	`); \`
247			`__return; \`
248			`})`
249	54	zero_gravi
250	55	zero_gravi
251	71	zero_gravi	`/********************************************************************//`
252			`* @name Custom instruction I-type format`
253			`**************************************************************************/`
254			`#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode) \`
255			`({ \`
256			`register uint32_t __return; \`
257			`asm volatile ( \`
258			`"" \`
259			`: [output] "=r" (__return) \`
260			`: [input_i] "r" (rs1) \`
261			`); \`
262			`asm volatile ( \`
263			`".word ( \`
264			`(((" #imm12 ") & 0xfff) << 20) \| \`
265			`((( regnum_%1 ) & 0x1f) << 15) \| \`
266			`(((" #funct3 ") & 0x07) << 12) \| \`
267			`((( regnum_%0 ) & 0x1f) << 7) \| \`
268			`(((" #opcode ") & 0x7f) << 0) \`
269			`);" \`
270			`: [rd] "=r" (__return) \`
271			`: "r" (rs1) \`
272			`); \`
273			`__return; \`
274			`})`
275	54	zero_gravi
276	71	zero_gravi
277	54	zero_gravi	`#endif // neorv32_intrinsics_h`

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