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[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_cpu.c] - Blame information for rev 2

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// #################################################################################################
// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >>                                   #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
// #                                                                                               #
// # Redistribution and use in source and binary forms, with or without modification, are          #
// # permitted provided that the following conditions are met:                                     #
// #                                                                                               #
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
// #    conditions and the following disclaimer.                                                   #
// #                                                                                               #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
// #    conditions and the following disclaimer in the documentation and/or other materials        #
// #    provided with the distribution.                                                            #
// #                                                                                               #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
// #    endorse or promote products derived from this software without specific prior written      #
// #    permission.                                                                                #
// #                                                                                               #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
 * @file neorv32_cpu.c
 * @author Stephan Nolting
 * @brief CPU Core Functions HW driver source file.
 **************************************************************************/
 
#include "neorv32.h"
#include "neorv32_cpu.h"
 
 
/**********************************************************************//**
 * Put CPU into "sleep" mode.
 *
 * @note This function executes the WFI insstruction.
 * The WFI (wait for interrupt) instruction will make the CPU stall until
 * an interupt request is detected. Interrupts have to be globally enabled
 * and at least one external source must be enabled (e.g., the CLIC or the machine
 * timer) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,
 * this will permanently stall the CPU.
 **************************************************************************/
void neorv32_cpu_sleep(void) {
 
  asm volatile ("wfi");
}
 
 
/**********************************************************************//**
 * Enable global CPU interrupts (via MIE flag in mstatus CSR).
 **************************************************************************/
void neorv32_cpu_eint(void) {
 
  const int mask = 1 << CPU_MSTATUS_MIE;
  asm volatile ("csrrsi zero, mstatus, %0" : : "i" (mask));
}
 
 
/**********************************************************************//**
 * Disable global CPU interrupts (via MIE flag in mstatus CSR).
 **************************************************************************/
void neorv32_cpu_dint(void) {
 
  const int mask = 1 << CPU_MSTATUS_MIE;
  asm volatile ("csrrci zero, mstatus, %0" : : "i" (mask));
}
 
 
/**********************************************************************//**
 * Enable specific CPU interrupt.
 *
 * @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
 *
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
 * return 0 if success, 1 if error (invalid irq_sel).
 **************************************************************************/
int neorv32_cpu_irq_enable(uint8_t irq_sel) {
 
  if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
    return 1;
  }
 
  register uint32_t mask = (uint32_t)(1 << irq_sel);
  asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
  return 0;
}
 
 
/**********************************************************************//**
 * Disable specific CPU interrupt.
 *
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
 * return 0 if success, 1 if error (invalid irq_sel).
 **************************************************************************/
int neorv32_cpu_irq_disable(uint8_t irq_sel) {
 
  if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
    return 1;
  }
 
  register uint32_t mask = (uint32_t)(1 << irq_sel);
  asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
  return 0;
}
 
 
/**********************************************************************//**
 * Trigger machine software interrupt.
 *
 * @note The according IRQ has to be enabled via neorv32_cpu_irq_enable(uint8_t irq_sel) and
 * global interrupts must be enabled via neorv32_cpu_eint(void) to trigger an IRQ via software.
 **************************************************************************/
void neorv32_cpu_sw_irq(void) {
 
  register uint32_t mask = (uint32_t)(1 << CPU_MIP_MSIP);
  asm volatile ("csrrs zero, mip, %0" : : "r" (mask));
}
 
 
/**********************************************************************//**
 * Trigger breakpoint exception (via EBREAK instruction).
 **************************************************************************/
void neorv32_cpu_breakpoint(void) {
 
  asm volatile ("ebreak");
}
 
 
/**********************************************************************//**
 * Trigger "environment call" exception (via ECALL instruction).
 **************************************************************************/
void neorv32_cpu_env_call(void) {
 
  asm volatile ("ecall");
}
 
 
/**********************************************************************//**
 * Simple delay function (not very precise) using busy wait.
 *
 * @param[in] time_ms Time in ms to wait.
 **************************************************************************/
void neorv32_cpu_delay_ms(uint32_t time_ms) {
 
  uint32_t clock_speed = neorv32_cpu_csr_read(CSR_MCLOCK) >> 10; // fake divide by 1000
  clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles)
  uint32_t cnt = clock_speed * time_ms;
 
  // one iteration = ~30 cycles
  while (cnt) {
    asm volatile("nop");
    asm volatile("nop");
    asm volatile("nop");
    asm volatile("nop");
    cnt--;
  }
}
 

Line No.	Rev	Author	Line
1	2	zero_gravi	`// #################################################################################################`
2			`// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >> #`
3			`// # ********************************************************************************************* #`
4			`// # BSD 3-Clause License #`
5			`// # #`
6			`// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #`
7			`// # #`
8			`// # Redistribution and use in source and binary forms, with or without modification, are #`
9			`// # permitted provided that the following conditions are met: #`
10			`// # #`
11			`// # 1. Redistributions of source code must retain the above copyright notice, this list of #`
12			`// # conditions and the following disclaimer. #`
13			`// # #`
14			`// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #`
15			`// # conditions and the following disclaimer in the documentation and/or other materials #`
16			`// # provided with the distribution. #`
17			`// # #`
18			`// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #`
19			`// # endorse or promote products derived from this software without specific prior written #`
20			`// # permission. #`
21			`// # #`
22			`// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #`
23			`// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #`
24			`// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #`
25			`// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #`
26			`// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #`
27			`// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #`
28			`// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #`
29			`// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #`
30			`// # OF THE POSSIBILITY OF SUCH DAMAGE. #`
31			`// # ********************************************************************************************* #`
32			`// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #`
33			`// #################################################################################################`
34
35
36			`/********************************************************************//`
37			`* @file neorv32_cpu.c`
38			`* @author Stephan Nolting`
39			`* @brief CPU Core Functions HW driver source file.`
40			`**************************************************************************/`
41
42			`#include "neorv32.h"`
43			`#include "neorv32_cpu.h"`
44
45
46			`/********************************************************************//`
47			`* Put CPU into "sleep" mode.`
48			`*`
49			`* @note This function executes the WFI insstruction.`
50			`* The WFI (wait for interrupt) instruction will make the CPU stall until`
51			`* an interupt request is detected. Interrupts have to be globally enabled`
52			`* and at least one external source must be enabled (e.g., the CLIC or the machine`
53			`* timer) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,`
54			`* this will permanently stall the CPU.`
55			`**************************************************************************/`
56			`void neorv32_cpu_sleep(void) {`
57
58			`asm volatile ("wfi");`
59			`}`
60
61
62			`/********************************************************************//`
63			`* Enable global CPU interrupts (via MIE flag in mstatus CSR).`
64			`**************************************************************************/`
65			`void neorv32_cpu_eint(void) {`
66
67			`const int mask = 1 << CPU_MSTATUS_MIE;`
68			`asm volatile ("csrrsi zero, mstatus, %0" : : "i" (mask));`
69			`}`
70
71
72			`/********************************************************************//`
73			`* Disable global CPU interrupts (via MIE flag in mstatus CSR).`
74			`**************************************************************************/`
75			`void neorv32_cpu_dint(void) {`
76
77			`const int mask = 1 << CPU_MSTATUS_MIE;`
78			`asm volatile ("csrrci zero, mstatus, %0" : : "i" (mask));`
79			`}`
80
81
82			`/********************************************************************//`
83			`* Enable specific CPU interrupt.`
84			`*`
85			`* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.`
86			`*`
87			`* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.`
88			`* return 0 if success, 1 if error (invalid irq_sel).`
89			`**************************************************************************/`
90			`int neorv32_cpu_irq_enable(uint8_t irq_sel) {`
91
92			`if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {`
93			`return 1;`
94			`}`
95
96			`register uint32_t mask = (uint32_t)(1 << irq_sel);`
97			`asm volatile ("csrrs zero, mie, %0" : : "r" (mask));`
98			`return 0;`
99			`}`
100
101
102			`/********************************************************************//`
103			`* Disable specific CPU interrupt.`
104			`*`
105			`* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.`
106			`* return 0 if success, 1 if error (invalid irq_sel).`
107			`**************************************************************************/`
108			`int neorv32_cpu_irq_disable(uint8_t irq_sel) {`
109
110			`if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {`
111			`return 1;`
112			`}`
113
114			`register uint32_t mask = (uint32_t)(1 << irq_sel);`
115			`asm volatile ("csrrc zero, mie, %0" : : "r" (mask));`
116			`return 0;`
117			`}`
118
119
120			`/********************************************************************//`
121			`* Trigger machine software interrupt.`
122			`*`
123			`* @note The according IRQ has to be enabled via neorv32_cpu_irq_enable(uint8_t irq_sel) and`
124			`* global interrupts must be enabled via neorv32_cpu_eint(void) to trigger an IRQ via software.`
125			`**************************************************************************/`
126			`void neorv32_cpu_sw_irq(void) {`
127
128			`register uint32_t mask = (uint32_t)(1 << CPU_MIP_MSIP);`
129			`asm volatile ("csrrs zero, mip, %0" : : "r" (mask));`
130			`}`
131
132
133			`/********************************************************************//`
134			`* Trigger breakpoint exception (via EBREAK instruction).`
135			`**************************************************************************/`
136			`void neorv32_cpu_breakpoint(void) {`
137
138			`asm volatile ("ebreak");`
139			`}`
140
141
142			`/********************************************************************//`
143			`* Trigger "environment call" exception (via ECALL instruction).`
144			`**************************************************************************/`
145			`void neorv32_cpu_env_call(void) {`
146
147			`asm volatile ("ecall");`
148			`}`
149
150
151			`/********************************************************************//`
152			`* Simple delay function (not very precise) using busy wait.`
153			`*`
154			`* @param[in] time_ms Time in ms to wait.`
155			`**************************************************************************/`
156			`void neorv32_cpu_delay_ms(uint32_t time_ms) {`
157
158			`uint32_t clock_speed = neorv32_cpu_csr_read(CSR_MCLOCK) >> 10; // fake divide by 1000`
159			`clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles)`
160			`uint32_t cnt = clock_speed * time_ms;`
161
162			`// one iteration = ~30 cycles`
163			`while (cnt) {`
164			`asm volatile("nop");`
165			`asm volatile("nop");`
166			`asm volatile("nop");`
167			`asm volatile("nop");`
168			`cnt--;`
169			`}`
170			`}`
171

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[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_cpu.c] - Blame information for rev 2