1 |
2 |
zero_gravi |
// #################################################################################################
|
2 |
|
|
// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >> #
|
3 |
|
|
// # ********************************************************************************************* #
|
4 |
|
|
// # BSD 3-Clause License #
|
5 |
|
|
// # #
|
6 |
|
|
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
7 |
|
|
// # #
|
8 |
|
|
// # Redistribution and use in source and binary forms, with or without modification, are #
|
9 |
|
|
// # permitted provided that the following conditions are met: #
|
10 |
|
|
// # #
|
11 |
|
|
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
12 |
|
|
// # conditions and the following disclaimer. #
|
13 |
|
|
// # #
|
14 |
|
|
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
15 |
|
|
// # conditions and the following disclaimer in the documentation and/or other materials #
|
16 |
|
|
// # provided with the distribution. #
|
17 |
|
|
// # #
|
18 |
|
|
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
19 |
|
|
// # endorse or promote products derived from this software without specific prior written #
|
20 |
|
|
// # permission. #
|
21 |
|
|
// # #
|
22 |
|
|
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
23 |
|
|
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
24 |
|
|
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
25 |
|
|
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
26 |
|
|
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
27 |
|
|
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
28 |
|
|
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
29 |
|
|
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
30 |
|
|
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
31 |
|
|
// # ********************************************************************************************* #
|
32 |
|
|
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
33 |
|
|
// #################################################################################################
|
34 |
|
|
|
35 |
|
|
|
36 |
|
|
/**********************************************************************//**
|
37 |
|
|
* @file neorv32_cpu.c
|
38 |
|
|
* @author Stephan Nolting
|
39 |
|
|
* @brief CPU Core Functions HW driver source file.
|
40 |
|
|
**************************************************************************/
|
41 |
|
|
|
42 |
|
|
#include "neorv32.h"
|
43 |
|
|
#include "neorv32_cpu.h"
|
44 |
|
|
|
45 |
|
|
|
46 |
|
|
/**********************************************************************//**
|
47 |
|
|
* Enable specific CPU interrupt.
|
48 |
|
|
*
|
49 |
|
|
* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
|
50 |
|
|
*
|
51 |
|
|
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
|
52 |
12 |
zero_gravi |
* @return 0 if success, 1 if error (invalid irq_sel).
|
53 |
2 |
zero_gravi |
**************************************************************************/
|
54 |
|
|
int neorv32_cpu_irq_enable(uint8_t irq_sel) {
|
55 |
|
|
|
56 |
14 |
zero_gravi |
if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
|
57 |
|
|
(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
|
58 |
2 |
zero_gravi |
return 1;
|
59 |
|
|
}
|
60 |
|
|
|
61 |
|
|
register uint32_t mask = (uint32_t)(1 << irq_sel);
|
62 |
|
|
asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
|
63 |
|
|
return 0;
|
64 |
|
|
}
|
65 |
|
|
|
66 |
|
|
|
67 |
|
|
/**********************************************************************//**
|
68 |
|
|
* Disable specific CPU interrupt.
|
69 |
|
|
*
|
70 |
|
|
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
|
71 |
12 |
zero_gravi |
* @return 0 if success, 1 if error (invalid irq_sel).
|
72 |
2 |
zero_gravi |
**************************************************************************/
|
73 |
|
|
int neorv32_cpu_irq_disable(uint8_t irq_sel) {
|
74 |
|
|
|
75 |
14 |
zero_gravi |
if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
|
76 |
|
|
(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
|
77 |
2 |
zero_gravi |
return 1;
|
78 |
|
|
}
|
79 |
|
|
|
80 |
|
|
register uint32_t mask = (uint32_t)(1 << irq_sel);
|
81 |
|
|
asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
|
82 |
|
|
return 0;
|
83 |
|
|
}
|
84 |
|
|
|
85 |
|
|
|
86 |
|
|
/**********************************************************************//**
|
87 |
12 |
zero_gravi |
* Get cycle count from cycle[h].
|
88 |
|
|
*
|
89 |
|
|
* @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR.
|
90 |
|
|
*
|
91 |
|
|
* @return Current cycle counter (64 bit).
|
92 |
|
|
**************************************************************************/
|
93 |
|
|
uint64_t neorv32_cpu_get_cycle(void) {
|
94 |
|
|
|
95 |
|
|
union {
|
96 |
|
|
uint64_t uint64;
|
97 |
|
|
uint32_t uint32[sizeof(uint64_t)/2];
|
98 |
|
|
} cycles;
|
99 |
|
|
|
100 |
|
|
uint32_t tmp1, tmp2, tmp3;
|
101 |
|
|
while(1) {
|
102 |
|
|
tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH);
|
103 |
|
|
tmp2 = neorv32_cpu_csr_read(CSR_CYCLE);
|
104 |
|
|
tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH);
|
105 |
|
|
if (tmp1 == tmp3) {
|
106 |
|
|
break;
|
107 |
|
|
}
|
108 |
|
|
}
|
109 |
|
|
|
110 |
|
|
cycles.uint32[0] = tmp2;
|
111 |
|
|
cycles.uint32[1] = tmp3;
|
112 |
|
|
|
113 |
|
|
return cycles.uint64;
|
114 |
|
|
}
|
115 |
|
|
|
116 |
|
|
|
117 |
|
|
/**********************************************************************//**
|
118 |
|
|
* Set mcycle[h] counter.
|
119 |
|
|
*
|
120 |
|
|
* @param[in] value New value for mcycle[h] CSR (64-bit).
|
121 |
|
|
**************************************************************************/
|
122 |
|
|
void neorv32_cpu_set_mcycle(uint64_t value) {
|
123 |
|
|
|
124 |
|
|
union {
|
125 |
|
|
uint64_t uint64;
|
126 |
|
|
uint32_t uint32[sizeof(uint64_t)/2];
|
127 |
|
|
} cycles;
|
128 |
|
|
|
129 |
|
|
cycles.uint64 = value;
|
130 |
|
|
|
131 |
|
|
neorv32_cpu_csr_write(CSR_MCYCLE, 0);
|
132 |
|
|
neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]);
|
133 |
|
|
neorv32_cpu_csr_write(CSR_MCYCLE, cycles.uint32[0]);
|
134 |
|
|
}
|
135 |
|
|
|
136 |
|
|
|
137 |
|
|
/**********************************************************************//**
|
138 |
|
|
* Get retired instructions counter from instret[h].
|
139 |
|
|
*
|
140 |
|
|
* @note The instret[h] CSR is shadowed copy of the instret[h] CSR.
|
141 |
|
|
*
|
142 |
|
|
* @return Current instructions counter (64 bit).
|
143 |
|
|
**************************************************************************/
|
144 |
|
|
uint64_t neorv32_cpu_get_instret(void) {
|
145 |
|
|
|
146 |
|
|
union {
|
147 |
|
|
uint64_t uint64;
|
148 |
|
|
uint32_t uint32[sizeof(uint64_t)/2];
|
149 |
|
|
} cycles;
|
150 |
|
|
|
151 |
|
|
uint32_t tmp1, tmp2, tmp3;
|
152 |
|
|
while(1) {
|
153 |
|
|
tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH);
|
154 |
|
|
tmp2 = neorv32_cpu_csr_read(CSR_INSTRET);
|
155 |
|
|
tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH);
|
156 |
|
|
if (tmp1 == tmp3) {
|
157 |
|
|
break;
|
158 |
|
|
}
|
159 |
|
|
}
|
160 |
|
|
|
161 |
|
|
cycles.uint32[0] = tmp2;
|
162 |
|
|
cycles.uint32[1] = tmp3;
|
163 |
|
|
|
164 |
|
|
return cycles.uint64;
|
165 |
|
|
}
|
166 |
|
|
|
167 |
|
|
|
168 |
|
|
/**********************************************************************//**
|
169 |
|
|
* Set retired instructions counter minstret[h].
|
170 |
|
|
*
|
171 |
|
|
* @param[in] value New value for mcycle[h] CSR (64-bit).
|
172 |
|
|
**************************************************************************/
|
173 |
|
|
void neorv32_cpu_set_minstret(uint64_t value) {
|
174 |
|
|
|
175 |
|
|
union {
|
176 |
|
|
uint64_t uint64;
|
177 |
|
|
uint32_t uint32[sizeof(uint64_t)/2];
|
178 |
|
|
} cycles;
|
179 |
|
|
|
180 |
|
|
cycles.uint64 = value;
|
181 |
|
|
|
182 |
|
|
neorv32_cpu_csr_write(CSR_MINSTRET, 0);
|
183 |
|
|
neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]);
|
184 |
|
|
neorv32_cpu_csr_write(CSR_MINSTRET, cycles.uint32[0]);
|
185 |
|
|
}
|
186 |
|
|
|
187 |
|
|
|
188 |
|
|
/**********************************************************************//**
|
189 |
|
|
* Get current system time from time[h] CSR.
|
190 |
|
|
*
|
191 |
|
|
* @note This function requires the MTIME system timer to be implemented.
|
192 |
|
|
*
|
193 |
|
|
* @return Current system time (64 bit).
|
194 |
|
|
**************************************************************************/
|
195 |
|
|
uint64_t neorv32_cpu_get_systime(void) {
|
196 |
|
|
|
197 |
|
|
union {
|
198 |
|
|
uint64_t uint64;
|
199 |
|
|
uint32_t uint32[sizeof(uint64_t)/2];
|
200 |
|
|
} cycles;
|
201 |
|
|
|
202 |
|
|
uint32_t tmp1, tmp2, tmp3;
|
203 |
|
|
while(1) {
|
204 |
|
|
tmp1 = neorv32_cpu_csr_read(CSR_TIMEH);
|
205 |
|
|
tmp2 = neorv32_cpu_csr_read(CSR_TIME);
|
206 |
|
|
tmp3 = neorv32_cpu_csr_read(CSR_TIMEH);
|
207 |
|
|
if (tmp1 == tmp3) {
|
208 |
|
|
break;
|
209 |
|
|
}
|
210 |
|
|
}
|
211 |
|
|
|
212 |
|
|
cycles.uint32[0] = tmp2;
|
213 |
|
|
cycles.uint32[1] = tmp3;
|
214 |
|
|
|
215 |
|
|
return cycles.uint64;
|
216 |
|
|
}
|
217 |
|
|
|
218 |
|
|
|
219 |
|
|
/**********************************************************************//**
|
220 |
39 |
zero_gravi |
* Simple delay function using busy wait.
|
221 |
2 |
zero_gravi |
*
|
222 |
39 |
zero_gravi |
* @warning This function requires the cycle CSR(s). Hence, the Zicsr extension is mandatory.
|
223 |
|
|
*
|
224 |
2 |
zero_gravi |
* @param[in] time_ms Time in ms to wait.
|
225 |
|
|
**************************************************************************/
|
226 |
|
|
void neorv32_cpu_delay_ms(uint32_t time_ms) {
|
227 |
|
|
|
228 |
39 |
zero_gravi |
uint64_t time_resume = neorv32_cpu_get_cycle();
|
229 |
2 |
zero_gravi |
|
230 |
39 |
zero_gravi |
uint32_t clock = SYSINFO_CLK; // clock ticks per second
|
231 |
|
|
clock = clock / 1000; // clock ticks per ms
|
232 |
|
|
|
233 |
|
|
uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);
|
234 |
|
|
time_resume += wait_cycles;
|
235 |
|
|
|
236 |
|
|
while(1) {
|
237 |
|
|
if (neorv32_cpu_get_cycle() >= time_resume) {
|
238 |
|
|
break;
|
239 |
|
|
}
|
240 |
2 |
zero_gravi |
}
|
241 |
|
|
}
|
242 |
|
|
|
243 |
15 |
zero_gravi |
|
244 |
|
|
/**********************************************************************//**
|
245 |
|
|
* Switch from privilege mode MACHINE to privilege mode USER.
|
246 |
|
|
*
|
247 |
39 |
zero_gravi |
* @warning This function requires the U extension to be implemented.
|
248 |
15 |
zero_gravi |
**************************************************************************/
|
249 |
|
|
void __attribute__((naked)) neorv32_cpu_goto_user_mode(void) {
|
250 |
|
|
|
251 |
35 |
zero_gravi |
// make sure to use NO registers in here! -> naked
|
252 |
15 |
zero_gravi |
|
253 |
39 |
zero_gravi |
asm volatile ("csrw mepc, ra \n\t" // move return address to mepc so we can return using "mret". also, we can now use ra as general purpose register in here
|
254 |
35 |
zero_gravi |
"li ra, %[input_imm] \n\t" // bit mask to clear the two MPP bits
|
255 |
|
|
"csrrc zero, mstatus, ra \n\t" // clear MPP bits -> MPP=u-mode
|
256 |
|
|
"mret \n\t" // return and switch to user mode
|
257 |
|
|
: : [input_imm] "i" ((1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L)));
|
258 |
15 |
zero_gravi |
}
|
259 |
39 |
zero_gravi |
|
260 |
|
|
|
261 |
|
|
/**********************************************************************//**
|
262 |
|
|
* Atomic compare-and-swap operation (for implemeneting semaphores and mutexes).
|
263 |
|
|
*
|
264 |
|
|
* @warning This function requires the A (atomic) CPU extension.
|
265 |
|
|
*
|
266 |
|
|
* @param[in] addr Address of memory location.
|
267 |
|
|
* @param[in] expected Expected value (for comparison).
|
268 |
|
|
* @param[in] desired Desired value (new value).
|
269 |
|
|
* @return Returns 0 on success, 1 on failure.
|
270 |
|
|
**************************************************************************/
|
271 |
|
|
int __attribute__ ((noinline)) neorv32_cpu_atomic_cas(uint32_t addr, uint32_t expected, uint32_t desired) {
|
272 |
|
|
#ifdef __riscv_atomic
|
273 |
|
|
|
274 |
|
|
register uint32_t addr_reg = addr;
|
275 |
|
|
register uint32_t des_reg = desired;
|
276 |
|
|
register uint32_t tmp_reg;
|
277 |
|
|
|
278 |
|
|
// load original value + reservation (lock)
|
279 |
|
|
asm volatile ("lr.w %[result], (%[input])" : [result] "=r" (tmp_reg) : [input] "r" (addr_reg));
|
280 |
|
|
|
281 |
|
|
if (tmp_reg != expected) {
|
282 |
|
|
asm volatile ("lw x0, 0(%[input])" : : [input] "r" (addr_reg)); // clear reservation lock
|
283 |
|
|
return 1;
|
284 |
|
|
}
|
285 |
|
|
|
286 |
|
|
// store-conditional
|
287 |
|
|
asm volatile ("sc.w %[result], %[input_i], (%[input_j])" : [result] "=r" (tmp_reg) : [input_i] "r" (des_reg), [input_j] "r" (addr_reg));
|
288 |
|
|
|
289 |
|
|
if (tmp_reg) {
|
290 |
|
|
return 1;
|
291 |
|
|
}
|
292 |
|
|
|
293 |
|
|
return 0;
|
294 |
|
|
#else
|
295 |
|
|
return 1; // A extension not implemented -Y always fail
|
296 |
|
|
#endif
|
297 |
|
|
}
|
298 |
40 |
zero_gravi |
|
299 |
|
|
|
300 |
|
|
/**********************************************************************//**
|
301 |
|
|
* Physical memory protection (PMP): Get minimal region size (granularity).
|
302 |
|
|
*
|
303 |
|
|
* @warning This function overrides PMPCFG0[0] and PMPADDR0 CSRs.
|
304 |
|
|
*
|
305 |
|
|
* @warning This function requires the PMP CPU extension.
|
306 |
|
|
*
|
307 |
|
|
* @return Returns minimal region size in bytes; Returns 0 on failure.
|
308 |
|
|
**************************************************************************/
|
309 |
|
|
uint32_t neorv32_cpu_pmp_get_granularity(void) {
|
310 |
|
|
|
311 |
|
|
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) == 0) {
|
312 |
|
|
return 0; // PMP not implemented
|
313 |
|
|
}
|
314 |
|
|
|
315 |
|
|
// check min granulartiy
|
316 |
|
|
uint32_t tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
|
317 |
|
|
tmp &= 0xffffff00; // disable entry 0
|
318 |
|
|
neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
|
319 |
|
|
neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffffff);
|
320 |
|
|
uint32_t tmp_a = neorv32_cpu_csr_read(CSR_PMPADDR0);
|
321 |
|
|
|
322 |
|
|
uint32_t i;
|
323 |
|
|
|
324 |
|
|
// find least-significat set bit
|
325 |
|
|
for (i=31; i!=0; i--) {
|
326 |
|
|
if (((tmp_a >> i) & 1) == 0) {
|
327 |
|
|
break;
|
328 |
|
|
}
|
329 |
|
|
}
|
330 |
|
|
|
331 |
|
|
return (uint32_t)(1 << (i+1+2));
|
332 |
|
|
}
|
333 |
|
|
|
334 |
|
|
|
335 |
|
|
/**********************************************************************//**
|
336 |
|
|
* Physical memory protection (PMP): Configure region.
|
337 |
|
|
*
|
338 |
|
|
* @note Using NAPOT mode - page base address has to be naturally aligned.
|
339 |
|
|
*
|
340 |
|
|
* @warning This function requires the PMP CPU extension.
|
341 |
|
|
*
|
342 |
|
|
* @param[in] index Region number (index, 0..max_regions-1).
|
343 |
|
|
* @param[in] base Region base address (has to be naturally aligned!).
|
344 |
|
|
* @param[in] size Region size, has to be a power of 2 (min 8 bytes or according to HW's PMP.granularity configuration).
|
345 |
|
|
* @param[in] config Region configuration (attributes) byte (for PMPCFGx).
|
346 |
|
|
* @return Returns 0 on success, 1 on failure.
|
347 |
|
|
**************************************************************************/
|
348 |
|
|
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config) {
|
349 |
|
|
|
350 |
|
|
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) == 0) {
|
351 |
|
|
return 1; // PMP not implemented
|
352 |
|
|
}
|
353 |
|
|
|
354 |
|
|
if (size < 8) {
|
355 |
|
|
return 1; // minimal region size is 8 bytes
|
356 |
|
|
}
|
357 |
|
|
|
358 |
|
|
if ((size & (size - 1)) != 0) {
|
359 |
|
|
return 1; // region size is not a power of two
|
360 |
|
|
}
|
361 |
|
|
|
362 |
|
|
// setup configuration
|
363 |
|
|
uint32_t tmp;
|
364 |
|
|
uint32_t config_int = ((uint32_t)config) << ((index%4)*8);
|
365 |
|
|
uint32_t config_mask = ((uint32_t)0xFF) << ((index%4)*8);
|
366 |
|
|
config_mask = ~config_mask;
|
367 |
|
|
|
368 |
|
|
// clear old configuration
|
369 |
|
|
if (index < 3) {
|
370 |
|
|
tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
|
371 |
|
|
tmp &= config_mask; // clear old config
|
372 |
|
|
neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
|
373 |
|
|
}
|
374 |
|
|
else {
|
375 |
|
|
tmp = neorv32_cpu_csr_read(CSR_PMPCFG1);
|
376 |
|
|
tmp &= config_mask; // clear old config
|
377 |
|
|
neorv32_cpu_csr_write(CSR_PMPCFG1, tmp);
|
378 |
|
|
}
|
379 |
|
|
|
380 |
|
|
// set base address and region size
|
381 |
|
|
uint32_t addr_mask = ~((size - 1) >> 2);
|
382 |
|
|
uint32_t size_mask = (size - 1) >> 3;
|
383 |
|
|
|
384 |
|
|
tmp = base & addr_mask;
|
385 |
|
|
tmp = tmp | size_mask;
|
386 |
|
|
|
387 |
|
|
switch(index & 7) {
|
388 |
|
|
case 0: neorv32_cpu_csr_write(CSR_PMPADDR0, tmp); break;
|
389 |
|
|
case 1: neorv32_cpu_csr_write(CSR_PMPADDR1, tmp); break;
|
390 |
|
|
case 2: neorv32_cpu_csr_write(CSR_PMPADDR2, tmp); break;
|
391 |
|
|
case 3: neorv32_cpu_csr_write(CSR_PMPADDR3, tmp); break;
|
392 |
|
|
case 4: neorv32_cpu_csr_write(CSR_PMPADDR4, tmp); break;
|
393 |
|
|
case 5: neorv32_cpu_csr_write(CSR_PMPADDR5, tmp); break;
|
394 |
|
|
case 6: neorv32_cpu_csr_write(CSR_PMPADDR6, tmp); break;
|
395 |
|
|
case 7: neorv32_cpu_csr_write(CSR_PMPADDR7, tmp); break;
|
396 |
|
|
default: break;
|
397 |
|
|
}
|
398 |
|
|
|
399 |
|
|
// wait for HW to computer PMP-internal stuff (address masks)
|
400 |
|
|
for (tmp=0; tmp<16; tmp++) {
|
401 |
|
|
asm volatile ("nop");
|
402 |
|
|
}
|
403 |
|
|
|
404 |
|
|
// set new configuration
|
405 |
|
|
if (index < 3) {
|
406 |
|
|
tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
|
407 |
|
|
tmp |= config_int; // set new config
|
408 |
|
|
neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
|
409 |
|
|
}
|
410 |
|
|
else {
|
411 |
|
|
tmp = neorv32_cpu_csr_read(CSR_PMPCFG1);
|
412 |
|
|
tmp |= config_int; // set new config
|
413 |
|
|
neorv32_cpu_csr_write(CSR_PMPCFG1, tmp);
|
414 |
|
|
}
|
415 |
|
|
|
416 |
|
|
return 0;
|
417 |
|
|
}
|