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[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_cpu.c] - Blame information for rev 64

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1 2 zero_gravi
// #################################################################################################
2
// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >>                                   #
3
// # ********************************************************************************************* #
4
// # BSD 3-Clause License                                                                          #
5
// #                                                                                               #
6 42 zero_gravi
// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi
// #                                                                                               #
8
// # Redistribution and use in source and binary forms, with or without modification, are          #
9
// # permitted provided that the following conditions are met:                                     #
10
// #                                                                                               #
11
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12
// #    conditions and the following disclaimer.                                                   #
13
// #                                                                                               #
14
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15
// #    conditions and the following disclaimer in the documentation and/or other materials        #
16
// #    provided with the distribution.                                                            #
17
// #                                                                                               #
18
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19
// #    endorse or promote products derived from this software without specific prior written      #
20
// #    permission.                                                                                #
21
// #                                                                                               #
22
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
31
// # ********************************************************************************************* #
32
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33
// #################################################################################################
34
 
35
 
36
/**********************************************************************//**
37
 * @file neorv32_cpu.c
38
 * @author Stephan Nolting
39
 * @brief CPU Core Functions HW driver source file.
40
 **************************************************************************/
41
 
42
#include "neorv32.h"
43
#include "neorv32_cpu.h"
44
 
45
 
46 53 zero_gravi
/**********************************************************************//**
47
 * Unavailable extensions warning.
48
 **************************************************************************/
49
#if defined __riscv_f || (__riscv_flen == 32)
50 60 zero_gravi
  #warning Single-precision floating-point extension <F/Zfinx> is WORK-IN-PROGRESS and there is NO NATIVE SUPPORT BY THE COMPILER yet!
51 53 zero_gravi
#endif
52 45 zero_gravi
 
53 53 zero_gravi
#if defined __riscv_d || (__riscv_flen == 64)
54
  #error Double-precision floating-point extension <D/Zdinx> is NOT supported!
55
#endif
56
 
57
#if (__riscv_xlen > 32)
58
  #error Only 32-bit <rv32> is supported!
59
#endif
60
 
61
#ifdef __riscv_b
62
  #warning Bit-manipulation extension <B> is still experimental (non-ratified) and does not support all <Zb*> subsets yet.
63
#endif
64
 
65
#ifdef __riscv_fdiv
66
  #warning Floating-point division instruction <FDIV> is NOT supported yet!
67
#endif
68
 
69
#ifdef __riscv_fsqrt
70
  #warning Floating-point square root instruction <FSQRT> is NOT supported yet!
71
#endif
72
 
73
 
74 2 zero_gravi
/**********************************************************************//**
75 45 zero_gravi
 * >Private< helper functions.
76
 **************************************************************************/
77 47 zero_gravi
static int __neorv32_cpu_irq_id_check(uint8_t irq_sel);
78 45 zero_gravi
static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index);
79
static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data);
80
 
81
 
82
/**********************************************************************//**
83 47 zero_gravi
 * Private function: Check IRQ id.
84
 *
85
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
86
 * @return 0 if success, 1 if error (invalid irq_sel).
87
 **************************************************************************/
88
static int __neorv32_cpu_irq_id_check(uint8_t irq_sel) {
89
 
90 48 zero_gravi
  if ((irq_sel == CSR_MIE_MSIE) || (irq_sel == CSR_MIE_MTIE) || (irq_sel == CSR_MIE_MEIE) ||
91
     ((irq_sel >= CSR_MIE_FIRQ0E) && (irq_sel <= CSR_MIE_FIRQ15E))) {
92 47 zero_gravi
    return 0;
93
  }
94
  else {
95
    return 1;
96
  }
97
}
98
 
99
 
100
/**********************************************************************//**
101 2 zero_gravi
 * Enable specific CPU interrupt.
102
 *
103
 * @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
104
 *
105 42 zero_gravi
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
106 12 zero_gravi
 * @return 0 if success, 1 if error (invalid irq_sel).
107 2 zero_gravi
 **************************************************************************/
108
int neorv32_cpu_irq_enable(uint8_t irq_sel) {
109
 
110 47 zero_gravi
  // check IRQ id
111
  if (__neorv32_cpu_irq_id_check(irq_sel)) {
112 2 zero_gravi
    return 1;
113
  }
114
 
115
  register uint32_t mask = (uint32_t)(1 << irq_sel);
116
  asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
117
  return 0;
118
}
119
 
120
 
121
/**********************************************************************//**
122
 * Disable specific CPU interrupt.
123
 *
124 42 zero_gravi
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
125 12 zero_gravi
 * @return 0 if success, 1 if error (invalid irq_sel).
126 2 zero_gravi
 **************************************************************************/
127
int neorv32_cpu_irq_disable(uint8_t irq_sel) {
128
 
129 47 zero_gravi
  // check IRQ id
130
  if (__neorv32_cpu_irq_id_check(irq_sel)) {
131 2 zero_gravi
    return 1;
132
  }
133
 
134
  register uint32_t mask = (uint32_t)(1 << irq_sel);
135
  asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
136
  return 0;
137
}
138
 
139
 
140
/**********************************************************************//**
141 12 zero_gravi
 * Get cycle count from cycle[h].
142
 *
143
 * @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR.
144
 *
145
 * @return Current cycle counter (64 bit).
146
 **************************************************************************/
147
uint64_t neorv32_cpu_get_cycle(void) {
148
 
149
  union {
150
    uint64_t uint64;
151
    uint32_t uint32[sizeof(uint64_t)/2];
152
  } cycles;
153
 
154 64 zero_gravi
  register uint32_t tmp1, tmp2, tmp3;
155 12 zero_gravi
  while(1) {
156
    tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH);
157
    tmp2 = neorv32_cpu_csr_read(CSR_CYCLE);
158
    tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH);
159
    if (tmp1 == tmp3) {
160
      break;
161
    }
162
  }
163
 
164
  cycles.uint32[0] = tmp2;
165
  cycles.uint32[1] = tmp3;
166
 
167
  return cycles.uint64;
168
}
169
 
170
 
171
/**********************************************************************//**
172
 * Set mcycle[h] counter.
173
 *
174
 * @param[in] value New value for mcycle[h] CSR (64-bit).
175
 **************************************************************************/
176
void neorv32_cpu_set_mcycle(uint64_t value) {
177
 
178
  union {
179
    uint64_t uint64;
180
    uint32_t uint32[sizeof(uint64_t)/2];
181
  } cycles;
182
 
183
  cycles.uint64 = value;
184
 
185
  neorv32_cpu_csr_write(CSR_MCYCLE,  0);
186
  neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]);
187
  neorv32_cpu_csr_write(CSR_MCYCLE,  cycles.uint32[0]);
188
}
189
 
190
 
191
/**********************************************************************//**
192
 * Get retired instructions counter from instret[h].
193
 *
194
 * @note The instret[h] CSR is shadowed copy of the instret[h] CSR.
195
 *
196
 * @return Current instructions counter (64 bit).
197
 **************************************************************************/
198
uint64_t neorv32_cpu_get_instret(void) {
199
 
200
  union {
201
    uint64_t uint64;
202
    uint32_t uint32[sizeof(uint64_t)/2];
203
  } cycles;
204
 
205 64 zero_gravi
  register uint32_t tmp1, tmp2, tmp3;
206 12 zero_gravi
  while(1) {
207
    tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH);
208
    tmp2 = neorv32_cpu_csr_read(CSR_INSTRET);
209
    tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH);
210
    if (tmp1 == tmp3) {
211
      break;
212
    }
213
  }
214
 
215
  cycles.uint32[0] = tmp2;
216
  cycles.uint32[1] = tmp3;
217
 
218
  return cycles.uint64;
219
}
220
 
221
 
222
/**********************************************************************//**
223
 * Set retired instructions counter minstret[h].
224
 *
225
 * @param[in] value New value for mcycle[h] CSR (64-bit).
226
 **************************************************************************/
227
void neorv32_cpu_set_minstret(uint64_t value) {
228
 
229
  union {
230
    uint64_t uint64;
231
    uint32_t uint32[sizeof(uint64_t)/2];
232
  } cycles;
233
 
234
  cycles.uint64 = value;
235
 
236
  neorv32_cpu_csr_write(CSR_MINSTRET,  0);
237
  neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]);
238
  neorv32_cpu_csr_write(CSR_MINSTRET,  cycles.uint32[0]);
239
}
240
 
241
 
242
/**********************************************************************//**
243
 * Get current system time from time[h] CSR.
244
 *
245
 * @note This function requires the MTIME system timer to be implemented.
246
 *
247
 * @return Current system time (64 bit).
248
 **************************************************************************/
249
uint64_t neorv32_cpu_get_systime(void) {
250
 
251
  union {
252
    uint64_t uint64;
253
    uint32_t uint32[sizeof(uint64_t)/2];
254
  } cycles;
255
 
256 64 zero_gravi
  register uint32_t tmp1, tmp2, tmp3;
257 12 zero_gravi
  while(1) {
258
    tmp1 = neorv32_cpu_csr_read(CSR_TIMEH);
259
    tmp2 = neorv32_cpu_csr_read(CSR_TIME);
260
    tmp3 = neorv32_cpu_csr_read(CSR_TIMEH);
261
    if (tmp1 == tmp3) {
262
      break;
263
    }
264
  }
265
 
266
  cycles.uint32[0] = tmp2;
267
  cycles.uint32[1] = tmp3;
268
 
269
  return cycles.uint64;
270
}
271
 
272
 
273
/**********************************************************************//**
274 64 zero_gravi
 * Delay function using busy wait.
275 2 zero_gravi
 *
276 64 zero_gravi
 * @note This function uses the time CSRs (from int./ext. MTIME). A simple ASM loop
277
 * is used as fall back if system timer is not advancing (no MTIME available).
278 39 zero_gravi
 *
279 64 zero_gravi
 * @warning Delay time might be less precise if M extensions is not available
280
 * (especially if MTIME unit is not available).
281
 *
282
 * @param[in] time_ms Time in ms to wait (unsigned 32-bit).
283 2 zero_gravi
 **************************************************************************/
284 64 zero_gravi
void neorv32_cpu_delay_ms(uint32_t time_ms) {
285 2 zero_gravi
 
286 64 zero_gravi
  uint32_t clock = NEORV32_SYSINFO.CLK; // clock ticks per second
287
  clock = clock / 1000; // clock ticks per ms
288 2 zero_gravi
 
289 64 zero_gravi
  uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);
290
 
291
  register uint64_t tmp = neorv32_cpu_get_systime();
292
  if (neorv32_cpu_get_systime() > tmp) { // system time advancing (MTIME available and running)?
293
 
294
    // use MTIME machine timer
295
    tmp += wait_cycles;
296
    while(1) {
297
      if (neorv32_cpu_get_systime() >= tmp) {
298
        break;
299
      }
300
    }
301 56 zero_gravi
  }
302 64 zero_gravi
  else {
303
    // use ASM loop
304
    // warning! not really precise (especially if M extensions is not available)!
305 56 zero_gravi
 
306 64 zero_gravi
    const uint32_t loop_cycles_c = 16; // clock cycles per iteration of the ASM loop
307
    uint32_t iterations = (uint32_t)(wait_cycles / loop_cycles_c);
308 39 zero_gravi
 
309 64 zero_gravi
    asm volatile (" .balign 4                                        \n" // make sure this is 32-bit aligned
310
                  " __neorv32_cpu_delay_ms_start:                    \n"
311
                  " beq  %[cnt_r], zero, __neorv32_cpu_delay_ms_end  \n" // 3 cycles (not taken)
312
                  " beq  %[cnt_r], zero, __neorv32_cpu_delay_ms_end  \n" // 3 cycles (never taken)
313
                  " addi %[cnt_w], %[cnt_r], -1                      \n" // 2 cycles
314
                  " nop                                              \n" // 2 cycles
315
                  " j    __neorv32_cpu_delay_ms_start                \n" // 6 cycles
316
                  " __neorv32_cpu_delay_ms_end: "
317
                  : [cnt_w] "=r" (iterations) : [cnt_r] "r" (iterations));
318
  }
319 2 zero_gravi
}
320
 
321 15 zero_gravi
 
322
/**********************************************************************//**
323
 * Switch from privilege mode MACHINE to privilege mode USER.
324
 *
325 39 zero_gravi
 * @warning This function requires the U extension to be implemented.
326 15 zero_gravi
 **************************************************************************/
327
void __attribute__((naked)) neorv32_cpu_goto_user_mode(void) {
328
 
329 35 zero_gravi
  // make sure to use NO registers in here! -> naked
330 15 zero_gravi
 
331 56 zero_gravi
  asm volatile ("csrw mepc, ra           \n" // move return address to mepc so we can return using "mret". also, we can now use ra as general purpose register in here
332
                "li ra, %[input_imm]     \n" // bit mask to clear the two MPP bits
333
                "csrrc zero, mstatus, ra \n" // clear MPP bits -> MPP=u-mode
334
                "mret                    \n" // return and switch to user mode
335 42 zero_gravi
                :  : [input_imm] "i" ((1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L)));
336 15 zero_gravi
}
337 39 zero_gravi
 
338
 
339
/**********************************************************************//**
340 42 zero_gravi
 * Physical memory protection (PMP): Get number of available regions.
341
 *
342
 * @warning This function overrides all available PMPCFG* CSRs.
343
 * @warning This function requires the PMP CPU extension.
344
 *
345
 * @return Returns number of available PMP regions.
346
 **************************************************************************/
347
uint32_t neorv32_cpu_pmp_get_num_regions(void) {
348
 
349 58 zero_gravi
  // PMP implemented at all?
350 64 zero_gravi
  if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_PMP)) == 0) {
351 58 zero_gravi
    return 0;
352
  }
353
 
354 45 zero_gravi
  uint32_t i = 0;
355
 
356 42 zero_gravi
  // try setting R bit in all PMPCFG CSRs
357 45 zero_gravi
  const uint32_t tmp = 0x01010101;
358
  for (i=0; i<16; i++) {
359
    __neorv32_cpu_pmp_cfg_write(i, tmp);
360
  }
361 42 zero_gravi
 
362
  // sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
363
  union {
364
    uint32_t uint32;
365
    uint8_t  uint8[sizeof(uint32_t)/sizeof(uint8_t)];
366
  } cnt;
367
 
368
  cnt.uint32 = 0;
369 45 zero_gravi
  for (i=0; i<16; i++) {
370
    cnt.uint32 += __neorv32_cpu_pmp_cfg_read(i);
371
  }
372 42 zero_gravi
 
373
  // sum up bytes
374
  uint32_t num_regions = 0;
375
  num_regions += (uint32_t)cnt.uint8[0];
376
  num_regions += (uint32_t)cnt.uint8[1];
377
  num_regions += (uint32_t)cnt.uint8[2];
378
  num_regions += (uint32_t)cnt.uint8[3];
379
 
380
  return num_regions;
381
}
382
 
383
 
384
/**********************************************************************//**
385 40 zero_gravi
 * Physical memory protection (PMP): Get minimal region size (granularity).
386
 *
387
 * @warning This function overrides PMPCFG0[0] and PMPADDR0 CSRs.
388
 * @warning This function requires the PMP CPU extension.
389
 *
390 42 zero_gravi
 * @return Returns minimal region size in bytes.
391 40 zero_gravi
 **************************************************************************/
392
uint32_t neorv32_cpu_pmp_get_granularity(void) {
393
 
394
  // check min granulartiy
395
  uint32_t tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
396
  tmp &= 0xffffff00; // disable entry 0
397
  neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
398
  neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffffff);
399
  uint32_t tmp_a = neorv32_cpu_csr_read(CSR_PMPADDR0);
400
 
401
  uint32_t i;
402
 
403
  // find least-significat set bit
404
  for (i=31; i!=0; i--) {
405
    if (((tmp_a >> i) & 1) == 0) {
406
      break;
407
    }
408
  }
409
 
410
  return (uint32_t)(1 << (i+1+2));
411
}
412
 
413
 
414
/**********************************************************************//**
415
 * Physical memory protection (PMP): Configure region.
416
 *
417
 * @note Using NAPOT mode - page base address has to be naturally aligned.
418
 *
419
 * @warning This function requires the PMP CPU extension.
420 42 zero_gravi
 * @warning Only use available PMP regions. Check before using neorv32_cpu_pmp_get_regions(void).
421 40 zero_gravi
 *
422 42 zero_gravi
 * @param[in] index Region number (index, 0..PMP_NUM_REGIONS-1).
423 40 zero_gravi
 * @param[in] base Region base address (has to be naturally aligned!).
424
 * @param[in] size Region size, has to be a power of 2 (min 8 bytes or according to HW's PMP.granularity configuration).
425
 * @param[in] config Region configuration (attributes) byte (for PMPCFGx).
426
 * @return Returns 0 on success, 1 on failure.
427
 **************************************************************************/
428
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config) {
429
 
430
  if (size < 8) {
431
    return 1; // minimal region size is 8 bytes
432
  }
433
 
434
  if ((size & (size - 1)) != 0) {
435
    return 1; // region size is not a power of two
436
  }
437
 
438 45 zero_gravi
  // pmpcfg register index
439
  uint32_t pmpcfg_index = index >> 4; // 4 entries per pmpcfg csr
440
 
441 40 zero_gravi
  // setup configuration
442
  uint32_t tmp;
443
  uint32_t config_int  = ((uint32_t)config) << ((index%4)*8);
444
  uint32_t config_mask = ((uint32_t)0xFF)   << ((index%4)*8);
445
  config_mask = ~config_mask;
446
 
447
  // clear old configuration
448 45 zero_gravi
  __neorv32_cpu_pmp_cfg_write(pmpcfg_index, __neorv32_cpu_pmp_cfg_read(pmpcfg_index) & config_mask);
449 40 zero_gravi
 
450 45 zero_gravi
 
451 40 zero_gravi
  // set base address and region size
452
  uint32_t addr_mask = ~((size - 1) >> 2);
453
  uint32_t size_mask = (size - 1) >> 3;
454
 
455
  tmp = base & addr_mask;
456
  tmp = tmp | size_mask;
457
 
458 42 zero_gravi
  switch(index & 63) {
459
    case 0:  neorv32_cpu_csr_write(CSR_PMPADDR0,  tmp); break;
460
    case 1:  neorv32_cpu_csr_write(CSR_PMPADDR1,  tmp); break;
461
    case 2:  neorv32_cpu_csr_write(CSR_PMPADDR2,  tmp); break;
462
    case 3:  neorv32_cpu_csr_write(CSR_PMPADDR3,  tmp); break;
463
    case 4:  neorv32_cpu_csr_write(CSR_PMPADDR4,  tmp); break;
464
    case 5:  neorv32_cpu_csr_write(CSR_PMPADDR5,  tmp); break;
465
    case 6:  neorv32_cpu_csr_write(CSR_PMPADDR6,  tmp); break;
466
    case 7:  neorv32_cpu_csr_write(CSR_PMPADDR7,  tmp); break;
467
    case 8:  neorv32_cpu_csr_write(CSR_PMPADDR8,  tmp); break;
468
    case 9:  neorv32_cpu_csr_write(CSR_PMPADDR9,  tmp); break;
469
    case 10: neorv32_cpu_csr_write(CSR_PMPADDR10, tmp); break;
470
    case 11: neorv32_cpu_csr_write(CSR_PMPADDR11, tmp); break;
471
    case 12: neorv32_cpu_csr_write(CSR_PMPADDR12, tmp); break;
472
    case 13: neorv32_cpu_csr_write(CSR_PMPADDR13, tmp); break;
473
    case 14: neorv32_cpu_csr_write(CSR_PMPADDR14, tmp); break;
474
    case 15: neorv32_cpu_csr_write(CSR_PMPADDR15, tmp); break;
475
    case 16: neorv32_cpu_csr_write(CSR_PMPADDR16, tmp); break;
476
    case 17: neorv32_cpu_csr_write(CSR_PMPADDR17, tmp); break;
477
    case 18: neorv32_cpu_csr_write(CSR_PMPADDR18, tmp); break;
478
    case 19: neorv32_cpu_csr_write(CSR_PMPADDR19, tmp); break;
479
    case 20: neorv32_cpu_csr_write(CSR_PMPADDR20, tmp); break;
480
    case 21: neorv32_cpu_csr_write(CSR_PMPADDR21, tmp); break;
481
    case 22: neorv32_cpu_csr_write(CSR_PMPADDR22, tmp); break;
482
    case 23: neorv32_cpu_csr_write(CSR_PMPADDR23, tmp); break;
483
    case 24: neorv32_cpu_csr_write(CSR_PMPADDR24, tmp); break;
484
    case 25: neorv32_cpu_csr_write(CSR_PMPADDR25, tmp); break;
485
    case 26: neorv32_cpu_csr_write(CSR_PMPADDR26, tmp); break;
486
    case 27: neorv32_cpu_csr_write(CSR_PMPADDR27, tmp); break;
487
    case 28: neorv32_cpu_csr_write(CSR_PMPADDR28, tmp); break;
488
    case 29: neorv32_cpu_csr_write(CSR_PMPADDR29, tmp); break;
489
    case 30: neorv32_cpu_csr_write(CSR_PMPADDR30, tmp); break;
490
    case 31: neorv32_cpu_csr_write(CSR_PMPADDR31, tmp); break;
491
    case 32: neorv32_cpu_csr_write(CSR_PMPADDR32, tmp); break;
492
    case 33: neorv32_cpu_csr_write(CSR_PMPADDR33, tmp); break;
493
    case 34: neorv32_cpu_csr_write(CSR_PMPADDR34, tmp); break;
494
    case 35: neorv32_cpu_csr_write(CSR_PMPADDR35, tmp); break;
495
    case 36: neorv32_cpu_csr_write(CSR_PMPADDR36, tmp); break;
496
    case 37: neorv32_cpu_csr_write(CSR_PMPADDR37, tmp); break;
497
    case 38: neorv32_cpu_csr_write(CSR_PMPADDR38, tmp); break;
498
    case 39: neorv32_cpu_csr_write(CSR_PMPADDR39, tmp); break;
499
    case 40: neorv32_cpu_csr_write(CSR_PMPADDR40, tmp); break;
500
    case 41: neorv32_cpu_csr_write(CSR_PMPADDR41, tmp); break;
501
    case 42: neorv32_cpu_csr_write(CSR_PMPADDR42, tmp); break;
502
    case 43: neorv32_cpu_csr_write(CSR_PMPADDR43, tmp); break;
503
    case 44: neorv32_cpu_csr_write(CSR_PMPADDR44, tmp); break;
504
    case 45: neorv32_cpu_csr_write(CSR_PMPADDR45, tmp); break;
505
    case 46: neorv32_cpu_csr_write(CSR_PMPADDR46, tmp); break;
506
    case 47: neorv32_cpu_csr_write(CSR_PMPADDR47, tmp); break;
507
    case 48: neorv32_cpu_csr_write(CSR_PMPADDR48, tmp); break;
508
    case 49: neorv32_cpu_csr_write(CSR_PMPADDR49, tmp); break;
509
    case 50: neorv32_cpu_csr_write(CSR_PMPADDR50, tmp); break;
510
    case 51: neorv32_cpu_csr_write(CSR_PMPADDR51, tmp); break;
511
    case 52: neorv32_cpu_csr_write(CSR_PMPADDR52, tmp); break;
512
    case 53: neorv32_cpu_csr_write(CSR_PMPADDR53, tmp); break;
513
    case 54: neorv32_cpu_csr_write(CSR_PMPADDR54, tmp); break;
514
    case 55: neorv32_cpu_csr_write(CSR_PMPADDR55, tmp); break;
515
    case 56: neorv32_cpu_csr_write(CSR_PMPADDR56, tmp); break;
516
    case 57: neorv32_cpu_csr_write(CSR_PMPADDR57, tmp); break;
517
    case 58: neorv32_cpu_csr_write(CSR_PMPADDR58, tmp); break;
518
    case 59: neorv32_cpu_csr_write(CSR_PMPADDR59, tmp); break;
519
    case 60: neorv32_cpu_csr_write(CSR_PMPADDR60, tmp); break;
520
    case 61: neorv32_cpu_csr_write(CSR_PMPADDR61, tmp); break;
521
    case 62: neorv32_cpu_csr_write(CSR_PMPADDR62, tmp); break;
522
    case 63: neorv32_cpu_csr_write(CSR_PMPADDR63, tmp); break;
523 40 zero_gravi
    default: break;
524
  }
525
 
526 42 zero_gravi
  // wait for HW to compute PMP-internal stuff (address masks)
527 40 zero_gravi
  for (tmp=0; tmp<16; tmp++) {
528
    asm volatile ("nop");
529
  }
530
 
531
  // set new configuration
532 45 zero_gravi
  __neorv32_cpu_pmp_cfg_write(pmpcfg_index, __neorv32_cpu_pmp_cfg_read(pmpcfg_index) | config_int);
533
 
534
  return 0;
535
}
536
 
537
 
538
/**********************************************************************//**
539
 * Internal helper function: Read PMP configuration register 0..15
540
 *
541
 * @warning This function requires the PMP CPU extension.
542
 *
543
 * @param[in] index PMP CFG configuration register ID (0..15).
544
 * @return PMP CFG read data.
545
 **************************************************************************/
546
static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index) {
547
 
548
  uint32_t tmp = 0;
549 42 zero_gravi
  switch(index & 15) {
550 45 zero_gravi
    case 0:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);  break;
551
    case 1:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG1);  break;
552
    case 2:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG2);  break;
553
    case 3:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG3);  break;
554
    case 4:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG4);  break;
555
    case 5:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG5);  break;
556
    case 6:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG6);  break;
557
    case 7:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG7);  break;
558
    case 8:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG8);  break;
559
    case 9:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG9);  break;
560
    case 10: tmp = neorv32_cpu_csr_read(CSR_PMPCFG10); break;
561
    case 11: tmp = neorv32_cpu_csr_read(CSR_PMPCFG11); break;
562
    case 12: tmp = neorv32_cpu_csr_read(CSR_PMPCFG12); break;
563
    case 13: tmp = neorv32_cpu_csr_read(CSR_PMPCFG13); break;
564
    case 14: tmp = neorv32_cpu_csr_read(CSR_PMPCFG14); break;
565
    case 15: tmp = neorv32_cpu_csr_read(CSR_PMPCFG15); break;
566 42 zero_gravi
    default: break;
567 40 zero_gravi
  }
568
 
569 45 zero_gravi
  return tmp;
570 40 zero_gravi
}
571 42 zero_gravi
 
572
 
573
/**********************************************************************//**
574 45 zero_gravi
 * Internal helper function: Write PMP configuration register 0..15
575
 *
576
 * @warning This function requires the PMP CPU extension.
577
 *
578
 * @param[in] index PMP CFG configuration register ID (0..15).
579
 * @param[in] data PMP CFG write data.
580
 **************************************************************************/
581
static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data) {
582
 
583
  switch(index & 15) {
584
    case 0:  neorv32_cpu_csr_write(CSR_PMPCFG0,  data); break;
585
    case 1:  neorv32_cpu_csr_write(CSR_PMPCFG1,  data); break;
586
    case 2:  neorv32_cpu_csr_write(CSR_PMPCFG2,  data); break;
587
    case 3:  neorv32_cpu_csr_write(CSR_PMPCFG3,  data); break;
588
    case 4:  neorv32_cpu_csr_write(CSR_PMPCFG4,  data); break;
589
    case 5:  neorv32_cpu_csr_write(CSR_PMPCFG5,  data); break;
590
    case 6:  neorv32_cpu_csr_write(CSR_PMPCFG6,  data); break;
591
    case 7:  neorv32_cpu_csr_write(CSR_PMPCFG7,  data); break;
592
    case 8:  neorv32_cpu_csr_write(CSR_PMPCFG8,  data); break;
593
    case 9:  neorv32_cpu_csr_write(CSR_PMPCFG9,  data); break;
594
    case 10: neorv32_cpu_csr_write(CSR_PMPCFG10, data); break;
595
    case 11: neorv32_cpu_csr_write(CSR_PMPCFG11, data); break;
596
    case 12: neorv32_cpu_csr_write(CSR_PMPCFG12, data); break;
597
    case 13: neorv32_cpu_csr_write(CSR_PMPCFG13, data); break;
598
    case 14: neorv32_cpu_csr_write(CSR_PMPCFG14, data); break;
599
    case 15: neorv32_cpu_csr_write(CSR_PMPCFG15, data); break;
600
    default: break;
601
  }
602
}
603
 
604
 
605
/**********************************************************************//**
606 42 zero_gravi
 * Hardware performance monitors (HPM): Get number of available HPM counters.
607
 *
608
 * @warning This function overrides all available mhpmcounter* CSRs.
609
 *
610 58 zero_gravi
 * @return Returns number of available HPM counters (0..29).
611 42 zero_gravi
 **************************************************************************/
612
uint32_t neorv32_cpu_hpm_get_counters(void) {
613
 
614 58 zero_gravi
  // HPMs implemented at all?
615 64 zero_gravi
  if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_HPM)) == 0) {
616 58 zero_gravi
    return 0;
617
  }
618
 
619 56 zero_gravi
  // inhibit all HPM counters
620
  uint32_t tmp = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
621
  tmp |= 0xfffffff8;
622
  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp);
623
 
624 42 zero_gravi
  // try setting all mhpmcounter* CSRs to 1
625
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER3,  1);
626
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER4,  1);
627
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER5,  1);
628
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER6,  1);
629
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER7,  1);
630
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER8,  1);
631
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER9,  1);
632
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 1);
633
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 1);
634
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 1);
635
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 1);
636
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 1);
637
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER15, 1);
638
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER16, 1);
639
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER17, 1);
640
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER18, 1);
641
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER19, 1);
642
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER20, 1);
643
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER21, 1);
644
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER22, 1);
645
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER23, 1);
646
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER24, 1);
647
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER25, 1);
648
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER26, 1);
649
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER27, 1);
650
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER28, 1);
651
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER29, 1);
652
 
653 56 zero_gravi
  // sum up all written ones (only available HPM counter CSRs will return =! 0)
654 42 zero_gravi
  uint32_t num_hpm_cnts = 0;
655
 
656
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER3);
657
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER4);
658
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER5);
659
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER6);
660
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER7);
661
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER8);
662
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER9);
663
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER10);
664
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER11);
665
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER12);
666
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER13);
667
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER14);
668
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER15);
669
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER16);
670
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER17);
671
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER18);
672
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER19);
673
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER20);
674
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER21);
675
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER22);
676
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER23);
677
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER24);
678
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER25);
679
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER26);
680
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER27);
681
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER28);
682
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER29);
683
 
684
  return num_hpm_cnts;
685
}
686 55 zero_gravi
 
687
 
688
/**********************************************************************//**
689 56 zero_gravi
 * Hardware performance monitors (HPM): Get total counter width
690
 *
691
 * @warning This function overrides mhpmcounter3[h] CSRs.
692
 *
693 58 zero_gravi
 * @return Size of HPM counter bits (1-64, 0 if not implemented at all).
694 56 zero_gravi
 **************************************************************************/
695
uint32_t neorv32_cpu_hpm_get_size(void) {
696
 
697 58 zero_gravi
  // HPMs implemented at all?
698 64 zero_gravi
  if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_HPM)) == 0) {
699 58 zero_gravi
    return 0;
700
  }
701
 
702 56 zero_gravi
  // inhibt auto-update
703 61 zero_gravi
  asm volatile ("csrwi %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_HPM3));
704 56 zero_gravi
 
705
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER3,  0xffffffff);
706
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER3H, 0xffffffff);
707
 
708
  uint32_t tmp, size, i;
709
 
710
  if (neorv32_cpu_csr_read(CSR_MHPMCOUNTER3H) == 0) {
711
    size = 0;
712
    tmp = neorv32_cpu_csr_read(CSR_MHPMCOUNTER3);
713
  }
714
  else {
715
    size = 32;
716
    tmp = neorv32_cpu_csr_read(CSR_MHPMCOUNTER3H);
717
  }
718
 
719
  for (i=0; i<32; i++) {
720
    if (tmp & (1<<i)) {
721
      size++;
722
    }
723
  }
724
 
725
  return size;
726
}
727
 

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