OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_cpu.c] - Blame information for rev 72

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 zero_gravi 
// #################################################################################################
2 
// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >>                                   #
3 
// # ********************************************************************************************* #
4 
// # BSD 3-Clause License                                                                          #
5 
// #                                                                                               #
6 71 zero_gravi 
// # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
// #                                                                                               #
8 
// # Redistribution and use in source and binary forms, with or without modification, are          #
9 
// # permitted provided that the following conditions are met:                                     #
10 
// #                                                                                               #
11 
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12 
// #    conditions and the following disclaimer.                                                   #
13 
// #                                                                                               #
14 
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15 
// #    conditions and the following disclaimer in the documentation and/or other materials        #
16 
// #    provided with the distribution.                                                            #
17 
// #                                                                                               #
18 
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19 
// #    endorse or promote products derived from this software without specific prior written      #
20 
// #    permission.                                                                                #
21 
// #                                                                                               #
22 
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23 
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24 
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25 
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26 
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27 
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28 
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29 
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30 
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
31 
// # ********************************************************************************************* #
32 
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33 
// #################################################################################################
34 
 
35 
 
36 
/**********************************************************************//**
37 
 * @file neorv32_cpu.c
38 
 * @author Stephan Nolting
39 
 * @brief CPU Core Functions HW driver source file.
40 
 **************************************************************************/
41 
 
42 
#include "neorv32.h"
43 
#include "neorv32_cpu.h"
44 
 
45 
 
46 53 zero_gravi 
/**********************************************************************//**
47 
 * Unavailable extensions warning.
48 
 **************************************************************************/
49 
#if defined __riscv_d || (__riscv_flen == 64)
50 
  #error Double-precision floating-point extension <D/Zdinx> is NOT supported!
51 
#endif
52 
 
53 
#if (__riscv_xlen > 32)
54 
  #error Only 32-bit <rv32> is supported!
55 
#endif
56 
 
57 
#ifdef __riscv_fdiv
58 
  #warning Floating-point division instruction <FDIV> is NOT supported yet!
59 
#endif
60 
 
61 
#ifdef __riscv_fsqrt
62 
  #warning Floating-point square root instruction <FSQRT> is NOT supported yet!
63 
#endif
64 
 
65 
 
66 2 zero_gravi 
/**********************************************************************//**
67 45 zero_gravi 
 * >Private< helper functions.
68 
 **************************************************************************/
69 47 zero_gravi 
static int __neorv32_cpu_irq_id_check(uint8_t irq_sel);
70 45 zero_gravi 
static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index);
71 
static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data);
72 
 
73 
 
74 
/**********************************************************************//**
75 47 zero_gravi 
 * Private function: Check IRQ id.
76 
 *
77 
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
78 
 * @return 0 if success, 1 if error (invalid irq_sel).
79 
 **************************************************************************/
80 
static int __neorv32_cpu_irq_id_check(uint8_t irq_sel) {
81 
 
82 48 zero_gravi 
  if ((irq_sel == CSR_MIE_MSIE) || (irq_sel == CSR_MIE_MTIE) || (irq_sel == CSR_MIE_MEIE) ||
83 
     ((irq_sel >= CSR_MIE_FIRQ0E) && (irq_sel <= CSR_MIE_FIRQ15E))) {
84 47 zero_gravi 
    return 0;
85 
  }
86 
  else {
87 
    return 1;
88 
  }
89 
}
90 
 
91 
 
92 
/**********************************************************************//**
93 2 zero_gravi 
 * Enable specific CPU interrupt.
94 
 *
95 
 * @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
96 
 *
97 42 zero_gravi 
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
98 12 zero_gravi 
 * @return 0 if success, 1 if error (invalid irq_sel).
99 2 zero_gravi 
 **************************************************************************/
100 
int neorv32_cpu_irq_enable(uint8_t irq_sel) {
101 
 
102 47 zero_gravi 
  // check IRQ id
103 
  if (__neorv32_cpu_irq_id_check(irq_sel)) {
104 2 zero_gravi 
    return 1;
105 
  }
106 
 
107 
  register uint32_t mask = (uint32_t)(1 << irq_sel);
108 
  asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
109 
  return 0;
110 
}
111 
 
112 
 
113 
/**********************************************************************//**
114 
 * Disable specific CPU interrupt.
115 
 *
116 42 zero_gravi 
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
117 12 zero_gravi 
 * @return 0 if success, 1 if error (invalid irq_sel).
118 2 zero_gravi 
 **************************************************************************/
119 
int neorv32_cpu_irq_disable(uint8_t irq_sel) {
120 
 
121 47 zero_gravi 
  // check IRQ id
122 
  if (__neorv32_cpu_irq_id_check(irq_sel)) {
123 2 zero_gravi 
    return 1;
124 
  }
125 
 
126 
  register uint32_t mask = (uint32_t)(1 << irq_sel);
127 
  asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
128 
  return 0;
129 
}
130 
 
131 
 
132 
/**********************************************************************//**
133 12 zero_gravi 
 * Get cycle count from cycle[h].
134 
 *
135 
 * @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR.
136 
 *
137 
 * @return Current cycle counter (64 bit).
138 
 **************************************************************************/
139 
uint64_t neorv32_cpu_get_cycle(void) {
140 
 
141 
  union {
142 
    uint64_t uint64;
143 71 zero_gravi 
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
144 12 zero_gravi 
  } cycles;
145 
 
146 64 zero_gravi 
  register uint32_t tmp1, tmp2, tmp3;
147 12 zero_gravi 
  while(1) {
148 
    tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH);
149 
    tmp2 = neorv32_cpu_csr_read(CSR_CYCLE);
150 
    tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH);
151 
    if (tmp1 == tmp3) {
152 
      break;
153 
    }
154 
  }
155 
 
156 
  cycles.uint32[0] = tmp2;
157 
  cycles.uint32[1] = tmp3;
158 
 
159 
  return cycles.uint64;
160 
}
161 
 
162 
 
163 
/**********************************************************************//**
164 
 * Set mcycle[h] counter.
165 
 *
166 
 * @param[in] value New value for mcycle[h] CSR (64-bit).
167 
 **************************************************************************/
168 
void neorv32_cpu_set_mcycle(uint64_t value) {
169 
 
170 
  union {
171 
    uint64_t uint64;
172 71 zero_gravi 
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
173 12 zero_gravi 
  } cycles;
174 
 
175 
  cycles.uint64 = value;
176 
 
177 
  neorv32_cpu_csr_write(CSR_MCYCLE,  0);
178 
  neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]);
179 
  neorv32_cpu_csr_write(CSR_MCYCLE,  cycles.uint32[0]);
180 
}
181 
 
182 
 
183 
/**********************************************************************//**
184 
 * Get retired instructions counter from instret[h].
185 
 *
186 
 * @note The instret[h] CSR is shadowed copy of the instret[h] CSR.
187 
 *
188 
 * @return Current instructions counter (64 bit).
189 
 **************************************************************************/
190 
uint64_t neorv32_cpu_get_instret(void) {
191 
 
192 
  union {
193 
    uint64_t uint64;
194 71 zero_gravi 
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
195 12 zero_gravi 
  } cycles;
196 
 
197 64 zero_gravi 
  register uint32_t tmp1, tmp2, tmp3;
198 12 zero_gravi 
  while(1) {
199 
    tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH);
200 
    tmp2 = neorv32_cpu_csr_read(CSR_INSTRET);
201 
    tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH);
202 
    if (tmp1 == tmp3) {
203 
      break;
204 
    }
205 
  }
206 
 
207 
  cycles.uint32[0] = tmp2;
208 
  cycles.uint32[1] = tmp3;
209 
 
210 
  return cycles.uint64;
211 
}
212 
 
213 
 
214 
/**********************************************************************//**
215 
 * Set retired instructions counter minstret[h].
216 
 *
217 
 * @param[in] value New value for mcycle[h] CSR (64-bit).
218 
 **************************************************************************/
219 
void neorv32_cpu_set_minstret(uint64_t value) {
220 
 
221 
  union {
222 
    uint64_t uint64;
223 71 zero_gravi 
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
224 12 zero_gravi 
  } cycles;
225 
 
226 
  cycles.uint64 = value;
227 
 
228 
  neorv32_cpu_csr_write(CSR_MINSTRET,  0);
229 
  neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]);
230 
  neorv32_cpu_csr_write(CSR_MINSTRET,  cycles.uint32[0]);
231 
}
232 
 
233 
 
234 
/**********************************************************************//**
235 
 * Get current system time from time[h] CSR.
236 
 *
237 
 * @note This function requires the MTIME system timer to be implemented.
238 
 *
239 
 * @return Current system time (64 bit).
240 
 **************************************************************************/
241 
uint64_t neorv32_cpu_get_systime(void) {
242 
 
243 
  union {
244 
    uint64_t uint64;
245 71 zero_gravi 
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
246 12 zero_gravi 
  } cycles;
247 
 
248 64 zero_gravi 
  register uint32_t tmp1, tmp2, tmp3;
249 12 zero_gravi 
  while(1) {
250 
    tmp1 = neorv32_cpu_csr_read(CSR_TIMEH);
251 
    tmp2 = neorv32_cpu_csr_read(CSR_TIME);
252 
    tmp3 = neorv32_cpu_csr_read(CSR_TIMEH);
253 
    if (tmp1 == tmp3) {
254 
      break;
255 
    }
256 
  }
257 
 
258 
  cycles.uint32[0] = tmp2;
259 
  cycles.uint32[1] = tmp3;
260 
 
261 
  return cycles.uint64;
262 
}
263 
 
264 
 
265 
/**********************************************************************//**
266 64 zero_gravi 
 * Delay function using busy wait.
267 2 zero_gravi 
 *
268 72 zero_gravi 
 * @note This function uses MTIME as time base. A simple ASM loop
269 
 * is used as fall back if system timer is not implemented.
270 39 zero_gravi 
 *
271 64 zero_gravi 
 * @warning Delay time might be less precise if M extensions is not available
272 
 * (especially if MTIME unit is not available).
273 
 *
274 
 * @param[in] time_ms Time in ms to wait (unsigned 32-bit).
275 2 zero_gravi 
 **************************************************************************/
276 64 zero_gravi 
void neorv32_cpu_delay_ms(uint32_t time_ms) {
277 2 zero_gravi 
 
278 64 zero_gravi 
  uint32_t clock = NEORV32_SYSINFO.CLK; // clock ticks per second
279 
  clock = clock / 1000; // clock ticks per ms
280 2 zero_gravi 
 
281 72 zero_gravi 
  register uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);
282 
  register uint64_t tmp = 0;
283 64 zero_gravi 
 
284 72 zero_gravi 
  // MTIME available?
285 
  if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_MTIME)) {
286 64 zero_gravi 
 
287 
    // use MTIME machine timer
288 72 zero_gravi 
    tmp = neorv32_mtime_get_time() + wait_cycles;
289 64 zero_gravi 
    while(1) {
290 72 zero_gravi 
      if (neorv32_mtime_get_time() >= tmp) {
291 64 zero_gravi 
        break;
292 
      }
293 
    }
294 56 zero_gravi 
  }
295 64 zero_gravi 
  else {
296 
    // use ASM loop
297 
    // warning! not really precise (especially if M extensions is not available)!
298 56 zero_gravi 
 
299 64 zero_gravi 
    const uint32_t loop_cycles_c = 16; // clock cycles per iteration of the ASM loop
300 72 zero_gravi 
    register uint32_t iterations = (uint32_t)(wait_cycles / loop_cycles_c); // M (div) extension would be nice here!
301 39 zero_gravi 
 
302 64 zero_gravi 
    asm volatile (" .balign 4                                        \n" // make sure this is 32-bit aligned
303 
                  " __neorv32_cpu_delay_ms_start:                    \n"
304 
                  " beq  %[cnt_r], zero, __neorv32_cpu_delay_ms_end  \n" // 3 cycles (not taken)
305 
                  " beq  %[cnt_r], zero, __neorv32_cpu_delay_ms_end  \n" // 3 cycles (never taken)
306 
                  " addi %[cnt_w], %[cnt_r], -1                      \n" // 2 cycles
307 
                  " nop                                              \n" // 2 cycles
308 
                  " j    __neorv32_cpu_delay_ms_start                \n" // 6 cycles
309 
                  " __neorv32_cpu_delay_ms_end: "
310 
                  : [cnt_w] "=r" (iterations) : [cnt_r] "r" (iterations));
311 
  }
312 2 zero_gravi 
}
313 
 
314 15 zero_gravi 
 
315 
/**********************************************************************//**
316 
 * Switch from privilege mode MACHINE to privilege mode USER.
317 
 *
318 39 zero_gravi 
 * @warning This function requires the U extension to be implemented.
319 15 zero_gravi 
 **************************************************************************/
320 
void __attribute__((naked)) neorv32_cpu_goto_user_mode(void) {
321 
 
322 35 zero_gravi 
  // make sure to use NO registers in here! -> naked
323 15 zero_gravi 
 
324 56 zero_gravi 
  asm volatile ("csrw mepc, ra           \n" // move return address to mepc so we can return using "mret". also, we can now use ra as general purpose register in here
325 
                "li ra, %[input_imm]     \n" // bit mask to clear the two MPP bits
326 
                "csrrc zero, mstatus, ra \n" // clear MPP bits -> MPP=u-mode
327 
                "mret                    \n" // return and switch to user mode
328 42 zero_gravi 
                :  : [input_imm] "i" ((1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L)));
329 15 zero_gravi 
}
330 39 zero_gravi 
 
331 
 
332 
/**********************************************************************//**
333 42 zero_gravi 
 * Physical memory protection (PMP): Get number of available regions.
334 
 *
335 
 * @warning This function overrides all available PMPCFG* CSRs.
336 
 * @warning This function requires the PMP CPU extension.
337 
 *
338 
 * @return Returns number of available PMP regions.
339 
 **************************************************************************/
340 
uint32_t neorv32_cpu_pmp_get_num_regions(void) {
341 
 
342 58 zero_gravi 
  // PMP implemented at all?
343 72 zero_gravi 
  if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_PMP)) == 0) {
344 58 zero_gravi 
    return 0;
345 
  }
346 
 
347 45 zero_gravi 
  uint32_t i = 0;
348 
 
349 42 zero_gravi 
  // try setting R bit in all PMPCFG CSRs
350 65 zero_gravi 
  const uint32_t mask = 0x01010101;
351 45 zero_gravi 
  for (i=0; i<16; i++) {
352 65 zero_gravi 
    __neorv32_cpu_pmp_cfg_write(i, mask);
353 45 zero_gravi 
  }
354 42 zero_gravi 
 
355 
  // sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
356 
  union {
357 
    uint32_t uint32;
358 
    uint8_t  uint8[sizeof(uint32_t)/sizeof(uint8_t)];
359 
  } cnt;
360 
 
361 
  cnt.uint32 = 0;
362 45 zero_gravi 
  for (i=0; i<16; i++) {
363 65 zero_gravi 
    cnt.uint32 += __neorv32_cpu_pmp_cfg_read(i) & mask;
364 45 zero_gravi 
  }
365 42 zero_gravi 
 
366 
  // sum up bytes
367 
  uint32_t num_regions = 0;
368 
  num_regions += (uint32_t)cnt.uint8[0];
369 
  num_regions += (uint32_t)cnt.uint8[1];
370 
  num_regions += (uint32_t)cnt.uint8[2];
371 
  num_regions += (uint32_t)cnt.uint8[3];
372 
 
373 
  return num_regions;
374 
}
375 
 
376 
 
377 
/**********************************************************************//**
378 40 zero_gravi 
 * Physical memory protection (PMP): Get minimal region size (granularity).
379 
 *
380 
 * @warning This function overrides PMPCFG0[0] and PMPADDR0 CSRs.
381 
 * @warning This function requires the PMP CPU extension.
382 
 *
383 42 zero_gravi 
 * @return Returns minimal region size in bytes.
384 40 zero_gravi 
 **************************************************************************/
385 
uint32_t neorv32_cpu_pmp_get_granularity(void) {
386 
 
387 
  // check min granulartiy
388 
  uint32_t tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
389 
  tmp &= 0xffffff00; // disable entry 0
390 
  neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
391 
  neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffffff);
392 
  uint32_t tmp_a = neorv32_cpu_csr_read(CSR_PMPADDR0);
393 
 
394 
  uint32_t i;
395 
 
396 
  // find least-significat set bit
397 
  for (i=31; i!=0; i--) {
398 
    if (((tmp_a >> i) & 1) == 0) {
399 
      break;
400 
    }
401 
  }
402 
 
403 
  return (uint32_t)(1 << (i+1+2));
404 
}
405 
 
406 
 
407 
/**********************************************************************//**
408 
 * Physical memory protection (PMP): Configure region.
409 
 *
410 
 * @note Using NAPOT mode - page base address has to be naturally aligned.
411 
 *
412 
 * @warning This function requires the PMP CPU extension.
413 42 zero_gravi 
 * @warning Only use available PMP regions. Check before using neorv32_cpu_pmp_get_regions(void).
414 40 zero_gravi 
 *
415 42 zero_gravi 
 * @param[in] index Region number (index, 0..PMP_NUM_REGIONS-1).
416 40 zero_gravi 
 * @param[in] base Region base address (has to be naturally aligned!).
417 
 * @param[in] size Region size, has to be a power of 2 (min 8 bytes or according to HW's PMP.granularity configuration).
418 
 * @param[in] config Region configuration (attributes) byte (for PMPCFGx).
419 
 * @return Returns 0 on success, 1 on failure.
420 
 **************************************************************************/
421 
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config) {
422 
 
423 
  if (size < 8) {
424 
    return 1; // minimal region size is 8 bytes
425 
  }
426 
 
427 
  if ((size & (size - 1)) != 0) {
428 
    return 1; // region size is not a power of two
429 
  }
430 
 
431 45 zero_gravi 
  // pmpcfg register index
432 
  uint32_t pmpcfg_index = index >> 4; // 4 entries per pmpcfg csr
433 
 
434 40 zero_gravi 
  // setup configuration
435 
  uint32_t tmp;
436 
  uint32_t config_int  = ((uint32_t)config) << ((index%4)*8);
437 
  uint32_t config_mask = ((uint32_t)0xFF)   << ((index%4)*8);
438 
  config_mask = ~config_mask;
439 
 
440 
  // clear old configuration
441 45 zero_gravi 
  __neorv32_cpu_pmp_cfg_write(pmpcfg_index, __neorv32_cpu_pmp_cfg_read(pmpcfg_index) & config_mask);
442 40 zero_gravi 
 
443 45 zero_gravi 
 
444 40 zero_gravi 
  // set base address and region size
445 
  uint32_t addr_mask = ~((size - 1) >> 2);
446 
  uint32_t size_mask = (size - 1) >> 3;
447 
 
448 
  tmp = base & addr_mask;
449 
  tmp = tmp | size_mask;
450 
 
451 42 zero_gravi 
  switch(index & 63) {
452 
    case 0:  neorv32_cpu_csr_write(CSR_PMPADDR0,  tmp); break;
453 
    case 1:  neorv32_cpu_csr_write(CSR_PMPADDR1,  tmp); break;
454 
    case 2:  neorv32_cpu_csr_write(CSR_PMPADDR2,  tmp); break;
455 
    case 3:  neorv32_cpu_csr_write(CSR_PMPADDR3,  tmp); break;
456 
    case 4:  neorv32_cpu_csr_write(CSR_PMPADDR4,  tmp); break;
457 
    case 5:  neorv32_cpu_csr_write(CSR_PMPADDR5,  tmp); break;
458 
    case 6:  neorv32_cpu_csr_write(CSR_PMPADDR6,  tmp); break;
459 
    case 7:  neorv32_cpu_csr_write(CSR_PMPADDR7,  tmp); break;
460 
    case 8:  neorv32_cpu_csr_write(CSR_PMPADDR8,  tmp); break;
461 
    case 9:  neorv32_cpu_csr_write(CSR_PMPADDR9,  tmp); break;
462 
    case 10: neorv32_cpu_csr_write(CSR_PMPADDR10, tmp); break;
463 
    case 11: neorv32_cpu_csr_write(CSR_PMPADDR11, tmp); break;
464 
    case 12: neorv32_cpu_csr_write(CSR_PMPADDR12, tmp); break;
465 
    case 13: neorv32_cpu_csr_write(CSR_PMPADDR13, tmp); break;
466 
    case 14: neorv32_cpu_csr_write(CSR_PMPADDR14, tmp); break;
467 
    case 15: neorv32_cpu_csr_write(CSR_PMPADDR15, tmp); break;
468 
    case 16: neorv32_cpu_csr_write(CSR_PMPADDR16, tmp); break;
469 
    case 17: neorv32_cpu_csr_write(CSR_PMPADDR17, tmp); break;
470 
    case 18: neorv32_cpu_csr_write(CSR_PMPADDR18, tmp); break;
471 
    case 19: neorv32_cpu_csr_write(CSR_PMPADDR19, tmp); break;
472 
    case 20: neorv32_cpu_csr_write(CSR_PMPADDR20, tmp); break;
473 
    case 21: neorv32_cpu_csr_write(CSR_PMPADDR21, tmp); break;
474 
    case 22: neorv32_cpu_csr_write(CSR_PMPADDR22, tmp); break;
475 
    case 23: neorv32_cpu_csr_write(CSR_PMPADDR23, tmp); break;
476 
    case 24: neorv32_cpu_csr_write(CSR_PMPADDR24, tmp); break;
477 
    case 25: neorv32_cpu_csr_write(CSR_PMPADDR25, tmp); break;
478 
    case 26: neorv32_cpu_csr_write(CSR_PMPADDR26, tmp); break;
479 
    case 27: neorv32_cpu_csr_write(CSR_PMPADDR27, tmp); break;
480 
    case 28: neorv32_cpu_csr_write(CSR_PMPADDR28, tmp); break;
481 
    case 29: neorv32_cpu_csr_write(CSR_PMPADDR29, tmp); break;
482 
    case 30: neorv32_cpu_csr_write(CSR_PMPADDR30, tmp); break;
483 
    case 31: neorv32_cpu_csr_write(CSR_PMPADDR31, tmp); break;
484 
    case 32: neorv32_cpu_csr_write(CSR_PMPADDR32, tmp); break;
485 
    case 33: neorv32_cpu_csr_write(CSR_PMPADDR33, tmp); break;
486 
    case 34: neorv32_cpu_csr_write(CSR_PMPADDR34, tmp); break;
487 
    case 35: neorv32_cpu_csr_write(CSR_PMPADDR35, tmp); break;
488 
    case 36: neorv32_cpu_csr_write(CSR_PMPADDR36, tmp); break;
489 
    case 37: neorv32_cpu_csr_write(CSR_PMPADDR37, tmp); break;
490 
    case 38: neorv32_cpu_csr_write(CSR_PMPADDR38, tmp); break;
491 
    case 39: neorv32_cpu_csr_write(CSR_PMPADDR39, tmp); break;
492 
    case 40: neorv32_cpu_csr_write(CSR_PMPADDR40, tmp); break;
493 
    case 41: neorv32_cpu_csr_write(CSR_PMPADDR41, tmp); break;
494 
    case 42: neorv32_cpu_csr_write(CSR_PMPADDR42, tmp); break;
495 
    case 43: neorv32_cpu_csr_write(CSR_PMPADDR43, tmp); break;
496 
    case 44: neorv32_cpu_csr_write(CSR_PMPADDR44, tmp); break;
497 
    case 45: neorv32_cpu_csr_write(CSR_PMPADDR45, tmp); break;
498 
    case 46: neorv32_cpu_csr_write(CSR_PMPADDR46, tmp); break;
499 
    case 47: neorv32_cpu_csr_write(CSR_PMPADDR47, tmp); break;
500 
    case 48: neorv32_cpu_csr_write(CSR_PMPADDR48, tmp); break;
501 
    case 49: neorv32_cpu_csr_write(CSR_PMPADDR49, tmp); break;
502 
    case 50: neorv32_cpu_csr_write(CSR_PMPADDR50, tmp); break;
503 
    case 51: neorv32_cpu_csr_write(CSR_PMPADDR51, tmp); break;
504 
    case 52: neorv32_cpu_csr_write(CSR_PMPADDR52, tmp); break;
505 
    case 53: neorv32_cpu_csr_write(CSR_PMPADDR53, tmp); break;
506 
    case 54: neorv32_cpu_csr_write(CSR_PMPADDR54, tmp); break;
507 
    case 55: neorv32_cpu_csr_write(CSR_PMPADDR55, tmp); break;
508 
    case 56: neorv32_cpu_csr_write(CSR_PMPADDR56, tmp); break;
509 
    case 57: neorv32_cpu_csr_write(CSR_PMPADDR57, tmp); break;
510 
    case 58: neorv32_cpu_csr_write(CSR_PMPADDR58, tmp); break;
511 
    case 59: neorv32_cpu_csr_write(CSR_PMPADDR59, tmp); break;
512 
    case 60: neorv32_cpu_csr_write(CSR_PMPADDR60, tmp); break;
513 
    case 61: neorv32_cpu_csr_write(CSR_PMPADDR61, tmp); break;
514 
    case 62: neorv32_cpu_csr_write(CSR_PMPADDR62, tmp); break;
515 
    case 63: neorv32_cpu_csr_write(CSR_PMPADDR63, tmp); break;
516 40 zero_gravi 
    default: break;
517 
  }
518 
 
519 42 zero_gravi 
  // wait for HW to compute PMP-internal stuff (address masks)
520 40 zero_gravi 
  for (tmp=0; tmp<16; tmp++) {
521 
    asm volatile ("nop");
522 
  }
523 
 
524 
  // set new configuration
525 45 zero_gravi 
  __neorv32_cpu_pmp_cfg_write(pmpcfg_index, __neorv32_cpu_pmp_cfg_read(pmpcfg_index) | config_int);
526 
 
527 
  return 0;
528 
}
529 
 
530 
 
531 
/**********************************************************************//**
532 
 * Internal helper function: Read PMP configuration register 0..15
533 
 *
534 
 * @warning This function requires the PMP CPU extension.
535 
 *
536 
 * @param[in] index PMP CFG configuration register ID (0..15).
537 
 * @return PMP CFG read data.
538 
 **************************************************************************/
539 
static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index) {
540 
 
541 
  uint32_t tmp = 0;
542 42 zero_gravi 
  switch(index & 15) {
543 45 zero_gravi 
    case 0:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);  break;
544 
    case 1:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG1);  break;
545 
    case 2:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG2);  break;
546 
    case 3:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG3);  break;
547 
    case 4:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG4);  break;
548 
    case 5:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG5);  break;
549 
    case 6:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG6);  break;
550 
    case 7:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG7);  break;
551 
    case 8:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG8);  break;
552 
    case 9:  tmp = neorv32_cpu_csr_read(CSR_PMPCFG9);  break;
553 
    case 10: tmp = neorv32_cpu_csr_read(CSR_PMPCFG10); break;
554 
    case 11: tmp = neorv32_cpu_csr_read(CSR_PMPCFG11); break;
555 
    case 12: tmp = neorv32_cpu_csr_read(CSR_PMPCFG12); break;
556 
    case 13: tmp = neorv32_cpu_csr_read(CSR_PMPCFG13); break;
557 
    case 14: tmp = neorv32_cpu_csr_read(CSR_PMPCFG14); break;
558 
    case 15: tmp = neorv32_cpu_csr_read(CSR_PMPCFG15); break;
559 42 zero_gravi 
    default: break;
560 40 zero_gravi 
  }
561 
 
562 45 zero_gravi 
  return tmp;
563 40 zero_gravi 
}
564 42 zero_gravi 
 
565 
 
566 
/**********************************************************************//**
567 45 zero_gravi 
 * Internal helper function: Write PMP configuration register 0..15
568 
 *
569 
 * @warning This function requires the PMP CPU extension.
570 
 *
571 
 * @param[in] index PMP CFG configuration register ID (0..15).
572 
 * @param[in] data PMP CFG write data.
573 
 **************************************************************************/
574 
static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data) {
575 
 
576 
  switch(index & 15) {
577 
    case 0:  neorv32_cpu_csr_write(CSR_PMPCFG0,  data); break;
578 
    case 1:  neorv32_cpu_csr_write(CSR_PMPCFG1,  data); break;
579 
    case 2:  neorv32_cpu_csr_write(CSR_PMPCFG2,  data); break;
580 
    case 3:  neorv32_cpu_csr_write(CSR_PMPCFG3,  data); break;
581 
    case 4:  neorv32_cpu_csr_write(CSR_PMPCFG4,  data); break;
582 
    case 5:  neorv32_cpu_csr_write(CSR_PMPCFG5,  data); break;
583 
    case 6:  neorv32_cpu_csr_write(CSR_PMPCFG6,  data); break;
584 
    case 7:  neorv32_cpu_csr_write(CSR_PMPCFG7,  data); break;
585 
    case 8:  neorv32_cpu_csr_write(CSR_PMPCFG8,  data); break;
586 
    case 9:  neorv32_cpu_csr_write(CSR_PMPCFG9,  data); break;
587 
    case 10: neorv32_cpu_csr_write(CSR_PMPCFG10, data); break;
588 
    case 11: neorv32_cpu_csr_write(CSR_PMPCFG11, data); break;
589 
    case 12: neorv32_cpu_csr_write(CSR_PMPCFG12, data); break;
590 
    case 13: neorv32_cpu_csr_write(CSR_PMPCFG13, data); break;
591 
    case 14: neorv32_cpu_csr_write(CSR_PMPCFG14, data); break;
592 
    case 15: neorv32_cpu_csr_write(CSR_PMPCFG15, data); break;
593 
    default: break;
594 
  }
595 
}
596 
 
597 
 
598 
/**********************************************************************//**
599 42 zero_gravi 
 * Hardware performance monitors (HPM): Get number of available HPM counters.
600 
 *
601 
 * @warning This function overrides all available mhpmcounter* CSRs.
602 
 *
603 58 zero_gravi 
 * @return Returns number of available HPM counters (0..29).
604 42 zero_gravi 
 **************************************************************************/
605 
uint32_t neorv32_cpu_hpm_get_counters(void) {
606 
 
607 58 zero_gravi 
  // HPMs implemented at all?
608 72 zero_gravi 
  if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZIHPM)) == 0) {
609 58 zero_gravi 
    return 0;
610 
  }
611 
 
612 56 zero_gravi 
  // inhibit all HPM counters
613 
  uint32_t tmp = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
614 
  tmp |= 0xfffffff8;
615 
  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp);
616 
 
617 42 zero_gravi 
  // try setting all mhpmcounter* CSRs to 1
618 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER3,  1);
619 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER4,  1);
620 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER5,  1);
621 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER6,  1);
622 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER7,  1);
623 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER8,  1);
624 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER9,  1);
625 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 1);
626 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 1);
627 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 1);
628 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 1);
629 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 1);
630 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER15, 1);
631 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER16, 1);
632 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER17, 1);
633 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER18, 1);
634 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER19, 1);
635 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER20, 1);
636 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER21, 1);
637 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER22, 1);
638 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER23, 1);
639 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER24, 1);
640 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER25, 1);
641 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER26, 1);
642 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER27, 1);
643 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER28, 1);
644 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER29, 1);
645 
 
646 56 zero_gravi 
  // sum up all written ones (only available HPM counter CSRs will return =! 0)
647 42 zero_gravi 
  uint32_t num_hpm_cnts = 0;
648 
 
649 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER3);
650 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER4);
651 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER5);
652 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER6);
653 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER7);
654 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER8);
655 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER9);
656 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER10);
657 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER11);
658 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER12);
659 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER13);
660 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER14);
661 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER15);
662 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER16);
663 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER17);
664 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER18);
665 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER19);
666 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER20);
667 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER21);
668 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER22);
669 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER23);
670 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER24);
671 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER25);
672 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER26);
673 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER27);
674 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER28);
675 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER29);
676 
 
677 
  return num_hpm_cnts;
678 
}
679 55 zero_gravi 
 
680 
 
681 
/**********************************************************************//**
682 56 zero_gravi 
 * Hardware performance monitors (HPM): Get total counter width
683 
 *
684 
 * @warning This function overrides mhpmcounter3[h] CSRs.
685 
 *
686 58 zero_gravi 
 * @return Size of HPM counter bits (1-64, 0 if not implemented at all).
687 56 zero_gravi 
 **************************************************************************/
688 
uint32_t neorv32_cpu_hpm_get_size(void) {
689 
 
690 58 zero_gravi 
  // HPMs implemented at all?
691 72 zero_gravi 
  if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZIHPM)) == 0) {
692 58 zero_gravi 
    return 0;
693 
  }
694 
 
695 56 zero_gravi 
  // inhibt auto-update
696 61 zero_gravi 
  asm volatile ("csrwi %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_HPM3));
697 56 zero_gravi 
 
698 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER3,  0xffffffff);
699 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER3H, 0xffffffff);
700 
 
701 
  uint32_t tmp, size, i;
702 
 
703 
  if (neorv32_cpu_csr_read(CSR_MHPMCOUNTER3H) == 0) {
704 
    size = 0;
705 
    tmp = neorv32_cpu_csr_read(CSR_MHPMCOUNTER3);
706 
  }
707 
  else {
708 
    size = 32;
709 
    tmp = neorv32_cpu_csr_read(CSR_MHPMCOUNTER3H);
710 
  }
711 
 
712 
  for (i=0; i<32; i++) {
713 
    if (tmp & (1<<i)) {
714 
      size++;
715 
    }
716 
  }
717 
 
718 
  return size;
719 
}
720 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.