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// #################################################################################################
// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >>                                   #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
// #                                                                                               #
// # Redistribution and use in source and binary forms, with or without modification, are          #
// # permitted provided that the following conditions are met:                                     #
// #                                                                                               #
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
// #    conditions and the following disclaimer.                                                   #
// #                                                                                               #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
// #    conditions and the following disclaimer in the documentation and/or other materials        #
// #    provided with the distribution.                                                            #
// #                                                                                               #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
// #    endorse or promote products derived from this software without specific prior written      #
// #    permission.                                                                                #
// #                                                                                               #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
 * @file neorv32_cpu.c
 * @brief CPU Core Functions HW driver source file.
 **************************************************************************/
 
#include "neorv32.h"
#include "neorv32_cpu.h"
 
 
/**********************************************************************//**
 * Unavailable extensions warning.
 **************************************************************************/
#if defined __riscv_d || (__riscv_flen == 64)
  #error Double-precision floating-point extension <D/Zdinx> is NOT supported!
#endif
 
#if (__riscv_xlen > 32)
  #error Only 32-bit <rv32> is supported!
#endif
 
#ifdef __riscv_fdiv
  #warning Floating-point division instruction <FDIV> is NOT supported yet!
#endif
 
#ifdef __riscv_fsqrt
  #warning Floating-point square root instruction <FSQRT> is NOT supported yet!
#endif
 
 
/**********************************************************************//**
 * >Private< helper functions.
 **************************************************************************/
static int __neorv32_cpu_irq_id_check(uint8_t irq_sel);
static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index);
static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data);
 
 
/**********************************************************************//**
 * Private function: Check IRQ id.
 *
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
 * @return 0 if success, 1 if error (invalid irq_sel).
 **************************************************************************/
static int __neorv32_cpu_irq_id_check(uint8_t irq_sel) {
 
  if ((irq_sel == CSR_MIE_MSIE) || (irq_sel == CSR_MIE_MTIE) || (irq_sel == CSR_MIE_MEIE) ||
     ((irq_sel >= CSR_MIE_FIRQ0E) && (irq_sel <= CSR_MIE_FIRQ15E))) {
    return 0;
  }
  else {
    return 1;
  }
}
 
 
/**********************************************************************//**
 * Enable specific CPU interrupt.
 *
 * @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
 *
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
 * @return 0 if success, 1 if error (invalid irq_sel).
 **************************************************************************/
int neorv32_cpu_irq_enable(uint8_t irq_sel) {
 
  // check IRQ id
  if (__neorv32_cpu_irq_id_check(irq_sel)) {
    return 1;
  }
 
  register uint32_t mask = (uint32_t)(1 << irq_sel);
  asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
  return 0;
}
 
 
/**********************************************************************//**
 * Disable specific CPU interrupt.
 *
 * @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
 * @return 0 if success, 1 if error (invalid irq_sel).
 **************************************************************************/
int neorv32_cpu_irq_disable(uint8_t irq_sel) {
 
  // check IRQ id
  if (__neorv32_cpu_irq_id_check(irq_sel)) {
    return 1;
  }
 
  register uint32_t mask = (uint32_t)(1 << irq_sel);
  asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
  return 0;
}
 
 
/**********************************************************************//**
 * Get cycle count from cycle[h].
 *
 * @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR.
 *
 * @return Current cycle counter (64 bit).
 **************************************************************************/
uint64_t neorv32_cpu_get_cycle(void) {
 
  union {
    uint64_t uint64;
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
  } cycles;
 
  register uint32_t tmp1, tmp2, tmp3;
  while(1) {
    tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH);
    tmp2 = neorv32_cpu_csr_read(CSR_CYCLE);
    tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH);
    if (tmp1 == tmp3) {
      break;
    }
  }
 
  cycles.uint32[0] = tmp2;
  cycles.uint32[1] = tmp3;
 
  return cycles.uint64;
}
 
 
/**********************************************************************//**
 * Set mcycle[h] counter.
 *
 * @param[in] value New value for mcycle[h] CSR (64-bit).
 **************************************************************************/
void neorv32_cpu_set_mcycle(uint64_t value) {
 
  union {
    uint64_t uint64;
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
  } cycles;
 
  cycles.uint64 = value;
 
  neorv32_cpu_csr_write(CSR_MCYCLE,  0);
  neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]);
  neorv32_cpu_csr_write(CSR_MCYCLE,  cycles.uint32[0]);
}
 
 
/**********************************************************************//**
 * Get retired instructions counter from instret[h].
 *
 * @note The instret[h] CSR is shadowed copy of the instret[h] CSR.
 *
 * @return Current instructions counter (64 bit).
 **************************************************************************/
uint64_t neorv32_cpu_get_instret(void) {
 
  union {
    uint64_t uint64;
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
  } cycles;
 
  register uint32_t tmp1, tmp2, tmp3;
  while(1) {
    tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH);
    tmp2 = neorv32_cpu_csr_read(CSR_INSTRET);
    tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH);
    if (tmp1 == tmp3) {
      break;
    }
  }
 
  cycles.uint32[0] = tmp2;
  cycles.uint32[1] = tmp3;
 
  return cycles.uint64;
}
 
 
/**********************************************************************//**
 * Set retired instructions counter minstret[h].
 *
 * @param[in] value New value for mcycle[h] CSR (64-bit).
 **************************************************************************/
void neorv32_cpu_set_minstret(uint64_t value) {
 
  union {
    uint64_t uint64;
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
  } cycles;
 
  cycles.uint64 = value;
 
  neorv32_cpu_csr_write(CSR_MINSTRET,  0);
  neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]);
  neorv32_cpu_csr_write(CSR_MINSTRET,  cycles.uint32[0]);
}
 
 
/**********************************************************************//**
 * Get current system time from time[h] CSR.
 *
 * @note This function requires the MTIME system timer to be implemented.
 *
 * @return Current system time (64 bit).
 **************************************************************************/
uint64_t neorv32_cpu_get_systime(void) {
 
  union {
    uint64_t uint64;
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
  } cycles;
 
  register uint32_t tmp1, tmp2, tmp3;
  while(1) {
    tmp1 = neorv32_cpu_csr_read(CSR_TIMEH);
    tmp2 = neorv32_cpu_csr_read(CSR_TIME);
    tmp3 = neorv32_cpu_csr_read(CSR_TIMEH);
    if (tmp1 == tmp3) {
      break;
    }
  }
 
  cycles.uint32[0] = tmp2;
  cycles.uint32[1] = tmp3;
 
  return cycles.uint64;
}
 
 
/**********************************************************************//**
 * Delay function using busy wait.
 *
 * @note This function uses MTIME as time base. A simple ASM loop
 * is used as fall back if system timer is not implemented.
 *
 * @warning Delay time might be less precise if M extensions is not available
 * (especially if MTIME unit is not available).
 *
 * @param[in] time_ms Time in ms to wait (unsigned 32-bit).
 **************************************************************************/
void neorv32_cpu_delay_ms(uint32_t time_ms) {
 
  uint32_t clock = NEORV32_SYSINFO.CLK; // clock ticks per second
  clock = clock / 1000; // clock ticks per ms
 
  register uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);
  register uint64_t tmp = 0;
 
  // MTIME available?
  if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_MTIME)) {
 
    // use MTIME machine timer
    tmp = neorv32_mtime_get_time() + wait_cycles;
    while(1) {
      if (neorv32_mtime_get_time() >= tmp) {
        break;
      }
    }
  }
  else {
    // use ASM loop
    // warning! not really precise (especially if M extensions is not available)!
 
    const uint32_t loop_cycles_c = 16; // clock cycles per iteration of the ASM loop
    register uint32_t iterations = (uint32_t)(wait_cycles / loop_cycles_c); // M (div) extension would be nice here!
 
    asm volatile (" .balign 4                                        \n" // make sure this is 32-bit aligned
                  " __neorv32_cpu_delay_ms_start:                    \n"
                  " beq  %[cnt_r], zero, __neorv32_cpu_delay_ms_end  \n" // 3 cycles (not taken)
                  " beq  %[cnt_r], zero, __neorv32_cpu_delay_ms_end  \n" // 3 cycles (never taken)
                  " addi %[cnt_w], %[cnt_r], -1                      \n" // 2 cycles
                  " nop                                              \n" // 2 cycles
                  " j    __neorv32_cpu_delay_ms_start                \n" // 6 cycles
                  " __neorv32_cpu_delay_ms_end: "
                  : [cnt_w] "=r" (iterations) : [cnt_r] "r" (iterations));
  }
}
 
 
/**********************************************************************//**
 * Physical memory protection (PMP): Get number of available regions.
 *
 * @warning This function overrides all available PMPCFG* CSRs!
 * @note This function requires the PMP CPU extension.
 *
 * @return Returns number of available PMP regions.
 **************************************************************************/
uint32_t neorv32_cpu_pmp_get_num_regions(void) {
 
  // PMP implemented at all?
  if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_PMP)) == 0) {
    return 0;
  }
 
  // try setting R bit in all PMPCFG CSRs
  const uint32_t mask = 0x01010101;
  __neorv32_cpu_pmp_cfg_write(0, mask);
  __neorv32_cpu_pmp_cfg_write(1, mask);
  __neorv32_cpu_pmp_cfg_write(2, mask);
  __neorv32_cpu_pmp_cfg_write(3, mask);
 
  // sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
  union {
    uint32_t uint32;
    uint8_t  uint8[sizeof(uint32_t)/sizeof(uint8_t)];
  } cnt;
 
  cnt.uint32 = 0;
  cnt.uint32 += __neorv32_cpu_pmp_cfg_read(0) & mask;
  cnt.uint32 += __neorv32_cpu_pmp_cfg_read(1) & mask;
  cnt.uint32 += __neorv32_cpu_pmp_cfg_read(2) & mask;
  cnt.uint32 += __neorv32_cpu_pmp_cfg_read(3) & mask;
 
  // sum up bytes
  uint32_t num_regions = 0;
  num_regions += (uint32_t)cnt.uint8[0];
  num_regions += (uint32_t)cnt.uint8[1];
  num_regions += (uint32_t)cnt.uint8[2];
  num_regions += (uint32_t)cnt.uint8[3];
 
  return num_regions;
}
 
 
/**********************************************************************//**
 * Physical memory protection (PMP): Get minimal region size (granularity).
 *
 * @warning This function overrides PMPCFG0[0] and PMPADDR0 CSRs!
 * @note This function requires the PMP CPU extension.
 *
 * @return Returns minimal region size in bytes. Returns zero on error.
 **************************************************************************/
uint32_t neorv32_cpu_pmp_get_granularity(void) {
 
  // PMP implemented at all?
  if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_PMP)) == 0) {
    return 0;
  }
 
  neorv32_cpu_csr_write(CSR_PMPCFG0, neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xffffff00); // disable entry 0
  neorv32_cpu_csr_write(CSR_PMPADDR0, -1UL); // try to set all bits
  uint32_t tmp = neorv32_cpu_csr_read(CSR_PMPADDR0);
 
  // no bits set at all -> fail
  if (tmp == 0) {
    return 0;
  }
 
  // count trailing zeros
  uint32_t i = 2;
  while(1) {
    if (tmp & 1) {
      break;
    }
    tmp >>= 1;
    i++;
  }
 
  return 1<<i;
}
 
 
/**********************************************************************//**
 * Physical memory protection (PMP): Configure region.
 *
 * @warning Only TOR mode is supported.
 *
 * @note This function requires the PMP CPU extension.
 * @note Only use available PMP regions. Check before using neorv32_cpu_pmp_get_regions(void).
 *
 * @param[in] index Region number (index, 0..PMP_NUM_REGIONS-1).
 * @param[in] base Region base address.
 * @param[in] config Region configuration byte (see #NEORV32_PMPCFG_ATTRIBUTES_enum).
 * @return Returns 0 on success, 1 on failure.
 **************************************************************************/
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint8_t config) {
 
  if ((index > 15) || ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_PMP)) == 0)) {
    return 1;
  }
 
  // set base address
  base = base >> 2;
  switch(index & 0xf) {
    case 0:  neorv32_cpu_csr_write(CSR_PMPADDR0,  base); break;
    case 1:  neorv32_cpu_csr_write(CSR_PMPADDR1,  base); break;
    case 2:  neorv32_cpu_csr_write(CSR_PMPADDR2,  base); break;
    case 3:  neorv32_cpu_csr_write(CSR_PMPADDR3,  base); break;
    case 4:  neorv32_cpu_csr_write(CSR_PMPADDR4,  base); break;
    case 5:  neorv32_cpu_csr_write(CSR_PMPADDR5,  base); break;
    case 6:  neorv32_cpu_csr_write(CSR_PMPADDR6,  base); break;
    case 7:  neorv32_cpu_csr_write(CSR_PMPADDR7,  base); break;
    case 8:  neorv32_cpu_csr_write(CSR_PMPADDR8,  base); break;
    case 9:  neorv32_cpu_csr_write(CSR_PMPADDR9,  base); break;
    case 10: neorv32_cpu_csr_write(CSR_PMPADDR10, base); break;
    case 11: neorv32_cpu_csr_write(CSR_PMPADDR11, base); break;
    case 12: neorv32_cpu_csr_write(CSR_PMPADDR12, base); break;
    case 13: neorv32_cpu_csr_write(CSR_PMPADDR13, base); break;
    case 14: neorv32_cpu_csr_write(CSR_PMPADDR14, base); break;
    case 15: neorv32_cpu_csr_write(CSR_PMPADDR15, base); break;
    default: break;
  }
 
  // pmpcfg register index
  uint32_t pmpcfg_index = index >> 4; // 4 entries per pmpcfg csr
 
  // get current configuration
  uint32_t tmp = __neorv32_cpu_pmp_cfg_read(pmpcfg_index);
 
  // clear old configuration
  uint32_t config_mask = (((uint32_t)0xFF) << ((index%4)*8));
  tmp = tmp & (~config_mask);
 
  // set configuration
  uint32_t config_new = ((uint32_t)config) << ((index%4)*8);
  tmp = tmp | config_new;
  __neorv32_cpu_pmp_cfg_write(pmpcfg_index, tmp);
 
 
  // check if update was successful
  tmp = __neorv32_cpu_pmp_cfg_read(pmpcfg_index);
  if ((tmp & config_mask) == config_new) {
    return 0;
  } else {
    return 2;
  }
}
 
 
/**********************************************************************//**
 * Internal helper function: Read PMP configuration register 0..15
 *
 * @warning This function requires the PMP CPU extension.
 *
 * @param[in] index PMP CFG configuration register ID (0..15).
 * @return PMP CFG read data.
 **************************************************************************/
static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index) {
 
  uint32_t tmp = 0;
  switch(index & 3) {
    case 0: tmp = neorv32_cpu_csr_read(CSR_PMPCFG0); break;
    case 1: tmp = neorv32_cpu_csr_read(CSR_PMPCFG1); break;
    case 2: tmp = neorv32_cpu_csr_read(CSR_PMPCFG2); break;
    case 3: tmp = neorv32_cpu_csr_read(CSR_PMPCFG3); break;
    default: break;
  }
 
  return tmp;
}
 
 
/**********************************************************************//**
 * Internal helper function: Write PMP configuration register 0..4
 *
 * @warning This function requires the PMP CPU extension.
 *
 * @param[in] index PMP CFG configuration register ID (0..4).
 * @param[in] data PMP CFG write data.
 **************************************************************************/
static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data) {
 
  switch(index & 3) {
    case 0: neorv32_cpu_csr_write(CSR_PMPCFG0, data); break;
    case 1: neorv32_cpu_csr_write(CSR_PMPCFG1, data); break;
    case 2: neorv32_cpu_csr_write(CSR_PMPCFG2, data); break;
    case 3: neorv32_cpu_csr_write(CSR_PMPCFG3, data); break;
    default: break;
  }
}
 
 
/**********************************************************************//**
 * Hardware performance monitors (HPM): Get number of available HPM counters.
 *
 * @warning This function overrides all available mhpmcounter* CSRs.
 *
 * @return Returns number of available HPM counters (0..29).
 **************************************************************************/
uint32_t neorv32_cpu_hpm_get_counters(void) {
 
  // HPMs implemented at all?
  if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZIHPM)) == 0) {
    return 0;
  }
 
  // inhibit all HPM counters
  uint32_t tmp = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
  tmp |= 0xfffffff8;
  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp);
 
  // try setting all mhpmcounter* CSRs to 1
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER3,  1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER4,  1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER5,  1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER6,  1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER7,  1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER8,  1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER9,  1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER15, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER16, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER17, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER18, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER19, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER20, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER21, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER22, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER23, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER24, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER25, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER26, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER27, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER28, 1);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER29, 1);
 
  // sum up all written ones (only available HPM counter CSRs will return =! 0)
  uint32_t num_hpm_cnts = 0;
 
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER3);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER4);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER5);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER6);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER7);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER8);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER9);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER10);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER11);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER12);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER13);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER14);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER15);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER16);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER17);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER18);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER19);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER20);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER21);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER22);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER23);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER24);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER25);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER26);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER27);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER28);
  num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER29);
 
  return num_hpm_cnts;
}
 
 
/**********************************************************************//**
 * Hardware performance monitors (HPM): Get total counter width
 *
 * @warning This function overrides mhpmcounter3[h] CSRs.
 *
 * @return Size of HPM counter bits (1-64, 0 if not implemented at all).
 **************************************************************************/
uint32_t neorv32_cpu_hpm_get_size(void) {
 
  uint32_t tmp, size, i;
 
  // HPMs implemented at all?
  if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZIHPM)) == 0) {
    return 0;
  }
 
  // inhibit auto-update of HPM counter3
  tmp = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
  tmp |= 1 << CSR_MCOUNTINHIBIT_HPM3;
  neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp);
 
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER3,  0xffffffff);
  neorv32_cpu_csr_write(CSR_MHPMCOUNTER3H, 0xffffffff);
 
  if (neorv32_cpu_csr_read(CSR_MHPMCOUNTER3H) == 0) {
    size = 0;
    tmp = neorv32_cpu_csr_read(CSR_MHPMCOUNTER3);
  }
  else {
    size = 32;
    tmp = neorv32_cpu_csr_read(CSR_MHPMCOUNTER3H);
  }
 
  for (i=0; i<32; i++) {
    if (tmp & (1<<i)) {
      size++;
    }
  }
 
  return size;
}
 

Line No.	Rev	Author	Line
1	2	zero_gravi	`// #################################################################################################`
2			`// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >> #`
3			`// # ********************************************************************************************* #`
4			`// # BSD 3-Clause License #`
5			`// # #`
6	71	zero_gravi	`// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #`
7	2	zero_gravi	`// # #`
8			`// # Redistribution and use in source and binary forms, with or without modification, are #`
9			`// # permitted provided that the following conditions are met: #`
10			`// # #`
11			`// # 1. Redistributions of source code must retain the above copyright notice, this list of #`
12			`// # conditions and the following disclaimer. #`
13			`// # #`
14			`// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #`
15			`// # conditions and the following disclaimer in the documentation and/or other materials #`
16			`// # provided with the distribution. #`
17			`// # #`
18			`// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #`
19			`// # endorse or promote products derived from this software without specific prior written #`
20			`// # permission. #`
21			`// # #`
22			`// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #`
23			`// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #`
24			`// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #`
25			`// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #`
26			`// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #`
27			`// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #`
28			`// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #`
29			`// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #`
30			`// # OF THE POSSIBILITY OF SUCH DAMAGE. #`
31			`// # ********************************************************************************************* #`
32			`// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #`
33			`// #################################################################################################`
34
35
36			`/********************************************************************//`
37			`* @file neorv32_cpu.c`
38			`* @brief CPU Core Functions HW driver source file.`
39			`**************************************************************************/`
40
41			`#include "neorv32.h"`
42			`#include "neorv32_cpu.h"`
43
44
45	53	zero_gravi	`/********************************************************************//`
46			`* Unavailable extensions warning.`
47			`**************************************************************************/`
48			`#if defined __riscv_d \|\| (__riscv_flen == 64)`
49			`#error Double-precision floating-point extension <D/Zdinx> is NOT supported!`
50			`#endif`
51
52			`#if (__riscv_xlen > 32)`
53			`#error Only 32-bit <rv32> is supported!`
54			`#endif`
55
56			`#ifdef __riscv_fdiv`
57			`#warning Floating-point division instruction <FDIV> is NOT supported yet!`
58			`#endif`
59
60			`#ifdef __riscv_fsqrt`
61			`#warning Floating-point square root instruction <FSQRT> is NOT supported yet!`
62			`#endif`
63
64
65	2	zero_gravi	`/********************************************************************//`
66	45	zero_gravi	`* >Private< helper functions.`
67			`**************************************************************************/`
68	47	zero_gravi	`static int __neorv32_cpu_irq_id_check(uint8_t irq_sel);`
69	45	zero_gravi	`static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index);`
70			`static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data);`
71
72
73			`/********************************************************************//`
74	47	zero_gravi	`* Private function: Check IRQ id.`
75			`*`
76			`* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.`
77			`* @return 0 if success, 1 if error (invalid irq_sel).`
78			`**************************************************************************/`
79			`static int __neorv32_cpu_irq_id_check(uint8_t irq_sel) {`
80
81	48	zero_gravi	`if ((irq_sel == CSR_MIE_MSIE) \|\| (irq_sel == CSR_MIE_MTIE) \|\| (irq_sel == CSR_MIE_MEIE) \|\|`
82			`((irq_sel >= CSR_MIE_FIRQ0E) && (irq_sel <= CSR_MIE_FIRQ15E))) {`
83	47	zero_gravi	`return 0;`
84			`}`
85			`else {`
86			`return 1;`
87			`}`
88			`}`
89
90
91			`/********************************************************************//`
92	2	zero_gravi	`* Enable specific CPU interrupt.`
93			`*`
94			`* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.`
95			`*`
96	42	zero_gravi	`* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.`
97	12	zero_gravi	`* @return 0 if success, 1 if error (invalid irq_sel).`
98	2	zero_gravi	`**************************************************************************/`
99			`int neorv32_cpu_irq_enable(uint8_t irq_sel) {`
100
101	47	zero_gravi	`// check IRQ id`
102			`if (__neorv32_cpu_irq_id_check(irq_sel)) {`
103	2	zero_gravi	`return 1;`
104			`}`
105
106			`register uint32_t mask = (uint32_t)(1 << irq_sel);`
107			`asm volatile ("csrrs zero, mie, %0" : : "r" (mask));`
108			`return 0;`
109			`}`
110
111
112			`/********************************************************************//`
113			`* Disable specific CPU interrupt.`
114			`*`
115	42	zero_gravi	`* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.`
116	12	zero_gravi	`* @return 0 if success, 1 if error (invalid irq_sel).`
117	2	zero_gravi	`**************************************************************************/`
118			`int neorv32_cpu_irq_disable(uint8_t irq_sel) {`
119
120	47	zero_gravi	`// check IRQ id`
121			`if (__neorv32_cpu_irq_id_check(irq_sel)) {`
122	2	zero_gravi	`return 1;`
123			`}`
124
125			`register uint32_t mask = (uint32_t)(1 << irq_sel);`
126			`asm volatile ("csrrc zero, mie, %0" : : "r" (mask));`
127			`return 0;`
128			`}`
129
130
131			`/********************************************************************//`
132	12	zero_gravi	`* Get cycle count from cycle[h].`
133			`*`
134			`* @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR.`
135			`*`
136			`* @return Current cycle counter (64 bit).`
137			`**************************************************************************/`
138			`uint64_t neorv32_cpu_get_cycle(void) {`
139
140			`union {`
141			`uint64_t uint64;`
142	71	zero_gravi	`uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];`
143	12	zero_gravi	`} cycles;`
144
145	64	zero_gravi	`register uint32_t tmp1, tmp2, tmp3;`
146	12	zero_gravi	`while(1) {`
147			`tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH);`
148			`tmp2 = neorv32_cpu_csr_read(CSR_CYCLE);`
149			`tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH);`
150			`if (tmp1 == tmp3) {`
151			`break;`
152			`}`
153			`}`
154
155			`cycles.uint32[0] = tmp2;`
156			`cycles.uint32[1] = tmp3;`
157
158			`return cycles.uint64;`
159			`}`
160
161
162			`/********************************************************************//`
163			`* Set mcycle[h] counter.`
164			`*`
165			`* @param[in] value New value for mcycle[h] CSR (64-bit).`
166			`**************************************************************************/`
167			`void neorv32_cpu_set_mcycle(uint64_t value) {`
168
169			`union {`
170			`uint64_t uint64;`
171	71	zero_gravi	`uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];`
172	12	zero_gravi	`} cycles;`
173
174			`cycles.uint64 = value;`
175
176			`neorv32_cpu_csr_write(CSR_MCYCLE, 0);`
177			`neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]);`
178			`neorv32_cpu_csr_write(CSR_MCYCLE, cycles.uint32[0]);`
179			`}`
180
181
182			`/********************************************************************//`
183			`* Get retired instructions counter from instret[h].`
184			`*`
185			`* @note The instret[h] CSR is shadowed copy of the instret[h] CSR.`
186			`*`
187			`* @return Current instructions counter (64 bit).`
188			`**************************************************************************/`
189			`uint64_t neorv32_cpu_get_instret(void) {`
190
191			`union {`
192			`uint64_t uint64;`
193	71	zero_gravi	`uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];`
194	12	zero_gravi	`} cycles;`
195
196	64	zero_gravi	`register uint32_t tmp1, tmp2, tmp3;`
197	12	zero_gravi	`while(1) {`
198			`tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH);`
199			`tmp2 = neorv32_cpu_csr_read(CSR_INSTRET);`
200			`tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH);`
201			`if (tmp1 == tmp3) {`
202			`break;`
203			`}`
204			`}`
205
206			`cycles.uint32[0] = tmp2;`
207			`cycles.uint32[1] = tmp3;`
208
209			`return cycles.uint64;`
210			`}`
211
212
213			`/********************************************************************//`
214			`* Set retired instructions counter minstret[h].`
215			`*`
216			`* @param[in] value New value for mcycle[h] CSR (64-bit).`
217			`**************************************************************************/`
218			`void neorv32_cpu_set_minstret(uint64_t value) {`
219
220			`union {`
221			`uint64_t uint64;`
222	71	zero_gravi	`uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];`
223	12	zero_gravi	`} cycles;`
224
225			`cycles.uint64 = value;`
226
227			`neorv32_cpu_csr_write(CSR_MINSTRET, 0);`
228			`neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]);`
229			`neorv32_cpu_csr_write(CSR_MINSTRET, cycles.uint32[0]);`
230			`}`
231
232
233			`/********************************************************************//`
234			`* Get current system time from time[h] CSR.`
235			`*`
236			`* @note This function requires the MTIME system timer to be implemented.`
237			`*`
238			`* @return Current system time (64 bit).`
239			`**************************************************************************/`
240			`uint64_t neorv32_cpu_get_systime(void) {`
241
242			`union {`
243			`uint64_t uint64;`
244	71	zero_gravi	`uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];`
245	12	zero_gravi	`} cycles;`
246
247	64	zero_gravi	`register uint32_t tmp1, tmp2, tmp3;`
248	12	zero_gravi	`while(1) {`
249			`tmp1 = neorv32_cpu_csr_read(CSR_TIMEH);`
250			`tmp2 = neorv32_cpu_csr_read(CSR_TIME);`
251			`tmp3 = neorv32_cpu_csr_read(CSR_TIMEH);`
252			`if (tmp1 == tmp3) {`
253			`break;`
254			`}`
255			`}`
256
257			`cycles.uint32[0] = tmp2;`
258			`cycles.uint32[1] = tmp3;`
259
260			`return cycles.uint64;`
261			`}`
262
263
264			`/********************************************************************//`
265	64	zero_gravi	`* Delay function using busy wait.`
266	2	zero_gravi	`*`
267	72	zero_gravi	`* @note This function uses MTIME as time base. A simple ASM loop`
268			`* is used as fall back if system timer is not implemented.`
269	39	zero_gravi	`*`
270	64	zero_gravi	`* @warning Delay time might be less precise if M extensions is not available`
271			`* (especially if MTIME unit is not available).`
272			`*`
273			`* @param[in] time_ms Time in ms to wait (unsigned 32-bit).`
274	2	zero_gravi	`**************************************************************************/`
275	64	zero_gravi	`void neorv32_cpu_delay_ms(uint32_t time_ms) {`
276	2	zero_gravi
277	64	zero_gravi	`uint32_t clock = NEORV32_SYSINFO.CLK; // clock ticks per second`
278			`clock = clock / 1000; // clock ticks per ms`
279	2	zero_gravi
280	72	zero_gravi	`register uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);`
281			`register uint64_t tmp = 0;`
282	64	zero_gravi
283	72	zero_gravi	`// MTIME available?`
284			`if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_MTIME)) {`
285	64	zero_gravi
286			`// use MTIME machine timer`
287	72	zero_gravi	`tmp = neorv32_mtime_get_time() + wait_cycles;`
288	64	zero_gravi	`while(1) {`
289	72	zero_gravi	`if (neorv32_mtime_get_time() >= tmp) {`
290	64	zero_gravi	`break;`
291			`}`
292			`}`
293	56	zero_gravi	`}`
294	64	zero_gravi	`else {`
295			`// use ASM loop`
296			`// warning! not really precise (especially if M extensions is not available)!`
297	56	zero_gravi
298	64	zero_gravi	`const uint32_t loop_cycles_c = 16; // clock cycles per iteration of the ASM loop`
299	72	zero_gravi	`register uint32_t iterations = (uint32_t)(wait_cycles / loop_cycles_c); // M (div) extension would be nice here!`
300	39	zero_gravi
301	64	zero_gravi	`asm volatile (" .balign 4 \n" // make sure this is 32-bit aligned`
302			`" __neorv32_cpu_delay_ms_start: \n"`
303			`" beq %[cnt_r], zero, __neorv32_cpu_delay_ms_end \n" // 3 cycles (not taken)`
304			`" beq %[cnt_r], zero, __neorv32_cpu_delay_ms_end \n" // 3 cycles (never taken)`
305			`" addi %[cnt_w], %[cnt_r], -1 \n" // 2 cycles`
306			`" nop \n" // 2 cycles`
307			`" j __neorv32_cpu_delay_ms_start \n" // 6 cycles`
308			`" __neorv32_cpu_delay_ms_end: "`
309			`: [cnt_w] "=r" (iterations) : [cnt_r] "r" (iterations));`
310			`}`
311	2	zero_gravi	`}`
312
313	15	zero_gravi
314			`/********************************************************************//`
315	42	zero_gravi	`* Physical memory protection (PMP): Get number of available regions.`
316			`*`
317	73	zero_gravi	`* @warning This function overrides all available PMPCFG* CSRs!`
318			`* @note This function requires the PMP CPU extension.`
319	42	zero_gravi	`*`
320			`* @return Returns number of available PMP regions.`
321			`**************************************************************************/`
322			`uint32_t neorv32_cpu_pmp_get_num_regions(void) {`
323
324	58	zero_gravi	`// PMP implemented at all?`
325	72	zero_gravi	`if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_PMP)) == 0) {`
326	58	zero_gravi	`return 0;`
327			`}`
328
329	42	zero_gravi	`// try setting R bit in all PMPCFG CSRs`
330	65	zero_gravi	`const uint32_t mask = 0x01010101;`
331	73	zero_gravi	`__neorv32_cpu_pmp_cfg_write(0, mask);`
332			`__neorv32_cpu_pmp_cfg_write(1, mask);`
333			`__neorv32_cpu_pmp_cfg_write(2, mask);`
334			`__neorv32_cpu_pmp_cfg_write(3, mask);`
335	42	zero_gravi
336			`// sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)`
337			`union {`
338			`uint32_t uint32;`
339			`uint8_t uint8[sizeof(uint32_t)/sizeof(uint8_t)];`
340			`} cnt;`
341
342			`cnt.uint32 = 0;`
343	73	zero_gravi	`cnt.uint32 += __neorv32_cpu_pmp_cfg_read(0) & mask;`
344			`cnt.uint32 += __neorv32_cpu_pmp_cfg_read(1) & mask;`
345			`cnt.uint32 += __neorv32_cpu_pmp_cfg_read(2) & mask;`
346			`cnt.uint32 += __neorv32_cpu_pmp_cfg_read(3) & mask;`
347	42	zero_gravi
348			`// sum up bytes`
349			`uint32_t num_regions = 0;`
350			`num_regions += (uint32_t)cnt.uint8[0];`
351			`num_regions += (uint32_t)cnt.uint8[1];`
352			`num_regions += (uint32_t)cnt.uint8[2];`
353			`num_regions += (uint32_t)cnt.uint8[3];`
354
355			`return num_regions;`
356			`}`
357
358
359			`/********************************************************************//`
360	40	zero_gravi	`* Physical memory protection (PMP): Get minimal region size (granularity).`
361			`*`
362	73	zero_gravi	`* @warning This function overrides PMPCFG0[0] and PMPADDR0 CSRs!`
363			`* @note This function requires the PMP CPU extension.`
364	40	zero_gravi	`*`
365	73	zero_gravi	`* @return Returns minimal region size in bytes. Returns zero on error.`
366	40	zero_gravi	`**************************************************************************/`
367			`uint32_t neorv32_cpu_pmp_get_granularity(void) {`
368
369	73	zero_gravi	`// PMP implemented at all?`
370			`if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_PMP)) == 0) {`
371			`return 0;`
372			`}`
373	40	zero_gravi
374	73	zero_gravi	`neorv32_cpu_csr_write(CSR_PMPCFG0, neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xffffff00); // disable entry 0`
375			`neorv32_cpu_csr_write(CSR_PMPADDR0, -1UL); // try to set all bits`
376			`uint32_t tmp = neorv32_cpu_csr_read(CSR_PMPADDR0);`
377	40	zero_gravi
378	73	zero_gravi	`// no bits set at all -> fail`
379			`if (tmp == 0) {`
380			`return 0;`
381			`}`
382
383			`// count trailing zeros`
384			`uint32_t i = 2;`
385			`while(1) {`
386			`if (tmp & 1) {`
387	40	zero_gravi	`break;`
388			`}`
389	73	zero_gravi	`tmp >>= 1;`
390			`i++;`
391	40	zero_gravi	`}`
392
393	73	zero_gravi	`return 1<<i;`
394	40	zero_gravi	`}`
395
396
397			`/********************************************************************//`
398			`* Physical memory protection (PMP): Configure region.`
399			`*`
400	73	zero_gravi	`* @warning Only TOR mode is supported.`
401	40	zero_gravi	`*`
402	73	zero_gravi	`* @note This function requires the PMP CPU extension.`
403			`* @note Only use available PMP regions. Check before using neorv32_cpu_pmp_get_regions(void).`
404	40	zero_gravi	`*`
405	42	zero_gravi	`* @param[in] index Region number (index, 0..PMP_NUM_REGIONS-1).`
406	73	zero_gravi	`* @param[in] base Region base address.`
407			`* @param[in] config Region configuration byte (see #NEORV32_PMPCFG_ATTRIBUTES_enum).`
408	40	zero_gravi	`* @return Returns 0 on success, 1 on failure.`
409			`**************************************************************************/`
410	73	zero_gravi	`int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint8_t config) {`
411	40	zero_gravi
412	73	zero_gravi	`if ((index > 15) \|\| ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_PMP)) == 0)) {`
413			`return 1;`
414	40	zero_gravi	`}`
415
416	73	zero_gravi	`// set base address`
417			`base = base >> 2;`
418			`switch(index & 0xf) {`
419			`case 0: neorv32_cpu_csr_write(CSR_PMPADDR0, base); break;`
420			`case 1: neorv32_cpu_csr_write(CSR_PMPADDR1, base); break;`
421			`case 2: neorv32_cpu_csr_write(CSR_PMPADDR2, base); break;`
422			`case 3: neorv32_cpu_csr_write(CSR_PMPADDR3, base); break;`
423			`case 4: neorv32_cpu_csr_write(CSR_PMPADDR4, base); break;`
424			`case 5: neorv32_cpu_csr_write(CSR_PMPADDR5, base); break;`
425			`case 6: neorv32_cpu_csr_write(CSR_PMPADDR6, base); break;`
426			`case 7: neorv32_cpu_csr_write(CSR_PMPADDR7, base); break;`
427			`case 8: neorv32_cpu_csr_write(CSR_PMPADDR8, base); break;`
428			`case 9: neorv32_cpu_csr_write(CSR_PMPADDR9, base); break;`
429			`case 10: neorv32_cpu_csr_write(CSR_PMPADDR10, base); break;`
430			`case 11: neorv32_cpu_csr_write(CSR_PMPADDR11, base); break;`
431			`case 12: neorv32_cpu_csr_write(CSR_PMPADDR12, base); break;`
432			`case 13: neorv32_cpu_csr_write(CSR_PMPADDR13, base); break;`
433			`case 14: neorv32_cpu_csr_write(CSR_PMPADDR14, base); break;`
434			`case 15: neorv32_cpu_csr_write(CSR_PMPADDR15, base); break;`
435			`default: break;`
436	40	zero_gravi	`}`
437
438	45	zero_gravi	`// pmpcfg register index`
439			`uint32_t pmpcfg_index = index >> 4; // 4 entries per pmpcfg csr`
440
441	73	zero_gravi	`// get current configuration`
442			`uint32_t tmp = __neorv32_cpu_pmp_cfg_read(pmpcfg_index);`
443	40	zero_gravi
444			`// clear old configuration`
445	73	zero_gravi	`uint32_t config_mask = (((uint32_t)0xFF) << ((index%4)*8));`
446			`tmp = tmp & (~config_mask);`
447	40	zero_gravi
448	73	zero_gravi	`// set configuration`
449			`uint32_t config_new = ((uint32_t)config) << ((index%4)*8);`
450			`tmp = tmp \| config_new;`
451			`__neorv32_cpu_pmp_cfg_write(pmpcfg_index, tmp);`
452	45	zero_gravi
453	40	zero_gravi
454	73	zero_gravi	`// check if update was successful`
455			`tmp = __neorv32_cpu_pmp_cfg_read(pmpcfg_index);`
456			`if ((tmp & config_mask) == config_new) {`
457			`return 0;`
458			`} else {`
459			`return 2;`
460	40	zero_gravi	`}`
461	45	zero_gravi	`}`
462
463
464			`/********************************************************************//`
465			`* Internal helper function: Read PMP configuration register 0..15`
466			`*`
467			`* @warning This function requires the PMP CPU extension.`
468			`*`
469			`* @param[in] index PMP CFG configuration register ID (0..15).`
470			`* @return PMP CFG read data.`
471			`**************************************************************************/`
472			`static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index) {`
473
474			`uint32_t tmp = 0;`
475	73	zero_gravi	`switch(index & 3) {`
476			`case 0: tmp = neorv32_cpu_csr_read(CSR_PMPCFG0); break;`
477			`case 1: tmp = neorv32_cpu_csr_read(CSR_PMPCFG1); break;`
478			`case 2: tmp = neorv32_cpu_csr_read(CSR_PMPCFG2); break;`
479			`case 3: tmp = neorv32_cpu_csr_read(CSR_PMPCFG3); break;`
480	42	zero_gravi	`default: break;`
481	40	zero_gravi	`}`
482
483	45	zero_gravi	`return tmp;`
484	40	zero_gravi	`}`
485	42	zero_gravi
486
487			`/********************************************************************//`
488	73	zero_gravi	`* Internal helper function: Write PMP configuration register 0..4`
489	45	zero_gravi	`*`
490			`* @warning This function requires the PMP CPU extension.`
491			`*`
492	73	zero_gravi	`* @param[in] index PMP CFG configuration register ID (0..4).`
493	45	zero_gravi	`* @param[in] data PMP CFG write data.`
494			`**************************************************************************/`
495			`static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data) {`
496
497	73	zero_gravi	`switch(index & 3) {`
498			`case 0: neorv32_cpu_csr_write(CSR_PMPCFG0, data); break;`
499			`case 1: neorv32_cpu_csr_write(CSR_PMPCFG1, data); break;`
500			`case 2: neorv32_cpu_csr_write(CSR_PMPCFG2, data); break;`

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