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// #################################################################################################
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// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32_cpu.c
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* @author Stephan Nolting
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* @brief CPU Core Functions HW driver source file.
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**************************************************************************/
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#include "neorv32.h"
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#include "neorv32_cpu.h"
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/**********************************************************************//**
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* Enable/disable CPU extension during runtime via the 'misa' CSR.
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*
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* @warning This is still highly experimental! This function requires the Zicsr + Zifencei CPU extensions.
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*
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* @param[in] sel Bit to be set in misa CSR / extension to be enabled. See #NEORV32_CPU_MISA_enum.
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* @param[in] state Set 1 to enable the selected extension, set 0 to disable it;
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* return 0 if success, 1 if error (invalid sel or extension cannot be enabled).
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**************************************************************************/
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int neorv32_cpu_switch_extension(int sel, int state) {
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// get current misa setting
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uint32_t misa_curr = neorv32_cpu_csr_read(CSR_MISA);
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uint32_t misa_prev = misa_curr;
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// abort if misa.z is cleared
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if ((misa_curr & (1 << CPU_MISA_Z_EXT)) == 0) {
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return 1;
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}
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// out of range?
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if (sel > 25) {
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return 1;
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}
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// enable/disable selected extension
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if (state & 1) {
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misa_curr |= (1 << sel);
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}
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else {
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misa_curr &= ~(1 << sel);
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}
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// try updating misa
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neorv32_cpu_csr_write(CSR_MISA, misa_curr);
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asm volatile("fence.i"); // required to flush prefetch buffers
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asm volatile("nop");
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// dit it work?
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if (neorv32_cpu_csr_read(CSR_MISA) == misa_prev) {
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return 1; // nope
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}
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else {
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return 0; // fine
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}
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}
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/**********************************************************************//**
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* Enable specific CPU interrupt.
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*
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
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return 1;
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
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return 0;
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}
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/**********************************************************************//**
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* Disable specific CPU interrupt.
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
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return 1;
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
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return 0;
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}
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/**********************************************************************//**
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* Simple delay function (not very precise) using busy wait.
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*
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* @param[in] time_ms Time in ms to wait.
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**************************************************************************/
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void neorv32_cpu_delay_ms(uint32_t time_ms) {
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uint32_t clock_speed = neorv32_cpu_csr_read(CSR_MCLOCK) >> 10; // fake divide by 1000
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clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles)
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uint32_t cnt = clock_speed * time_ms;
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// one iteration = ~30 cycles
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while (cnt) {
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asm volatile("nop");
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asm volatile("nop");
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asm volatile("nop");
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asm volatile("nop");
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cnt--;
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}
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}
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