OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_gpio.c] - Blame information for rev 46

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 zero_gravi
// #################################################################################################
2
// # << NEORV32: neorv32_gpio.c - General Purpose Input/Output Port HW Driver (Source) >>          #
3
// # ********************************************************************************************* #
4
// # BSD 3-Clause License                                                                          #
5
// #                                                                                               #
6 44 zero_gravi
// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi
// #                                                                                               #
8
// # Redistribution and use in source and binary forms, with or without modification, are          #
9
// # permitted provided that the following conditions are met:                                     #
10
// #                                                                                               #
11
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12
// #    conditions and the following disclaimer.                                                   #
13
// #                                                                                               #
14
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15
// #    conditions and the following disclaimer in the documentation and/or other materials        #
16
// #    provided with the distribution.                                                            #
17
// #                                                                                               #
18
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19
// #    endorse or promote products derived from this software without specific prior written      #
20
// #    permission.                                                                                #
21
// #                                                                                               #
22
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
31
// # ********************************************************************************************* #
32
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33
// #################################################################################################
34
 
35
 
36
/**********************************************************************//**
37
 * @file neorv32_gpio.c
38
 * @author Stephan Nolting
39
 * @brief General purpose input/output port unit (GPIO) HW driver source file.
40
 *
41 44 zero_gravi
 * @note These functions should only be used if the GPIO unit was synthesized (IO_GPIO_EN = true).
42 2 zero_gravi
 **************************************************************************/
43
 
44
#include "neorv32.h"
45
#include "neorv32_gpio.h"
46
 
47
 
48
/**********************************************************************//**
49
 * Check if GPIO unit was synthesized.
50
 *
51
 * @return 0 if GPIO was not synthesized, 1 if GPIO is available.
52
 **************************************************************************/
53
int neorv32_gpio_available(void) {
54
 
55 12 zero_gravi
  if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_GPIO)) {
56 2 zero_gravi
    return 1;
57
  }
58
  else {
59
    return 0;
60
  }
61
}
62
 
63
 
64
/**********************************************************************//**
65
 * Set single pin of GPIO's output port.
66
 *
67 23 zero_gravi
 * @param[in] pin Output pin number to be set (0..31).
68 2 zero_gravi
 **************************************************************************/
69
void neorv32_gpio_pin_set(uint8_t pin) {
70
 
71 23 zero_gravi
  pin &= 0x1f;
72
  GPIO_OUTPUT = GPIO_OUTPUT | (uint32_t)(1 << pin);
73 2 zero_gravi
}
74
 
75
 
76
/**********************************************************************//**
77
 * Clear single pin of GPIO's output port.
78
 *
79 23 zero_gravi
 * @param[in] pin Output pin number to be cleared (0..31).
80 2 zero_gravi
 **************************************************************************/
81
void neorv32_gpio_pin_clr(uint8_t pin) {
82
 
83 23 zero_gravi
  pin &= 0x1f;
84
  GPIO_OUTPUT = GPIO_OUTPUT & ~((uint32_t)(1 << pin));
85 2 zero_gravi
}
86
 
87
 
88
/**********************************************************************//**
89
 * Toggle single pin of GPIO's output port.
90
 *
91 23 zero_gravi
 * @param[in] pin Output pin number to be toggled (0..31).
92 2 zero_gravi
 **************************************************************************/
93
void neorv32_gpio_pin_toggle(uint8_t pin) {
94
 
95 23 zero_gravi
  pin &= 0x1f;
96
  GPIO_OUTPUT = GPIO_OUTPUT ^ (uint32_t)(1 << pin);
97 2 zero_gravi
}
98
 
99
 
100
/**********************************************************************//**
101
 * Get single pin of GPIO's input port.
102
 *
103 23 zero_gravi
 * @param[in] pin Input pin to be read (0..31).
104
 * @return uint32_t: =0 if pin is low, !=0 if pin is high.
105 2 zero_gravi
 **************************************************************************/
106 23 zero_gravi
uint32_t neorv32_gpio_pin_get(uint8_t pin) {
107 2 zero_gravi
 
108 23 zero_gravi
  pin &= 0x1f;
109
  return GPIO_INPUT & (uint32_t)(1 << pin);
110 2 zero_gravi
}
111
 
112
 
113
/**********************************************************************//**
114
 * Set complete GPIO output port.
115
 *
116 23 zero_gravi
 * @param[in] port_data New output port value (32-bit).
117 2 zero_gravi
 **************************************************************************/
118 23 zero_gravi
void neorv32_gpio_port_set(uint32_t port_data) {
119 2 zero_gravi
 
120
  GPIO_OUTPUT = port_data;
121
}
122
 
123
 
124
/**********************************************************************//**
125
 * Get complete GPIO input port.
126
 *
127 23 zero_gravi
 * @return Current input port state (32-bit).
128 2 zero_gravi
 **************************************************************************/
129 23 zero_gravi
uint32_t neorv32_gpio_port_get(void) {
130 2 zero_gravi
 
131
  return GPIO_INPUT;
132
}
133 23 zero_gravi
 
134
 
135
/**********************************************************************//**
136
 * Configure pin-change IRQ mask for input pins.
137
 *
138
 * @note The pin-change IRQ will trigger on any transition (rising and falling edge) for any enabled input pin.
139
 *
140 26 zero_gravi
 * @param[in] pin_sel Mask to select which input pins can cause a pin-change IRQ (32-bit), 1 = pin enabled.
141 23 zero_gravi
 **************************************************************************/
142
void neorv32_gpio_pin_change_config(uint32_t pin_sel) {
143
 
144
  GPIO_INPUT = pin_sel;
145
}
146
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.