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// #################################################################################################
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// # << NEORV32: neorv32_rte.c - NEORV32 Runtime Environment >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32_rte.c
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* @author Stephan Nolting
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* @brief NEORV32 Runtime Environment.
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**************************************************************************/
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#include "neorv32.h"
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#include "neorv32_rte.h"
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/**********************************************************************//**
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* The >private< trap vector look-up table of the NEORV32 RTE.
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**************************************************************************/
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static uint32_t __neorv32_rte_vector_lut[16] __attribute__((unused)); // trap handler vector table
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// private functions
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static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused));
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static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
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/**********************************************************************//**
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* Setup NEORV32 runtime environment.
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*
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* @note This function installs a debug handler for ALL exception and interrupt sources, which
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* gives detailed information about the exception/interrupt. Actual handler can be installed afterwards
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* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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**************************************************************************/
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void neorv32_rte_setup(void) {
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// configure trap handler base address
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uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
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neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
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// install debug handler for all sources
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uint8_t id;
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for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) {
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neorv32_rte_exception_uninstall(id); // this will configure the debug handler
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}
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}
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/**********************************************************************//**
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* Install exception handler function to NEORV32 runtime environment.
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*
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* @note Interrupt sources have to be explicitly enabled by the user via the CSR.mie bits via neorv32_cpu_irq_enable(uint8_t irq_sel)
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* and the global interrupt enable bit mstatus.mie via neorv32_cpu_eint(void).
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*
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* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
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* @param[in] handler The actual handler function for the specified exception (function MUST be of type "void function(void);").
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* return 0 if success, 1 if error (invalid id or targeted exception not supported).
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**************************************************************************/
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int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)) {
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// id valid?
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if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
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(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) ||
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(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) ||
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(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) ||
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(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) {
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__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler
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return 0;
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}
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return 1;
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}
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/**********************************************************************//**
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* Uninstall exception handler function from NEORV32 runtime environment, which was
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* previously installed via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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*
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* @note Interrupt sources have to be explicitly disabled by the user via the CSR.mie bits via neorv32_cpu_irq_disable(uint8_t irq_sel)
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* and/or the global interrupt enable bit mstatus.mie via neorv32_cpu_dint(void).
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*
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* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
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* return 0 if success, 1 if error (invalid id or targeted exception not supported).
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**************************************************************************/
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int neorv32_rte_exception_uninstall(uint8_t id) {
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// id valid?
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if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
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(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) ||
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(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) ||
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(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) ||
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(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) {
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__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidently triggered
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return 0;
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}
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return 1;
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}
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/**********************************************************************//**
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* This is the core of the NEORV32 RTE.
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*
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* @note This function must no be explicitly used by the user.
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* @warning When using the the RTE, this function is the ONLY function that can use the 'interrupt' attribute!
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**************************************************************************/
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static void __attribute__((__interrupt__)) __attribute__((aligned(16))) __neorv32_rte_core(void) {
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register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
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// compute return address
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if ((rte_mcause & 0x80000000) == 0) { // modify pc only if exception
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// get low half word of faulting instruction
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register uint32_t rte_trap_inst;
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (rte_trap_inst) : [input_i] "r" (rte_mepc));
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if ((rte_trap_inst & 3) == 3) { // faulting instruction is uncompressed instruction
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rte_mepc += 4;
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}
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else { // faulting instruction is compressed instruction
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rte_mepc += 2;
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}
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// store new return address
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neorv32_cpu_csr_write(CSR_MEPC, rte_mepc);
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}
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// find according trap handler
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register uint32_t rte_handler = (uint32_t)(&__neorv32_rte_debug_exc_handler);
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switch (rte_mcause) {
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case TRAP_CODE_I_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break;
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case TRAP_CODE_I_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
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case TRAP_CODE_I_ILLEGAL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break;
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case TRAP_CODE_BREAKPOINT: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break;
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case TRAP_CODE_L_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_L_MISALIGNED]; break;
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case TRAP_CODE_L_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_L_ACCESS]; break;
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case TRAP_CODE_S_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_MISALIGNED]; break;
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case TRAP_CODE_S_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break;
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case TRAP_CODE_MENV_CALL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break;
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case TRAP_CODE_MSI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break;
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case TRAP_CODE_MTI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MTI]; break;
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case TRAP_CODE_MEI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MEI]; break;
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case TRAP_CODE_FIRQ_0: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_0]; break;
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case TRAP_CODE_FIRQ_1: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_1]; break;
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case TRAP_CODE_FIRQ_2: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_2]; break;
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case TRAP_CODE_FIRQ_3: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_3]; break;
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default: break;
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}
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// execute handler
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void (*handler_pnt)(void);
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handler_pnt = (void*)rte_handler;
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(*handler_pnt)();
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}
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/**********************************************************************//**
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* NEORV32 runtime environment: Debug exception handler, printing various exception/interrupt information via UART.
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zero_gravi |
* @note This function is used by neorv32_rte_exception_uninstall(void) only.
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zero_gravi |
**************************************************************************/
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static void __neorv32_rte_debug_exc_handler(void) {
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zero_gravi |
// intro
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neorv32_uart_printf("<RTE> ");
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zero_gravi |
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zero_gravi |
// cause
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zero_gravi |
register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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switch (trap_cause) {
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case TRAP_CODE_I_MISALIGNED: neorv32_uart_printf("Instruction address misaligned"); break;
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case TRAP_CODE_I_ACCESS: neorv32_uart_printf("Instruction access fault"); break;
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case TRAP_CODE_I_ILLEGAL: neorv32_uart_printf("Illegal instruction"); break;
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case TRAP_CODE_BREAKPOINT: neorv32_uart_printf("Breakpoint (EBREAK)"); break;
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case TRAP_CODE_L_MISALIGNED: neorv32_uart_printf("Load address misaligned"); break;
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case TRAP_CODE_L_ACCESS: neorv32_uart_printf("Load access fault"); break;
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case TRAP_CODE_S_MISALIGNED: neorv32_uart_printf("Store address misaligned"); break;
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case TRAP_CODE_S_ACCESS: neorv32_uart_printf("Store access fault"); break;
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case TRAP_CODE_MENV_CALL: neorv32_uart_printf("Environment call from M-mode"); break;
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case TRAP_CODE_MSI: neorv32_uart_printf("Machine software interrupt"); break;
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case TRAP_CODE_MTI: neorv32_uart_printf("Machine timer interrupt"); break;
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case TRAP_CODE_MEI: neorv32_uart_printf("Machine external interrupt"); break;
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case TRAP_CODE_FIRQ_0: neorv32_uart_printf("Fast interrupt channel 0"); break;
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case TRAP_CODE_FIRQ_1: neorv32_uart_printf("Fast interrupt channel 1"); break;
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case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt channel 2"); break;
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case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt channel 3"); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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zero_gravi |
}
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zero_gravi |
// address
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_inst;
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2 |
zero_gravi |
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zero_gravi |
asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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if ((trap_cause & 0x80000000) == 0) {
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if ((trap_inst & 3) == 3) {
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trap_addr -= 4;
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}
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else {
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trap_addr -= 2;
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}
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zero_gravi |
}
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zero_gravi |
neorv32_uart_printf(" @0x%x, MTVAL=0x%x </RTE>", trap_addr, neorv32_cpu_csr_read(CSR_MTVAL));
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zero_gravi |
}
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/**********************************************************************//**
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* NEORV32 runtime environment: Print hardware configuration information via UART
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**************************************************************************/
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void neorv32_rte_print_hw_config(void) {
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uint32_t tmp;
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int i;
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char c;
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neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n");
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// CPU configuration
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neorv32_uart_printf("\n-- Central Processing Unit --\n");
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// Hart ID
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12 |
zero_gravi |
neorv32_uart_printf("Hart ID: %u\n", neorv32_cpu_csr_read(CSR_MHARTID));
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6 |
zero_gravi |
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12 |
zero_gravi |
// Custom user code
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neorv32_uart_printf("User code: 0x%x\n", SYSINFO_USER_CODE);
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6 |
zero_gravi |
// HW version
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neorv32_uart_printf("Hardware version: ");
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260 |
12 |
zero_gravi |
neorv32_rte_print_hw_version();
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zero_gravi |
neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID));
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// CPU architecture
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neorv32_uart_printf("Architecture: ");
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tmp = neorv32_cpu_csr_read(CSR_MISA);
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|
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tmp = (tmp >> 30) & 0x03;
|
267 |
|
|
if (tmp == 0) {
|
268 |
|
|
neorv32_uart_printf("unknown");
|
269 |
|
|
}
|
270 |
|
|
if (tmp == 1) {
|
271 |
|
|
neorv32_uart_printf("RV32");
|
272 |
|
|
}
|
273 |
|
|
if (tmp == 2) {
|
274 |
|
|
neorv32_uart_printf("RV64");
|
275 |
|
|
}
|
276 |
|
|
if (tmp == 3) {
|
277 |
|
|
neorv32_uart_printf("RV128");
|
278 |
|
|
}
|
279 |
|
|
|
280 |
|
|
// CPU extensions
|
281 |
|
|
neorv32_uart_printf("\nCPU extensions: ");
|
282 |
|
|
tmp = neorv32_cpu_csr_read(CSR_MISA);
|
283 |
|
|
for (i=0; i<26; i++) {
|
284 |
|
|
if (tmp & (1 << i)) {
|
285 |
|
|
c = (char)('A' + i);
|
286 |
|
|
neorv32_uart_putc(c);
|
287 |
|
|
neorv32_uart_putc(' ');
|
288 |
|
|
}
|
289 |
|
|
}
|
290 |
|
|
neorv32_uart_printf("(0x%x)\n", tmp);
|
291 |
|
|
|
292 |
|
|
|
293 |
15 |
zero_gravi |
// Misc
|
294 |
|
|
neorv32_uart_printf("\n-- System --\n");
|
295 |
|
|
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
|
296 |
|
|
|
297 |
|
|
|
298 |
6 |
zero_gravi |
// Memory configuration
|
299 |
15 |
zero_gravi |
neorv32_uart_printf("\n-- Processor Memory Configuration --\n");
|
300 |
6 |
zero_gravi |
|
301 |
12 |
zero_gravi |
uint32_t size = SYSINFO_ISPACE_SIZE;
|
302 |
|
|
uint32_t base = SYSINFO_ISPACE_BASE;
|
303 |
6 |
zero_gravi |
neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base);
|
304 |
|
|
neorv32_uart_printf("Internal IMEM: ");
|
305 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM));
|
306 |
6 |
zero_gravi |
neorv32_uart_printf("Internal IMEM as ROM: ");
|
307 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM));
|
308 |
6 |
zero_gravi |
|
309 |
12 |
zero_gravi |
size = SYSINFO_DSPACE_SIZE;
|
310 |
|
|
base = SYSINFO_DSPACE_BASE;
|
311 |
6 |
zero_gravi |
neorv32_uart_printf("Data memory: %u bytes @ 0x%x\n", size, base);
|
312 |
|
|
neorv32_uart_printf("Internal DMEM: ");
|
313 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM));
|
314 |
6 |
zero_gravi |
|
315 |
|
|
neorv32_uart_printf("Bootloader: ");
|
316 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
|
317 |
6 |
zero_gravi |
|
318 |
|
|
neorv32_uart_printf("External interface: ");
|
319 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
|
320 |
6 |
zero_gravi |
|
321 |
|
|
// peripherals
|
322 |
15 |
zero_gravi |
neorv32_uart_printf("\n-- Processor Peripherals --\n");
|
323 |
|
|
|
324 |
12 |
zero_gravi |
tmp = SYSINFO_FEATURES;
|
325 |
6 |
zero_gravi |
|
326 |
|
|
neorv32_uart_printf("GPIO: ");
|
327 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
|
328 |
6 |
zero_gravi |
|
329 |
|
|
neorv32_uart_printf("MTIME: ");
|
330 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME));
|
331 |
6 |
zero_gravi |
|
332 |
|
|
neorv32_uart_printf("UART: ");
|
333 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART));
|
334 |
6 |
zero_gravi |
|
335 |
|
|
neorv32_uart_printf("SPI: ");
|
336 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI));
|
337 |
6 |
zero_gravi |
|
338 |
|
|
neorv32_uart_printf("TWI: ");
|
339 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI));
|
340 |
6 |
zero_gravi |
|
341 |
|
|
neorv32_uart_printf("PWM: ");
|
342 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM));
|
343 |
6 |
zero_gravi |
|
344 |
|
|
neorv32_uart_printf("WDT: ");
|
345 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT));
|
346 |
6 |
zero_gravi |
|
347 |
|
|
neorv32_uart_printf("TRNG: ");
|
348 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
|
349 |
6 |
zero_gravi |
|
350 |
|
|
neorv32_uart_printf("DEVNULL: ");
|
351 |
12 |
zero_gravi |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_DEVNULL));
|
352 |
6 |
zero_gravi |
}
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
/**********************************************************************//**
|
356 |
|
|
* NEORV32 runtime environment: Private function to print true or false.
|
357 |
|
|
* @note This function is used by neorv32_rte_print_hw_config(void) only.
|
358 |
|
|
*
|
359 |
|
|
* @param[in] state Print TRUE when !=0, print FALSE when 0
|
360 |
|
|
**************************************************************************/
|
361 |
|
|
static void __neorv32_rte_print_true_false(int state) {
|
362 |
|
|
|
363 |
|
|
if (state) {
|
364 |
|
|
neorv32_uart_printf("True\n");
|
365 |
|
|
}
|
366 |
2 |
zero_gravi |
else {
|
367 |
6 |
zero_gravi |
neorv32_uart_printf("False\n");
|
368 |
2 |
zero_gravi |
}
|
369 |
6 |
zero_gravi |
}
|
370 |
2 |
zero_gravi |
|
371 |
|
|
|
372 |
6 |
zero_gravi |
/**********************************************************************//**
|
373 |
12 |
zero_gravi |
* NEORV32 runtime environment: Function to show the processor version in human-readable format.
|
374 |
6 |
zero_gravi |
**************************************************************************/
|
375 |
12 |
zero_gravi |
void neorv32_rte_print_hw_version(void) {
|
376 |
6 |
zero_gravi |
|
377 |
|
|
uint32_t i;
|
378 |
|
|
char tmp, cnt;
|
379 |
|
|
uint32_t version = neorv32_cpu_csr_read(CSR_MIMPID);
|
380 |
|
|
|
381 |
|
|
for (i=0; i<4; i++) {
|
382 |
|
|
|
383 |
|
|
tmp = (char)(version >> (24 - 8*i));
|
384 |
|
|
|
385 |
|
|
// serial division
|
386 |
|
|
cnt = 0;
|
387 |
|
|
while (tmp >= 10) {
|
388 |
|
|
tmp = tmp - 10;
|
389 |
|
|
cnt++;
|
390 |
|
|
}
|
391 |
|
|
|
392 |
|
|
if (cnt) {
|
393 |
|
|
neorv32_uart_putc('0' + cnt);
|
394 |
|
|
}
|
395 |
|
|
neorv32_uart_putc('0' + tmp);
|
396 |
|
|
if (i < 3) {
|
397 |
|
|
neorv32_uart_putc('.');
|
398 |
|
|
}
|
399 |
|
|
}
|
400 |
2 |
zero_gravi |
}
|
401 |
11 |
zero_gravi |
|
402 |
|
|
|
403 |
|
|
/**********************************************************************//**
|
404 |
|
|
* NEORV32 runtime environment: Print project credits
|
405 |
|
|
**************************************************************************/
|
406 |
|
|
void neorv32_rte_print_credits(void) {
|
407 |
|
|
|
408 |
|
|
neorv32_uart_print("\n\nThe NEORV32 Processor Project\n"
|
409 |
|
|
"by Stephan Nolting\n"
|
410 |
|
|
"https://github.com/stnolting/neorv32\n"
|
411 |
|
|
"made in Hannover, Germany\n\n");
|
412 |
|
|
}
|
413 |
|
|
|