OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_spi.c] - Blame information for rev 22

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 zero_gravi
// #################################################################################################
2 10 zero_gravi
// # << NEORV32: neorv32_spi.c - Serial Peripheral Interface Controller (SPI) HW Driver >>         #
3 2 zero_gravi
// # ********************************************************************************************* #
4
// # BSD 3-Clause License                                                                          #
5
// #                                                                                               #
6
// # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
7
// #                                                                                               #
8
// # Redistribution and use in source and binary forms, with or without modification, are          #
9
// # permitted provided that the following conditions are met:                                     #
10
// #                                                                                               #
11
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12
// #    conditions and the following disclaimer.                                                   #
13
// #                                                                                               #
14
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15
// #    conditions and the following disclaimer in the documentation and/or other materials        #
16
// #    provided with the distribution.                                                            #
17
// #                                                                                               #
18
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
19
// #    endorse or promote products derived from this software without specific prior written      #
20
// #    permission.                                                                                #
21
// #                                                                                               #
22
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
31
// # ********************************************************************************************* #
32
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33
// #################################################################################################
34
 
35
 
36
/**********************************************************************//**
37
 * @file neorv32_spi.c
38
 * @author Stephan Nolting
39 10 zero_gravi
 * @brief Serial peripheral interface controller (SPI) HW driver source file.
40 2 zero_gravi
 *
41
 * @note These functions should only be used if the SPI unit was synthesized (IO_SPI_USE = true).
42
 **************************************************************************/
43
 
44
#include "neorv32.h"
45
#include "neorv32_spi.h"
46
 
47
 
48
/**********************************************************************//**
49
 * Check if SPI unit was synthesized.
50
 *
51
 * @return 0 if SPI was not synthesized, 1 if SPI is available.
52
 **************************************************************************/
53
int neorv32_spi_available(void) {
54
 
55 12 zero_gravi
  if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_SPI)) {
56 2 zero_gravi
    return 1;
57
  }
58
  else {
59
    return 0;
60
  }
61
}
62
 
63
 
64
/**********************************************************************//**
65
 * Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CT_enum.
66
 *
67
 * @param[in] prsc Clock prescaler select (0..7).  See #NEORV32_CLOCK_PRSC_enum.
68
 * @param[in] clk_polarity Idle clock polarity (0, 1).
69
 * @param[in] dir Shift direction (0: MSB first, 1: LSB first).
70
 * @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
71
 * @param[in] irq_en Enable transfer-done interrupt when 1.
72
 **************************************************************************/
73
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t dir, uint8_t data_size, uint8_t irq_en) {
74
 
75
  SPI_CT = 0; // reset
76
 
77
  uint32_t ct_enable = 1;
78
  ct_enable = ct_enable << SPI_CT_EN;
79
 
80
  uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
81
  ct_prsc = ct_prsc << SPI_CT_PRSC0;
82
 
83
  uint32_t ct_polarity = (uint32_t)(clk_polarity & 0x01);
84
  ct_polarity = ct_polarity << SPI_CT_CPHA;
85
 
86
  uint32_t ct_dir = (uint32_t)(dir & 0x01);
87
  ct_dir = ct_dir << SPI_CT_DIR;
88
 
89
  uint32_t ct_size = (uint32_t)(data_size & 0x03);
90
  ct_size = ct_size << SPI_CT_SIZE0;
91
 
92
  uint32_t ct_irq = (uint32_t)(irq_en & 0x01);
93
  ct_irq = ct_irq << SPI_CT_IRQ_EN;
94
 
95
  SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_dir | ct_size | ct_irq;
96
}
97
 
98
 
99
/**********************************************************************//**
100
 * Disable and SPI controller.
101
 **************************************************************************/
102
void neorv32_spi_disable(void) {
103
 
104
  SPI_CT &= ~((uint32_t)(1 << SPI_CT_EN));
105
}
106
 
107
 
108
/**********************************************************************//**
109
 * Activate SPI chip select signal.
110
 *
111
 * @note The chip select output lines are LOW when activated.
112
 *
113
 * @param cs Chip select line to activate (0..7).
114
 **************************************************************************/
115
void neorv32_spi_cs_en(uint8_t cs) {
116
 
117
  uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));
118
  cs_mask = cs_mask << SPI_CT_CS0;
119
  SPI_CT |= cs_mask;
120
}
121
 
122
 
123
/**********************************************************************//**
124
 * Deactivate SPI chip select signal.
125
 *
126
 * @note The chip select output lines are HIGH when deactivated.
127
 *
128
 * @param cs Chip select line to deactivate (0..7).
129
 **************************************************************************/
130
void neorv32_spi_cs_dis(uint8_t cs) {
131
 
132
  uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));
133
  cs_mask = cs_mask << SPI_CT_CS0;
134
  SPI_CT &= ~cs_mask;
135
}
136
 
137
 
138
/**********************************************************************//**
139
 * Initiate SPI transfer.
140
 *
141
 * @note This function is blocking.
142
 *
143
 * @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
144
 * @return Receive data (8/16/24/32-bit, LSB-aligned).
145
 **************************************************************************/
146
uint32_t neorv32_spi_trans(uint32_t tx_data) {
147
 
148
  SPI_DATA = tx_data; // trigger transfer
149
  while((SPI_CT & (1<<SPI_CT_BUSY)) != 0); // wait for current transfer to finish
150
 
151
  return SPI_DATA;
152
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.