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[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_spi.c] - Blame information for rev 52

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// #################################################################################################
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// # << NEORV32: neorv32_spi.c - Serial Peripheral Interface Controller (SPI) HW Driver >>         #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License                                                                          #
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// #                                                                                               #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
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// #                                                                                               #
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// # Redistribution and use in source and binary forms, with or without modification, are          #
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// # permitted provided that the following conditions are met:                                     #
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// #                                                                                               #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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// #    conditions and the following disclaimer.                                                   #
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// #                                                                                               #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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// #    conditions and the following disclaimer in the documentation and/or other materials        #
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// #    provided with the distribution.                                                            #
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// #                                                                                               #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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// #    endorse or promote products derived from this software without specific prior written      #
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// #    permission.                                                                                #
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// #                                                                                               #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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 * @file neorv32_spi.c
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 * @author Stephan Nolting
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 * @brief Serial peripheral interface controller (SPI) HW driver source file.
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 *
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 * @note These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true).
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 **************************************************************************/
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#include "neorv32.h"
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#include "neorv32_spi.h"
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/**********************************************************************//**
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 * Check if SPI unit was synthesized.
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 *
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 * @return 0 if SPI was not synthesized, 1 if SPI is available.
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 **************************************************************************/
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int neorv32_spi_available(void) {
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  if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_SPI)) {
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    return 1;
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  }
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  else {
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    return 0;
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  }
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}
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/**********************************************************************//**
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 * Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CT_enum.
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 *
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 * @param[in] prsc Clock prescaler select (0..7).  See #NEORV32_CLOCK_PRSC_enum.
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 * @param[in] clk_polarity Idle clock polarity (0, 1).
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 * @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
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 **************************************************************************/
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void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size) {
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  SPI_CT = 0; // reset
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  uint32_t ct_enable = 1;
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  ct_enable = ct_enable << SPI_CT_EN;
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  uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
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  ct_prsc = ct_prsc << SPI_CT_PRSC0;
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  uint32_t ct_polarity = (uint32_t)(clk_polarity & 0x01);
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  ct_polarity = ct_polarity << SPI_CT_CPHA;
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  uint32_t ct_size = (uint32_t)(data_size & 0x03);
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  ct_size = ct_size << SPI_CT_SIZE0;
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  SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_size;
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}
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/**********************************************************************//**
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 * Disable SPI controller.
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 **************************************************************************/
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void neorv32_spi_disable(void) {
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  SPI_CT &= ~((uint32_t)(1 << SPI_CT_EN));
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}
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/**********************************************************************//**
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 * Activate SPI chip select signal.
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 *
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 * @note The chip select output lines are LOW when activated.
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 *
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 * @param cs Chip select line to activate (0..7).
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 **************************************************************************/
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void neorv32_spi_cs_en(uint8_t cs) {
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  uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));
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  cs_mask = cs_mask << SPI_CT_CS0;
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  SPI_CT |= cs_mask;
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}
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/**********************************************************************//**
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 * Deactivate SPI chip select signal.
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 *
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 * @note The chip select output lines are HIGH when deactivated.
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 *
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 * @param cs Chip select line to deactivate (0..7).
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 **************************************************************************/
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void neorv32_spi_cs_dis(uint8_t cs) {
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  uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));
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  cs_mask = cs_mask << SPI_CT_CS0;
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  SPI_CT &= ~cs_mask;
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}
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/**********************************************************************//**
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 * Initiate SPI transfer.
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 *
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 * @warning The SPI always sends MSB first.
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 *
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 * @note This function is blocking.
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 *
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 * @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
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 * @return Receive data (8/16/24/32-bit, LSB-aligned).
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 **************************************************************************/
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uint32_t neorv32_spi_trans(uint32_t tx_data) {
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  SPI_DATA = tx_data; // trigger transfer
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  while((SPI_CT & (1<<SPI_CT_BUSY)) != 0); // wait for current transfer to finish
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  return SPI_DATA;
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}
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/**********************************************************************//**
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 * Check if SPI transceiver is busy.
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 *
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 * @note This function is blocking.
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 *
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 * @return 0 if idle, 1 if busy
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 **************************************************************************/
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int neorv32_spi_busy(void) {
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  if ((SPI_CT & (1<<SPI_CT_BUSY)) != 0) {
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    return 1;
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  }
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  return 0;
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}

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