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[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_spi.c] - Blame information for rev 66

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// #################################################################################################
// # << NEORV32: neorv32_spi.c - Serial Peripheral Interface Controller (SPI) HW Driver >>         #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
// #                                                                                               #
// # Redistribution and use in source and binary forms, with or without modification, are          #
// # permitted provided that the following conditions are met:                                     #
// #                                                                                               #
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
// #    conditions and the following disclaimer.                                                   #
// #                                                                                               #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
// #    conditions and the following disclaimer in the documentation and/or other materials        #
// #    provided with the distribution.                                                            #
// #                                                                                               #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
// #    endorse or promote products derived from this software without specific prior written      #
// #    permission.                                                                                #
// #                                                                                               #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
 * @file neorv32_spi.c
 * @author Stephan Nolting
 * @brief Serial peripheral interface controller (SPI) HW driver source file.
 *
 * @note These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true).
 **************************************************************************/
 
#include "neorv32.h"
#include "neorv32_spi.h"
 
 
/**********************************************************************//**
 * Check if SPI unit was synthesized.
 *
 * @return 0 if SPI was not synthesized, 1 if SPI is available.
 **************************************************************************/
int neorv32_spi_available(void) {
 
  if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_SPI)) {
    return 1;
  }
  else {
    return 0;
  }
}
 
 
/**********************************************************************//**
 * Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CTRL_enum.
 *
 * @param[in] prsc Clock prescaler select (0..7).  See #NEORV32_CLOCK_PRSC_enum.
 * @param[in] clk_phase Clock phase (0=sample on rising edge, 1=sample on falling edge).
 * @param[in] clk_polarity Clock polarity (when idle).
 * @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
 **************************************************************************/
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_phase, uint8_t clk_polarity, uint8_t data_size) {
 
  NEORV32_SPI.CTRL = 0; // reset
 
  uint32_t ct_enable = 1;
  ct_enable = ct_enable << SPI_CTRL_EN;
 
  uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
  ct_prsc = ct_prsc << SPI_CTRL_PRSC0;
 
  uint32_t ct_phase = (uint32_t)(clk_phase & 0x01);
  ct_phase = ct_phase << SPI_CTRL_CPHA;
 
  uint32_t ct_polarity = (uint32_t)(clk_polarity & 0x01);
  ct_polarity = ct_polarity << SPI_CTRL_CPOL;
 
  uint32_t ct_size = (uint32_t)(data_size & 0x03);
  ct_size = ct_size << SPI_CTRL_SIZE0;
 
  NEORV32_SPI.CTRL = ct_enable | ct_prsc | ct_phase | ct_polarity | ct_size;
}
 
 
/**********************************************************************//**
 * Disable SPI controller.
 **************************************************************************/
void neorv32_spi_disable(void) {
 
  NEORV32_SPI.CTRL &= ~((uint32_t)(1 << SPI_CTRL_EN));
}
 
 
/**********************************************************************//**
 * Enable SPI controller.
 **************************************************************************/
void neorv32_spi_enable(void) {
 
  NEORV32_SPI.CTRL |= ((uint32_t)(1 << SPI_CTRL_EN));
}
 
 
/**********************************************************************//**
 * Activate SPI chip select signal.
 *
 * @note The chip select output lines are LOW when activated.
 *
 * @param cs Chip select line to activate (0..7).
 **************************************************************************/
void neorv32_spi_cs_en(uint8_t cs) {
 
  uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));
  cs_mask = cs_mask << SPI_CTRL_CS0;
  NEORV32_SPI.CTRL |= cs_mask;
}
 
 
/**********************************************************************//**
 * Deactivate SPI chip select signal.
 *
 * @note The chip select output lines are HIGH when deactivated.
 *
 * @param cs Chip select line to deactivate (0..7).
 **************************************************************************/
void neorv32_spi_cs_dis(uint8_t cs) {
 
  uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));
  cs_mask = cs_mask << SPI_CTRL_CS0;
  NEORV32_SPI.CTRL &= ~cs_mask;
}
 
 
/**********************************************************************//**
 * Initiate SPI transfer.
 *
 * @note This function is blocking.
 *
 * @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
 * @return Receive data (8/16/24/32-bit, LSB-aligned).
 **************************************************************************/
uint32_t neorv32_spi_trans(uint32_t tx_data) {
 
  NEORV32_SPI.DATA = tx_data; // trigger transfer
  while((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0); // wait for current transfer to finish
 
  return NEORV32_SPI.DATA;
}
 
 
/**********************************************************************//**
 * Initiate SPI TX transfer (non-blocking).
 *
 * @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
 **************************************************************************/
void neorv32_spi_put_nonblocking(uint32_t tx_data) {
 
  NEORV32_SPI.DATA = tx_data; // trigger transfer
}
 
 
/**********************************************************************//**
 * Get SPI RX data (non-blocking).
 *
 * @return Receive data (8/16/24/32-bit, LSB-aligned).
 **************************************************************************/
uint32_t neorv32_spi_get_nonblocking(void) {
 
  return NEORV32_SPI.DATA;
}
 
 
/**********************************************************************//**
 * Check if SPI transceiver is busy.
 *
 * @return 0 if idle, 1 if busy
 **************************************************************************/
int neorv32_spi_busy(void) {
 
  if ((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0) {
    return 1;
  }
  else {
    return 0;
  }
}

Line No.	Rev	Author	Line
1	2	zero_gravi	`// #################################################################################################`
2	10	zero_gravi	`// # << NEORV32: neorv32_spi.c - Serial Peripheral Interface Controller (SPI) HW Driver >> #`
3	2	zero_gravi	`// # ********************************************************************************************* #`
4			`// # BSD 3-Clause License #`
5			`// # #`
6	44	zero_gravi	`// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #`
7	2	zero_gravi	`// # #`
8			`// # Redistribution and use in source and binary forms, with or without modification, are #`
9			`// # permitted provided that the following conditions are met: #`
10			`// # #`
11			`// # 1. Redistributions of source code must retain the above copyright notice, this list of #`
12			`// # conditions and the following disclaimer. #`
13			`// # #`
14			`// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #`
15			`// # conditions and the following disclaimer in the documentation and/or other materials #`
16			`// # provided with the distribution. #`
17			`// # #`
18			`// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #`
19			`// # endorse or promote products derived from this software without specific prior written #`
20			`// # permission. #`
21			`// # #`
22			`// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #`
23			`// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #`
24			`// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #`
25			`// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #`
26			`// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #`
27			`// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #`
28			`// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #`
29			`// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #`
30			`// # OF THE POSSIBILITY OF SUCH DAMAGE. #`
31			`// # ********************************************************************************************* #`
32			`// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #`
33			`// #################################################################################################`
34
35
36			`/********************************************************************//`
37			`* @file neorv32_spi.c`
38			`* @author Stephan Nolting`
39	10	zero_gravi	`* @brief Serial peripheral interface controller (SPI) HW driver source file.`
40	2	zero_gravi	`*`
41	44	zero_gravi	`* @note These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true).`
42	2	zero_gravi	`**************************************************************************/`
43
44			`#include "neorv32.h"`
45			`#include "neorv32_spi.h"`
46
47
48			`/********************************************************************//`
49			`* Check if SPI unit was synthesized.`
50			`*`
51			`* @return 0 if SPI was not synthesized, 1 if SPI is available.`
52			`**************************************************************************/`
53			`int neorv32_spi_available(void) {`
54
55	64	zero_gravi	`if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_SPI)) {`
56	2	zero_gravi	`return 1;`
57			`}`
58			`else {`
59			`return 0;`
60			`}`
61			`}`
62
63
64			`/********************************************************************//`
65	64	zero_gravi	`* Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CTRL_enum.`
66	2	zero_gravi	`*`
67			`* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.`
68	65	zero_gravi	`* @param[in] clk_phase Clock phase (0=sample on rising edge, 1=sample on falling edge).`
69			`* @param[in] clk_polarity Clock polarity (when idle).`
70	2	zero_gravi	`* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).`
71			`**************************************************************************/`
72	65	zero_gravi	`void neorv32_spi_setup(uint8_t prsc, uint8_t clk_phase, uint8_t clk_polarity, uint8_t data_size) {`
73	2	zero_gravi
74	64	zero_gravi	`NEORV32_SPI.CTRL = 0; // reset`
75	2	zero_gravi
76			`uint32_t ct_enable = 1;`
77	64	zero_gravi	`ct_enable = ct_enable << SPI_CTRL_EN;`
78	2	zero_gravi
79			`uint32_t ct_prsc = (uint32_t)(prsc & 0x07);`
80	64	zero_gravi	`ct_prsc = ct_prsc << SPI_CTRL_PRSC0;`
81	2	zero_gravi
82	65	zero_gravi	`uint32_t ct_phase = (uint32_t)(clk_phase & 0x01);`
83			`ct_phase = ct_phase << SPI_CTRL_CPHA;`
84
85	2	zero_gravi	`uint32_t ct_polarity = (uint32_t)(clk_polarity & 0x01);`
86	65	zero_gravi	`ct_polarity = ct_polarity << SPI_CTRL_CPOL;`
87	2	zero_gravi
88			`uint32_t ct_size = (uint32_t)(data_size & 0x03);`
89	64	zero_gravi	`ct_size = ct_size << SPI_CTRL_SIZE0;`
90	2	zero_gravi
91	65	zero_gravi	`NEORV32_SPI.CTRL = ct_enable \| ct_prsc \| ct_phase \| ct_polarity \| ct_size;`
92	2	zero_gravi	`}`
93
94
95			`/********************************************************************//`
96	52	zero_gravi	`* Disable SPI controller.`
97	2	zero_gravi	`**************************************************************************/`
98			`void neorv32_spi_disable(void) {`
99
100	64	zero_gravi	`NEORV32_SPI.CTRL &= ~((uint32_t)(1 << SPI_CTRL_EN));`
101	2	zero_gravi	`}`
102
103
104			`/********************************************************************//`
105	61	zero_gravi	`* Enable SPI controller.`
106			`**************************************************************************/`
107			`void neorv32_spi_enable(void) {`
108
109	64	zero_gravi	`NEORV32_SPI.CTRL \|= ((uint32_t)(1 << SPI_CTRL_EN));`
110	61	zero_gravi	`}`
111
112
113			`/********************************************************************//`
114	2	zero_gravi	`* Activate SPI chip select signal.`
115			`*`
116			`* @note The chip select output lines are LOW when activated.`
117			`*`
118			`* @param cs Chip select line to activate (0..7).`
119			`**************************************************************************/`
120			`void neorv32_spi_cs_en(uint8_t cs) {`
121
122			`uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));`
123	64	zero_gravi	`cs_mask = cs_mask << SPI_CTRL_CS0;`
124			`NEORV32_SPI.CTRL \|= cs_mask;`
125	2	zero_gravi	`}`
126
127
128			`/********************************************************************//`
129			`* Deactivate SPI chip select signal.`
130			`*`
131			`* @note The chip select output lines are HIGH when deactivated.`
132			`*`
133			`* @param cs Chip select line to deactivate (0..7).`
134			`**************************************************************************/`
135			`void neorv32_spi_cs_dis(uint8_t cs) {`
136
137			`uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));`
138	64	zero_gravi	`cs_mask = cs_mask << SPI_CTRL_CS0;`
139			`NEORV32_SPI.CTRL &= ~cs_mask;`
140	2	zero_gravi	`}`
141
142
143			`/********************************************************************//`
144			`* Initiate SPI transfer.`
145			`*`
146			`* @note This function is blocking.`
147			`*`
148			`* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).`
149			`* @return Receive data (8/16/24/32-bit, LSB-aligned).`
150			`**************************************************************************/`
151			`uint32_t neorv32_spi_trans(uint32_t tx_data) {`
152
153	64	zero_gravi	`NEORV32_SPI.DATA = tx_data; // trigger transfer`
154			`while((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0); // wait for current transfer to finish`
155	2	zero_gravi
156	64	zero_gravi	`return NEORV32_SPI.DATA;`
157	2	zero_gravi	`}`
158	23	zero_gravi
159
160			`/********************************************************************//`
161	66	zero_gravi	`* Initiate SPI TX transfer (non-blocking).`
162			`*`
163			`* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).`
164			`**************************************************************************/`
165			`void neorv32_spi_put_nonblocking(uint32_t tx_data) {`
166
167			`NEORV32_SPI.DATA = tx_data; // trigger transfer`
168			`}`
169
170
171			`/********************************************************************//`
172			`* Get SPI RX data (non-blocking).`
173			`*`
174			`* @return Receive data (8/16/24/32-bit, LSB-aligned).`
175			`**************************************************************************/`
176			`uint32_t neorv32_spi_get_nonblocking(void) {`
177
178			`return NEORV32_SPI.DATA;`
179			`}`
180
181
182			`/********************************************************************//`
183	23	zero_gravi	`* Check if SPI transceiver is busy.`
184			`*`
185			`* @return 0 if idle, 1 if busy`
186			`**************************************************************************/`
187			`int neorv32_spi_busy(void) {`
188
189	64	zero_gravi	`if ((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0) {`
190	23	zero_gravi	`return 1;`
191			`}`
192	65	zero_gravi	`else {`
193			`return 0;`
194			`}`
195	23	zero_gravi	`}`

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[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_spi.c] - Blame information for rev 66