URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [svd/] [neorv32.svd] - Blame information for rev 73

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  stnolting
  neorv32
  RISC-V
  1.6.4
  The NEORV32 RISC-V Processor
 
  
  
    NEORV32
    r2p0
    little
    true
    true
    false
    false
    true
    true
    0
    false
  
 
  
  8
  32
  32
  read-write
  0x00000000
  0x00000000 
 
  
  
 
    
    
      CFS
      Custom functions subsystem
      CFS
      0xFFFFFE00
 
      CFS_FIRQ1
 
      
        0
        0x80
        registers
      
 
      
        REG0Application-defined0x00
        REG1Application-defined0x04
        REG2Application-defined0x08
        REG3Application-defined0x0C
        REG4Application-defined0x10
        REG5Application-defined0x14
        REG6Application-defined0x18
        REG7Application-defined0x1C
        REG8Application-defined0x20
        REG9Application-defined0x24
        REG10Application-defined0x28
        REG11Application-defined0x2C
        REG12Application-defined0x30
        REG13Application-defined0x34
        REG14Application-defined0x38
        REG15Application-defined0x3C
        REG16Application-defined0x40
        REG17Application-defined0x44
        REG18Application-defined0x48
        REG19Application-defined0x4C
        REG20Application-defined0x50
        REG21Application-defined0x54
        REG22Application-defined0x58
        REG23Application-defined0x5C
        REG24Application-defined0x60
        REG25Application-defined0x64
        REG26Application-defined0x68
        REG27Application-defined0x6C
        REG28Application-defined0x70
        REG29Application-defined0x74
        REG30Application-defined0x78
        REG31Application-defined0x7C
      
    
 
    
    
      PWM
      Pulse-width modulation controller
      PWM
      0xFFFFFE80
 
      
        0
        0x40
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              PWM_CTRL_EN
              [0:0]
              PWM controller enable flag
            
            
              PWM_CTRL_PRSCx
              [3:1]
              Clock prescaler select
            
          
        
        
          DUTY0
          Duty cycle register 0
          0x04
        
        
          DUTY1
          Duty cycle register 1
          0x08
        
        
          DUTY2
          Duty cycle register 2
          0x0C
        
        
          DUTY3
          Duty cycle register 3
          0x10
        
        
          DUTY4
          Duty cycle register 4
          0x14
        
        
          DUTY5
          Duty cycle register 5
          0x18
        
        
          DUTY6
          Duty cycle register 6
          0x1C
        
        
          DUTY7
          Duty cycle register 7
          0x20
        
        
          DUTY8
          Duty cycle register 8
          0x24
        
        
          DUTY9
          Duty cycle register 9
          0x28
        
        
          DUTY10
          Duty cycle register 10
          0x2C
        
        
          DUTY11
          Duty cycle register 11
          0x30
        
        
          DUTY12
          Duty cycle register 12
          0x34
        
        
          DUTY13
          Duty cycle register 13
          0x38
        
        
          DUTY14
          Duty cycle register 14
          0x3C
        
      
    
 
    
    
      SLINK
      Stream link interface
      SLINK
      0xFFFFFEC0
 
      SLINK_RX_FIRQ10
      SLINK_TX_FIRQ11
 
      
        0
        0x40
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              SLINK_CTRL_RX_NUMx
              read-only
              [3:0]
              Number of implemented RX links
            
            
              SLINK_CTRL_TX_NUMx
              read-only
              [7:4]
              Number of implemented TX links
            
            
              SLINK_CTRL_RX_FIFO_Sx
              read-only
              [11:8]
              log2(RX FIFO size)
            
            
              SLINK_CTRL_TX_FIFO_Sx
              read-only
              [15:12]
              log2(TX FIFO size)
            
            
              SLINK_CTRL_EN
              read-write
              [31:31]
              SLINK enable flag
            
          
        
        
          IRQ
          Link interrupt configuration register
          0x08
          
            
              SLINK_IRQ_RX_EN
              [7:0]
              RX link interrupt enable
            
            
              SLINK_IRQ_RX_MODE
              [15:8]
              RX link interrupt mode
            
            
              SLINK_IRQ_TX_EN
              [23:16]
              TX link interrupt enable
            
            
              SLINK_IRQ_TX_MODE
              [31:24]
              TX link interrupt mode
            
          
        
        
          STATUS
          Link status register
          0x10
          
            
              SLINK_STATUS_RX_AVAIL
              [7:0]
              RX link n FIFO is NOT empty (data available)
            
            
              SLINK_STATUS_TX_FREE
              [15:8]
              TX link n FIFO is NOT full (ready to send)
            
            
              SLINK_STATUS_RX_HALF
              [23:16]
              RX link n FIFO fill level is >= half-full
            
            
              SLINK_STATUS_TX_HALF
              [31:24]
              TX link 0 FIFO fill level is > half-full
            
          
        
        
          DATA0
          Link 0 RTX data register
          0x20
        
        
          DATA1
          Link 1 RTX data register
          0x24
        
        
          DATA2
          Link 2 RTX data register
          0x28
        
        
          DATA3
          Link 3 RTX data register
          0x2C
        
        
          DATA4
          Link 4 RTX data register
          0x30
        
        
          DATA5
          Link 5 RTX data register
          0x34
        
        
          DATA6
          Link 6 RTX data register
          0x38
        
        
          DATA7
          Link 7 RTX data register
          0x3C
        
      
    
 
    
    
      XIP
      Execute In Place Module
      CIP
      0xFFFFFF40
 
      
        0
        0x10
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              XIP_CTRL_EN
              [0:0]
              XIP module enable flag
            
            
              XIP_CTRL_PRSC
              [3:1]
              SPI clock prescaler select
            
            
              XIP_CTRL_CPOL
              [4:4]
              SPI clock (idle) polarity
            
            
              XIP_CTRL_CPHA
              [5:5]
              SPI clock phase
            
            
              XIP_CTRL_SPI_NBYTES
              [9:6]
              Number of bytes in SPI transmission
            
            
              XIP_CTRL_XIP_EN
              [10:10]
              XIP mode enable
            
            
              XIP_CTRL_XIP_ABYTES
              [12:11]
              Number of XIP address bytes (minus 1)
            
            
              XIP_CTRL_RD_CMD
              [20:13]
              SPI flash read command
            
            
              XIP_CTRL_XIP_PAGE
              [24:21]
              XIP memory page
            
            
              XIP_CTRL_SPI_CSEN
              [25:25]
              SPI chip-select enable
            
            
              XIP_CTRL_HIGHSPEED
              [26:26]
              SPI high-speed mode enable (ignoring XIP_CTRL_PRSC)
            
            
              XIP_CTRL_PHY_BUSY
              [30:30]
              read-only
              SPI PHY busy
            
            
              XIP_CTRL_XIP_BUSY
              [31:31]
              read-only
              XIP access in progress
            
          
        
        
          DATA_LO
          Direct SPI access - data register low
          0x08
        
        
          DATA_HI
          Direct SPI access - data register high
          0x0C
        
      
    
 
    
    
      GPTMR
      General purpose timer
      GPTMR
      0xFFFFFF60
 
      GPTMR_FIRQ12
 
      
        0
        0x10
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              GPTMR_CTRL_EN
              [0:0]
              Timer enable flag
            
            
              GPTMR_CTRL_PRSC
              [3:1]
              Clock prescaler select
            
            
              GPTMR_CTRL_MODE
              [4:4]
              Timer mode: 0=single-shot mode, 1=continuous mode
            
          
        
        
          THRES
          Threshold register
          0x04
        
        
          COUNT
          Counter register
          0x08
        
      
    
 
    
    
      BUSKEEPER
      Bus keeper
      BUSKEEPER
      0xFFFFFF7C
 
      
        0
        0x04
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              BUSKEEPER_ERR_TYPE
              [0:0]
              read-only
              Bus error type: 0=device error, 1=access timeout
            
            
              BUSKEEPER_ERR_FLAG
              [31:31]
              Sticky error flag, clears after read or write access
            
          
        
      
    
 
    
    
      XIRQ
      External interrupts controller
      XIRQ
      0xFFFFFF80
 
      XIRQ_FIRQ8
 
      
        0
        0x10
        registers
      
 
      
        
          IER
          IRQ input enable register
          0x00
        
        
          IPR
          IRQ pending/ack/clear register
          0x04
        
        
          SCR
          IRQ source register
          0x08
        
      
    
 
    
    
      MTIME
      Machine timer
      MTIME
      0xFFFFFF90
 
      
        0
        0x10
        registers
      
 
      
        
          TIME_LO
          System time register - low
          0x00
        
        
          TIME_HI
          System time register - high
          0x04
        
        
          TIMECMP_LO
          Time compare register - low
          0x08
        
        
          TIMECMP_HI
          Time compare register - high
          0x0C
        
      
    
 
    
    
      UART0
      Primary universal asynchronous receiver and transmitter
      UART0
      0xFFFFFFA0
 
      UART0_RX_FIRQ2
      UART0_TX_FIRQ3
 
      
        0
        0x08
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              UART_CTRL_BAUD
              [11:0]
              Baud rate divisor
            
            
              UART_CTRL_SIM_MODE
              [12:12]
              Simulation output override enable, for use in simulation only
            
            
              UART_CTRL_RX_EMPTY
              [13:13]
              read-only
              RX FIFO is empty
            
            
              UART_CTRL_RX_HALF
              [14:14]
              read-only
              RX FIFO is at least half-full
            
            
              UART_CTRL_RX_FULL
              [15:15]
              read-only
              RX FIFO is full
            
            
              UART_CTRL_TX_EMPTY
              [16:16]
              read-only
              TX FIFO is empty
            
            
              UART_CTRL_TX_HALF
              [17:17]
              read-only
              TX FIFO is at least half-full
            
            
              UART_CTRL_TX_FULL
              [18:18]
              read-only
              TX FIFO is full
            
            
              UART_CTRL_RTS_EN
              [20:20]
              Enable hardware flow control: Assert RTS output if UART.RX is ready to receive
            
            
              UART_CTRL_CTS_EN
              [21:21]
              Enable hardware flow control: UART.TX starts sending only if CTS input is asserted
            
            
              UART_CTRL_PMODE0
              [22:22]
              Parity configuration (0=even; 1=odd)
            
            
              UART_CTRL_PMODE1
              [23:23]
              Parity bit enabled when set
            
            
              UART_CTRL_PRSC
              [26:24]
              Clock prescaler select
            
            
              UART_CTRL_CTS
              [27:27]
              read-only
              current state of CTS input
            
            
              UART_CTRL_EN
              [28:28]
              UART enable flag
            
            
              UART_CTRL_RX_IRQ
              [29:29]
              RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty
            
            
              UART_CTRL_TX_IRQ
              [30:30]
              TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full
            
            
              UART_CTRL_TX_BUSY
              [31:31]
              read-only
              Transmitter is busy when set
            
          
        
        
          DATA
          RX/TX data register
          0x04
          
            
              UART_DATA
              [7:0]
              Receive/transmit data
            
            
              UART_DATA_PERR
              [28:28]
              read-only
              RX parity error detected when set
            
            
              UART_DATA_FERR
              [29:29]
              read-only
              RX frame error (no valid stop bit) detected when set
            
            
              UART_DATA_OVERR
              [30:30]
              read-only
              RX parity error detected when set
            
            
              UART_DATA_AVAIL
              [31:31]
              read-only
              RX data available when set
            
          
        
      
    
 
    
    
      UART1
      Secondary universal asynchronous receiver and transmitter
      UART1
      0xFFFFFFD0
 
      UART1_RX_FIRQ4
      UART1_TX_FIRQ5
 
      
        0
        0x08
        registers
      
 
    
 
    
    
      SPI
      Serial peripheral interface controller
      SPI
      0xFFFFFFA8
 
      SPI_FIRQ6
 
      
        0
        0x08
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              SPI_CTRL_CS
              [7:0]
              Direct chip select line
            
            
              SPI_CTRL_EN
              [8:8]
              SPI enable flag
            
            
              SPI_CTRL_CPHA
              [9:9]
              Clock phase
            
            
              SPI_CTRL_PRSC
              [12:10]
              Clock prescaler select
            
            
              SPI_CTRL_SIZE
              [14:13]
              Data transfer size
            
            
              SPI_CTRL_CPOL
              [15:15]
              Clock polarity
            
            
              SPI_CTRL_HIGHSPEED
              [16:16]
              SPI high-speed mode enable (ignoring SPI_CTRL_PRSC)
            
            
              SPI_CTRL_BUSY
              [31:31]
              read-only
              SPI busy flag
            
          
        
        
          DATA
          RX/TX data register
          0x04
        
      
    
 
    
    
      TWI
      Two-wire interface controller
      SPI
      0xFFFFFFB0
 
      TWI_FIRQ7
 
      
        0
        0x08
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              TWI_CTRL_EN
              [0:0]
              TWI enable flag
            
            
              TWI_CTRL_START
              [1:1]
              Generate START condition, auto-clears
            
            
              TWI_CTRL_STOP
              [2:2]
              Generate STOP condition, auto-clears
            
            
              TWI_CTRL_PRSC
              [5:3]
              Clock prescaler select
            
            
              TWI_CTRL_MACK
              [6:6]
              Generate ACK by controller for each transmission
            
            
              TWI_CTRL_ACK
              [30:30]
              read-only
              ACK received when set
            
            
              TWI_CTRL_BUSY
              [31:31]
              read-only
              Transfer in progress, busy flag
            
          
        
        
          DATA
          RX/TX data register
          0x04
          
            
              TWI_DATA
              [7:0]
              RX/TX data
            
          
        
      
    
 
    
    
      TRNG
      True random number generator
      TRNG
      0xFFFFFFB8
 
      
        0
        0x04
        registers
      
 
      
        
          CTRL
          Control and data register
          0x00
          
            
              TRNG_CTRL_DATA
              [7:0]
              read-only
              Random data
            
            
              TRNG_CTRL_EN
              [30:30]
              TRNG enable flag
            
            
              TRNG_CTRL_VALID
              [31:31]
              read-only
              Random data output valid
            
          
        
      
    
 
    
    
      WDT
      Watchdog timer
      WDT
      0xFFFFFFBC
 
      WDT_FIRQ0
 
      
        0
        0x04
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              WDT_CTRL_EN
              [0:0]
              WDT enable flag
            
            
              WDT_CTRL_CLK_SEL
              [3:1]
              Clock prescaler select
            
            
              WDT_CTRL_MODE
              [4:4]
              Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset
            
            
              WDT_CTRL_RCAUSE
              [5:5]
              read-only
              Cause of last system reset: 0=external reset, 1=watchdog
            
            
              WDT_CTRL_RESET
              [6:6]
              Reset WDT counter when set, auto-clears
            
            
              WDT_CTRL_FORCE
              [7:7]
              Force WDT action, auto-clears
            
            
              WDT_CTRL_LOCK
              [8:8]
              Lock write access to control register, clears on reset (HW or WDT) only
            
            
              WDT_CTRL_DBEN
              [9:9]
              Allow WDT to continue operation even when in debug mode
            
            
              WDT_CTRL_HALF
              [10:10]
              read-only
              Set if at least half of the max. timeout counter value has been reached
            
          
        
      
    
 
    
    
      GPIO
      General purpose input/output port
      GPIO
      0xFFFFFFc0
 
      
        0
        0x10
        registers
      
 
      
        
          INPUT_LO
          Parallel input register - low
          0x00
          read-only
        
        
          INPUT_HI
          Parallel input register - high
          0x04
          read-only
        
        
          OUTPUT_LO
          Parallel output register - low
          0x08
        
        
          OUTPUT_HI
          Parallel output register - high
          0x0C
        
      
    
 
    
    
      NEOLED
      Smart LED hardware interface
      NEOLED
      0xFFFFFFD8
 
      NEOLED_FIRQ9
 
      
        0
        0x08
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              NEOLED_CTRL_EN
              [0:0]
              NEOLED enable flag
            
            
              NEOLED_CTRL_MODE
              [1:1]
              TX mode (0=24-bit, 1=32-bit)
            
            
              NEOLED_CTRL_STROBE
              [2:2]
              Strobe (0=send normal data, 1=send RESET command on data write)
            
            
              NEOLED_CTRL_PRSC
              [5:3]
              Clock prescaler select
            
            
              NEOLED_CTRL_BUFS
              [9:6]
              read-only
              log2(tx buffer size)
            
            
              NEOLED_CTRL_T_TOT
              [14:10]
              pulse-clock ticks per total period bit
            
            
              NEOLED_CTRL_T_ZERO_H
              [19:15]
              pulse-clock ticks per ZERO high-time
            
            
              NEOLED_CTRL_T_ONE_H
              [24:20]
              pulse-clock ticks per ONE high-time
            
            
              NEOLED_CTRL_IRQ_CONF
              [27:27]
              TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty
            
            
              NEOLED_CTRL_TX_EMPTY
              [28:28]
              read-only
              TX FIFO is empty
            
            
              NEOLED_CTRL_TX_HALF
              [29:29]
              read-only
              TX FIFO is at least half-full
            
            
              NEOLED_CTRL_TX_FULL
              [30:30]
              read-only
              TX FIFO is full
            
            
              NEOLED_CTRL_TX_BUSY
              [31:31]
              read-only
              busy flag
            
          
        
        
          DATA
          Data register
          0x04
        
      
    
 
    
    
      SYSINFO
      System configuration information memory
      SYSINFO
      0xFFFFFFE0
 
      
        0
        0x20
        registers
      
 
      
        
          CLK
          Clock speed in Hz
          0x00
          read-only
        
        
          SOC
          SoC features
          0x08
          read-only
          
            SYSINFO_SOC_BOOTLOADER[0:0]Bootloader implemented
            SYSINFO_SOC_MEM_EXT[1:1]External bus interface implemented
            SYSINFO_SOC_MEM_INT_IMEM[2:2]Processor-internal instruction memory implemented
            SYSINFO_SOC_MEM_INT_DMEM[3:3]Processor-internal data memory implemented
            SYSINFO_SOC_MEM_EXT_ENDIAN[4:4]External bus interface uses BIG-endian byte-order
            SYSINFO_SOC_ICACHE[5:5]Processor-internal instruction cache implemented
            SYSINFO_SOC_IS_SIM[13:13]Set if processor is being simulated
            SYSINFO_SOC_OCD[14:14]On-chip debugger implemented
            SYSINFO_SOC_HW_RESET[15:15]Dedicated hardware reset of core registers implemented
            SYSINFO_SOC_IO_GPIO[16:16]General purpose input/output port unit implemented
            SYSINFO_SOC_IO_MTIME[17:17]Machine system timer implemented
            SYSINFO_SOC_IO_UART0[18:18]Primary universal asynchronous receiver/transmitter 0 implemented
            SYSINFO_SOC_IO_SPI[19:19]Serial peripheral interface implemented
            SYSINFO_SOC_IO_TWI[20:20]Two-wire interface implemented
            SYSINFO_SOC_IO_PWM[21:21]Pulse-width modulation unit implemented
            SYSINFO_SOC_IO_WDT[22:22]Watchdog timer implemented
            SYSINFO_SOC_IO_CFS[23:23]Custom functions subsystem implemented
            SYSINFO_SOC_IO_TRNG[24:24]True random number generator implemented
            SYSINFO_SOC_IO_SLINK[25:25]Stream link interface implemented
            SYSINFO_SOC_IO_UART1[26:26]Secondary universal asynchronous receiver/transmitter 1 implemented
            SYSINFO_SOC_IO_NEOLED[27:27]NeoPixel-compatible smart LED interface implemented
            SYSINFO_SOC_IO_XIRQ[28:28]External interrupt controller implemented
            SYSINFO_SOC_IO_GPTMR[29:29]General purpose timer implemented
            SYSINFO_SOC_IO_XIP[30:30]Execute in place module implemented
          
        
        
          CACHE
          Cache configuration
          0x0C
          read-only
          
            SYSINFO_CACHE_IC_BLOCK_SIZE[3:0]i-cache: log2(Block size in bytes)
            SYSINFO_CACHE_IC_NUM_BLOCKS[7:4]i-cache: log2(Number of cache blocks/pages/lines)
            SYSINFO_CACHE_IC_ASSOCIATIVITY[11:8]i-cache: log2(associativity)
            SYSINFO_CACHE_IC_REPLACEMENT[15:12]i-cache: replacement policy (0001 = LRU if associativity > 0)
          
        
        
          ISPACE_BASE
          Instruction memory address space base address
          0x10
          read-only
        
        
          DSPACE_BASE
          Data memory address space base address
          0x14
          read-only
        
        
          IMEM_SIZE
          Internal instruction memory (IMEM) size in bytes
          0x18
          read-only
        
        
          DMEM_SIZE
          Internal data memory (DMEM) size in bytes
          0x1C
          read-only
        
      
    
 
  


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[/] [neorv32/] [trunk/] [sw/] [svd/] [neorv32.svd] - Blame information for rev 73

Line No.	Rev	Author	Line
1	69	zero_gravi
2
3
4			`stnolting`
5			`neorv32`
6			`RISC-V`
7			`1.6.4`
8			`The NEORV32 RISC-V Processor`
9
10
11
12			`NEORV32`
13			`r2p0`
14			`little`
15			`true`
16			`true`
17			`false`
18			`false`
19			`true`
20			`true`
21			`0`
22			`false`
23
24
25
26			`8`
27			`32`
28			`32`
29			`read-write`
30			`0x00000000`
31			`0x00000000`
32
33
34
35
36
37
38			`CFS`
39			`Custom functions subsystem`
40			`CFS`
41			`0xFFFFFE00`
42
43			`CFS_FIRQ1`
44
45
46			`0`
47			`0x80`
48			`registers`
49
50
51
52			`REG0Application-defined0x00`
53			`REG1Application-defined0x04`
54			`REG2Application-defined0x08`
55			`REG3Application-defined0x0C`
56			`REG4Application-defined0x10`
57			`REG5Application-defined0x14`
58			`REG6Application-defined0x18`
59			`REG7Application-defined0x1C`
60			`REG8Application-defined0x20`
61			`REG9Application-defined0x24`
62			`REG10Application-defined0x28`
63			`REG11Application-defined0x2C`
64			`REG12Application-defined0x30`
65			`REG13Application-defined0x34`
66			`REG14Application-defined0x38`
67			`REG15Application-defined0x3C`
68			`REG16Application-defined0x40`
69			`REG17Application-defined0x44`
70			`REG18Application-defined0x48`
71			`REG19Application-defined0x4C`
72			`REG20Application-defined0x50`
73			`REG21Application-defined0x54`
74			`REG22Application-defined0x58`
75			`REG23Application-defined0x5C`
76			`REG24Application-defined0x60`
77			`REG25Application-defined0x64`
78			`REG26Application-defined0x68`
79			`REG27Application-defined0x6C`
80			`REG28Application-defined0x70`
81			`REG29Application-defined0x74`
82			`REG30Application-defined0x78`
83			`REG31Application-defined0x7C`
84
85
86
87
88
89			`PWM`
90			`Pulse-width modulation controller`
91			`PWM`
92			`0xFFFFFE80`
93
94
95			`0`
96			`0x40`
97			`registers`
98
99
100
101
102			`CTRL`
103			`Control register`
104			`0x00`
105
106
107			`PWM_CTRL_EN`
108			`[0:0]`
109			`PWM controller enable flag`
110
111
112			`PWM_CTRL_PRSCx`
113			`[3:1]`
114			`Clock prescaler select`
115
116
117
118
119			`DUTY0`
120			`Duty cycle register 0`
121			`0x04`
122
123
124			`DUTY1`
125			`Duty cycle register 1`
126			`0x08`
127
128
129			`DUTY2`
130			`Duty cycle register 2`
131			`0x0C`
132
133
134			`DUTY3`
135			`Duty cycle register 3`
136			`0x10`
137
138
139			`DUTY4`
140			`Duty cycle register 4`
141			`0x14`
142
143
144			`DUTY5`
145			`Duty cycle register 5`
146			`0x18`
147
148
149			`DUTY6`
150			`Duty cycle register 6`
151			`0x1C`
152
153
154			`DUTY7`
155			`Duty cycle register 7`
156			`0x20`
157
158
159			`DUTY8`
160			`Duty cycle register 8`
161			`0x24`
162
163
164			`DUTY9`
165			`Duty cycle register 9`
166			`0x28`
167
168
169			`DUTY10`
170			`Duty cycle register 10`
171			`0x2C`
172
173
174			`DUTY11`
175			`Duty cycle register 11`
176			`0x30`
177
178
179			`DUTY12`
180			`Duty cycle register 12`
181			`0x34`
182
183
184			`DUTY13`
185			`Duty cycle register 13`
186			`0x38`
187
188
189			`DUTY14`
190			`Duty cycle register 14`
191			`0x3C`
192
193
194
195
196
197
198			`SLINK`
199			`Stream link interface`
200			`SLINK`
201			`0xFFFFFEC0`
202
203			`SLINK_RX_FIRQ10`
204			`SLINK_TX_FIRQ11`
205
206
207			`0`
208			`0x40`
209			`registers`
210
211
212
213
214			`CTRL`
215			`Control register`
216			`0x00`
217
218
219			`SLINK_CTRL_RX_NUMx`
220			`read-only`
221			`[3:0]`
222			`Number of implemented RX links`
223
224
225			`SLINK_CTRL_TX_NUMx`
226			`read-only`
227			`[7:4]`
228			`Number of implemented TX links`
229
230
231			`SLINK_CTRL_RX_FIFO_Sx`
232			`read-only`
233			`[11:8]`
234			`log2(RX FIFO size)`
235
236
237			`SLINK_CTRL_TX_FIFO_Sx`
238			`read-only`
239			`[15:12]`
240			`log2(TX FIFO size)`
241
242
243			`SLINK_CTRL_EN`
244			`read-write`
245			`[31:31]`
246			`SLINK enable flag`
247
248
249
250
251			`IRQ`
252			`Link interrupt configuration register`
253			`0x08`
254
255
256			`SLINK_IRQ_RX_EN`
257			`[7:0]`
258			`RX link interrupt enable`
259
260
261			`SLINK_IRQ_RX_MODE`
262			`[15:8]`
263			`RX link interrupt mode`
264
265
266			`SLINK_IRQ_TX_EN`
267			`[23:16]`
268			`TX link interrupt enable`
269
270
271			`SLINK_IRQ_TX_MODE`
272			`[31:24]`
273			`TX link interrupt mode`
274
275
276
277
278			`STATUS`
279			`Link status register`
280			`0x10`
281
282
283			`SLINK_STATUS_RX_AVAIL`
284			`[7:0]`
285			`RX link n FIFO is NOT empty (data available)`
286
287
288			`SLINK_STATUS_TX_FREE`
289			`[15:8]`
290			`TX link n FIFO is NOT full (ready to send)`
291
292
293			`SLINK_STATUS_RX_HALF`
294			`[23:16]`
295			`RX link n FIFO fill level is >= half-full`
296
297
298			`SLINK_STATUS_TX_HALF`
299			`[31:24]`
300			`TX link 0 FIFO fill level is > half-full`
301
302
303
304
305			`DATA0`
306			`Link 0 RTX data register`
307			`0x20`
308
309
310			`DATA1`
311			`Link 1 RTX data register`
312			`0x24`
313
314
315			`DATA2`
316			`Link 2 RTX data register`
317			`0x28`
318
319
320			`DATA3`
321			`Link 3 RTX data register`
322			`0x2C`
323
324
325			`DATA4`
326			`Link 4 RTX data register`
327			`0x30`
328
329
330			`DATA5`
331			`Link 5 RTX data register`
332			`0x34`
333
334
335			`DATA6`
336			`Link 6 RTX data register`
337			`0x38`
338
339
340			`DATA7`
341			`Link 7 RTX data register`
342			`0x3C`
343
344
345
346
347	70	zero_gravi
348
349			`XIP`
350			`Execute In Place Module`
351			`CIP`
352			`0xFFFFFF40`
353
354
355			`0`
356			`0x10`
357			`registers`
358
359
360
361
362			`CTRL`
363			`Control register`
364			`0x00`
365
366
367			`XIP_CTRL_EN`
368			`[0:0]`
369			`XIP module enable flag`
370
371
372			`XIP_CTRL_PRSC`
373			`[3:1]`
374			`SPI clock prescaler select`
375
376
377			`XIP_CTRL_CPOL`
378			`[4:4]`
379			`SPI clock (idle) polarity`
380
381
382			`XIP_CTRL_CPHA`
383			`[5:5]`
384			`SPI clock phase`
385
386
387			`XIP_CTRL_SPI_NBYTES`
388			`[9:6]`
389			`Number of bytes in SPI transmission`
390
391
392			`XIP_CTRL_XIP_EN`
393			`[10:10]`
394			`XIP mode enable`
395
396
397			`XIP_CTRL_XIP_ABYTES`
398			`[12:11]`
399			`Number of XIP address bytes (minus 1)`
400
401
402			`XIP_CTRL_RD_CMD`
403			`[20:13]`
404			`SPI flash read command`
405
406
407			`XIP_CTRL_XIP_PAGE`
408			`[24:21]`
409			`XIP memory page`
410
411
412			`XIP_CTRL_SPI_CSEN`
413			`[25:25]`
414			`SPI chip-select enable`
415
416
417			`XIP_CTRL_HIGHSPEED`
418			`[26:26]`
419			`SPI high-speed mode enable (ignoring XIP_CTRL_PRSC)`
420
421
422			`XIP_CTRL_PHY_BUSY`
423			`[30:30]`
424			`read-only`
425			`SPI PHY busy`
426
427
428			`XIP_CTRL_XIP_BUSY`
429			`[31:31]`
430			`read-only`
431			`XIP access in progress`
432
433
434
435
436			`DATA_LO`
437			`Direct SPI access - data register low`
438			`0x08`
439
440
441			`DATA_HI`
442			`Direct SPI access - data register high`
443			`0x0C`
444
445
446
447
448	69	zero_gravi
449
450			`GPTMR`
451			`General purpose timer`
452			`GPTMR`
453			`0xFFFFFF60`
454
455			`GPTMR_FIRQ12`
456
457
458			`0`
459			`0x10`
460			`registers`
461
462
463
464
465			`CTRL`
466			`Control register`
467			`0x00`
468
469
470			`GPTMR_CTRL_EN`
471			`[0:0]`
472			`Timer enable flag`
473
474
475			`GPTMR_CTRL_PRSC`
476			`[3:1]`
477			`Clock prescaler select`
478
479
480			`GPTMR_CTRL_MODE`
481			`[4:4]`
482			`Timer mode: 0=single-shot mode, 1=continuous mode`
483
484
485
486
487			`THRES`
488			`Threshold register`
489			`0x04`
490
491
492			`COUNT`
493			`Counter register`
494			`0x08`
495
496
497
498
499
500
501			`BUSKEEPER`
502			`Bus keeper`
503			`BUSKEEPER`
504			`0xFFFFFF7C`
505
506
507			`0`
508			`0x04`
509			`registers`
510
511
512
513
514			`CTRL`
515			`Control register`
516			`0x00`
517
518
519			`BUSKEEPER_ERR_TYPE`
520			`[0:0]`
521			`read-only`
522			`Bus error type: 0=device error, 1=access timeout`
523
524
525			`BUSKEEPER_ERR_FLAG`
526			`[31:31]`
527			`Sticky error flag, clears after read or write access`
528
529
530
531
532
533
534
535
536			`XIRQ`
537			`External interrupts controller`
538			`XIRQ`
539			`0xFFFFFF80`
540
541			`XIRQ_FIRQ8`
542
543
544			`0`
545			`0x10`
546			`registers`
547
548
549
550
551			`IER`
552			`IRQ input enable register`
553			`0x00`
554
555
556			`IPR`
557			`IRQ pending/ack/clear register`
558			`0x04`
559
560
561			`SCR`
562			`IRQ source register`
563			`0x08`
564
565
566
567
568
569
570			`MTIME`
571			`Machine timer`
572			`MTIME`
573			`0xFFFFFF90`
574
575
576			`0`
577			`0x10`
578			`registers`
579
580
581
582
583			`TIME_LO`
584			`System time register - low`
585			`0x00`
586
587
588			`TIME_HI`
589			`System time register - high`
590			`0x04`
591
592
593			`TIMECMP_LO`
594			`Time compare register - low`
595			`0x08`
596
597
598			`TIMECMP_HI`
599			`Time compare register - high`
600			`0x0C`
601
602
603
604
605
606
607			`UART0`
608			`Primary universal asynchronous receiver and transmitter`
609			`UART0`
610			`0xFFFFFFA0`
611
612			`UART0_RX_FIRQ2`
613			`UART0_TX_FIRQ3`
614
615
616			`0`
617			`0x08`
618			`registers`
619
620
621
622
623			`CTRL`
624			`Control register`
625			`0x00`
626
627
628			`UART_CTRL_BAUD`
629			`[11:0]`
630			`Baud rate divisor`
631
632
633			`UART_CTRL_SIM_MODE`
634			`[12:12]`
635			`Simulation output override enable, for use in simulation only`
636
637
638			`UART_CTRL_RX_EMPTY`
639			`[13:13]`
640			`read-only`
641			`RX FIFO is empty`
642
643
644			`UART_CTRL_RX_HALF`
645			`[14:14]`
646			`read-only`
647			`RX FIFO is at least half-full`
648
649
650			`UART_CTRL_RX_FULL`
651			`[15:15]`
652			`read-only`
653			`RX FIFO is full`
654
655
656			`UART_CTRL_TX_EMPTY`
657			`[16:16]`
658			`read-only`
659			`TX FIFO is empty`
660
661
662			`UART_CTRL_TX_HALF`
663			`[17:17]`
664			`read-only`
665			`TX FIFO is at least half-full`
666
667
668			`UART_CTRL_TX_FULL`
669			`[18:18]`
670			`read-only`
671			`TX FIFO is full`
672
673
674			`UART_CTRL_RTS_EN`
675			`[20:20]`
676			`Enable hardware flow control: Assert RTS output if UART.RX is ready to receive`
677
678
679			`UART_CTRL_CTS_EN`
680			`[21:21]`
681			`Enable hardware flow control: UART.TX starts sending only if CTS input is asserted`
682
683
684			`UART_CTRL_PMODE0`
685			`[22:22]`
686			`Parity configuration (0=even; 1=odd)`
687
688
689			`UART_CTRL_PMODE1`
690			`[23:23]`
691			`Parity bit enabled when set`
692
693
694			`UART_CTRL_PRSC`
695			`[26:24]`
696			`Clock prescaler select`
697
698
699			`UART_CTRL_CTS`
700			`[27:27]`
701			`read-only`
702			`current state of CTS input`
703
704
705			`UART_CTRL_EN`
706			`[28:28]`
707			`UART enable flag`
708
709
710			`UART_CTRL_RX_IRQ`
711			`[29:29]`
712			`RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty`
713
714
715			`UART_CTRL_TX_IRQ`
716			`[30:30]`
717			`TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full`
718
719
720			`UART_CTRL_TX_BUSY`
721			`[31:31]`
722			`read-only`
723			`Transmitter is busy when set`
724
725
726
727
728			`DATA`
729			`RX/TX data register`
730			`0x04`
731
732
733			`UART_DATA`
734			`[7:0]`
735			`Receive/transmit data`
736
737
738			`UART_DATA_PERR`
739			`[28:28]`
740			`read-only`
741			`RX parity error detected when set`
742
743
744			`UART_DATA_FERR`
745			`[29:29]`
746			`read-only`
747			`RX frame error (no valid stop bit) detected when set`
748
749
750			`UART_DATA_OVERR`
751			`[30:30]`
752			`read-only`
753			`RX parity error detected when set`
754
755
756			`UART_DATA_AVAIL`
757			`[31:31]`
758			`read-only`
759			`RX data available when set`
760
761
762
763
764
765
766
767
768			`UART1`
769			`Secondary universal asynchronous receiver and transmitter`
770			`UART1`
771			`0xFFFFFFD0`
772
773			`UART1_RX_FIRQ4`
774			`UART1_TX_FIRQ5`
775
776
777			`0`
778			`0x08`
779			`registers`
780
781
782
783
784
785
786			`SPI`
787			`Serial peripheral interface controller`
788			`SPI`
789			`0xFFFFFFA8`
790
791			`SPI_FIRQ6`
792
793
794			`0`
795			`0x08`
796			`registers`
797
798
799
800
801			`CTRL`
802			`Control register`
803			`0x00`
804
805
806			`SPI_CTRL_CS`
807			`[7:0]`
808			`Direct chip select line`
809
810
811			`SPI_CTRL_EN`
812			`[8:8]`
813			`SPI enable flag`
814
815
816			`SPI_CTRL_CPHA`
817			`[9:9]`
818			`Clock phase`
819
820
821			`SPI_CTRL_PRSC`
822			`[12:10]`
823			`Clock prescaler select`
824
825
826			`SPI_CTRL_SIZE`
827			`[14:13]`
828			`Data transfer size`
829
830
831			`SPI_CTRL_CPOL`
832			`[15:15]`
833			`Clock polarity`
834
835
836	70	zero_gravi	`SPI_CTRL_HIGHSPEED`
837			`[16:16]`
838			`SPI high-speed mode enable (ignoring SPI_CTRL_PRSC)`
839
840
841	69	zero_gravi	`SPI_CTRL_BUSY`
842			`[31:31]`
843			`read-only`
844			`SPI busy flag`
845
846
847
848
849			`DATA`
850			`RX/TX data register`
851			`0x04`
852
853
854
855
856
857
858			`TWI`
859			`Two-wire interface controller`
860			`SPI`
861			`0xFFFFFFB0`
862
863			`TWI_FIRQ7`
864
865
866			`0`
867			`0x08`
868			`registers`
869
870
871
872
873			`CTRL`
874			`Control register`
875			`0x00`
876
877
878			`TWI_CTRL_EN`
879			`[0:0]`
880			`TWI enable flag`
881
882
883			`TWI_CTRL_START`
884			`[1:1]`
885			`Generate START condition, auto-clears`
886
887
888			`TWI_CTRL_STOP`
889			`[2:2]`
890			`Generate STOP condition, auto-clears`
891
892
893			`TWI_CTRL_PRSC`
894			`[5:3]`
895			`Clock prescaler select`
896
897
898			`TWI_CTRL_MACK`
899			`[6:6]`
900			`Generate ACK by controller for each transmission`
901
902
903			`TWI_CTRL_ACK`
904			`[30:30]`
905			`read-only`
906			`ACK received when set`
907
908
909			`TWI_CTRL_BUSY`
910			`[31:31]`
911			`read-only`
912			`Transfer in progress, busy flag`
913
914
915
916
917			`DATA`
918			`RX/TX data register`
919			`0x04`
920
921
922			`TWI_DATA`
923			`[7:0]`
924			`RX/TX data`
925
926
927
928
929
930
931
932
933			`TRNG`
934			`True random number generator`
935			`TRNG`
936			`0xFFFFFFB8`
937
938
939			`0`
940			`0x04`
941			`registers`
942
943
944
945
946			`CTRL`
947			`Control and data register`
948			`0x00`
949
950
951			`TRNG_CTRL_DATA`
952			`[7:0]`
953			`read-only`
954			`Random data`
955
956
957			`TRNG_CTRL_EN`
958			`[30:30]`
959			`TRNG enable flag`
960
961
962			`TRNG_CTRL_VALID`
963			`[31:31]`
964			`read-only`
965			`Random data output valid`
966
967
968
969
970
971
972
973
974			`WDT`
975			`Watchdog timer`
976			`WDT`
977			`0xFFFFFFBC`
978
979			`WDT_FIRQ0`
980
981
982			`0`
983			`0x04`
984			`registers`
985
986
987
988
989			`CTRL`
990			`Control register`
991			`0x00`
992
993
994			`WDT_CTRL_EN`
995			`[0:0]`
996			`WDT enable flag`
997
998
999			`WDT_CTRL_CLK_SEL`
1000			`[3:1]`
1001			`Clock prescaler select`
1002
1003
1004			`WDT_CTRL_MODE`
1005			`[4:4]`
1006			`Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset`
1007
1008
1009			`WDT_CTRL_RCAUSE`
1010			`[5:5]`
1011			`read-only`
1012			`Cause of last system reset: 0=external reset, 1=watchdog`
1013
1014
1015			`WDT_CTRL_RESET`
1016			`[6:6]`
1017			`Reset WDT counter when set, auto-clears`
1018
1019
1020			`WDT_CTRL_FORCE`
1021			`[7:7]`
1022			`Force WDT action, auto-clears`
1023
1024
1025			`WDT_CTRL_LOCK`
1026			`[8:8]`
1027			`Lock write access to control register, clears on reset (HW or WDT) only`
1028
1029
1030			`WDT_CTRL_DBEN`
1031			`[9:9]`
1032			`Allow WDT to continue operation even when in debug mode`
1033
1034
1035			`WDT_CTRL_HALF`
1036			`[10:10]`
1037			`read-only`
1038			`Set if at least half of the max. timeout counter value has been reached`
1039
1040
1041
1042
1043
1044
1045
1046
1047			`GPIO`
1048			`General purpose input/output port`
1049			`GPIO`
1050			`0xFFFFFFc0`
1051
1052
1053			`0`
1054			`0x10`
1055			`registers`
1056
1057
1058
1059
1060			`INPUT_LO`
1061			`Parallel input register - low`
1062			`0x00`
1063			`read-only`
1064
1065
1066			`INPUT_HI`
1067			`Parallel input register - high`
1068			`0x04`
1069			`read-only`
1070
1071
1072			`OUTPUT_LO`
1073			`Parallel output register - low`
1074			`0x08`
1075
1076
1077			`OUTPUT_HI`
1078			`Parallel output register - high`
1079			`0x0C`
1080
1081
1082
1083
1084
1085
1086			`NEOLED`
1087			`Smart LED hardware interface`
1088			`NEOLED`
1089			`0xFFFFFFD8`
1090
1091			`NEOLED_FIRQ9`
1092
1093
1094			`0`
1095			`0x08`
1096			`registers`
1097
1098
1099
1100
1101			`CTRL`
1102			`Control register`
1103			`0x00`
1104
1105
1106			`NEOLED_CTRL_EN`
1107			`[0:0]`
1108			`NEOLED enable flag`
1109
1110
1111			`NEOLED_CTRL_MODE`
1112			`[1:1]`
1113			`TX mode (0=24-bit, 1=32-bit)`
1114
1115
1116			`NEOLED_CTRL_STROBE`
1117			`[2:2]`
1118			`Strobe (0=send normal data, 1=send RESET command on data write)`
1119
1120
1121			`NEOLED_CTRL_PRSC`
1122			`[5:3]`
1123			`Clock prescaler select`
1124
1125
1126			`NEOLED_CTRL_BUFS`
1127			`[9:6]`
1128			`read-only`
1129			`log2(tx buffer size)`
1130
1131
1132			`NEOLED_CTRL_T_TOT`
1133			`[14:10]`
1134			`pulse-clock ticks per total period bit`
1135
1136
1137			`NEOLED_CTRL_T_ZERO_H`
1138			`[19:15]`
1139			`pulse-clock ticks per ZERO high-time`
1140
1141
1142			`NEOLED_CTRL_T_ONE_H`
1143			`[24:20]`
1144			`pulse-clock ticks per ONE high-time`
1145
1146
1147			`NEOLED_CTRL_IRQ_CONF`
1148			`[27:27]`
1149			`TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty`
1150
1151
1152			`NEOLED_CTRL_TX_EMPTY`
1153			`[28:28]`
1154			`read-only`
1155			`TX FIFO is empty`
1156
1157
1158			`NEOLED_CTRL_TX_HALF`
1159			`[29:29]`
1160			`read-only`
1161			`TX FIFO is at least half-full`
1162
1163
1164			`NEOLED_CTRL_TX_FULL`
1165			`[30:30]`
1166			`read-only`
1167			`TX FIFO is full`
1168
1169
1170			`NEOLED_CTRL_TX_BUSY`
1171			`[31:31]`
1172			`read-only`
1173			`busy flag`
1174
1175
1176
1177
1178			`DATA`
1179			`Data register`
1180			`0x04`
1181
1182
1183
1184
1185
1186
1187			`SYSINFO`
1188			`System configuration information memory`
1189			`SYSINFO`
1190			`0xFFFFFFE0`
1191
1192
1193			`0`
1194			`0x20`
1195			`registers`
1196
1197
1198
1199
1200			`CLK`
1201			`Clock speed in Hz`
1202			`0x00`
1203			`read-only`
1204
1205
1206			`SOC`
1207			`SoC features`
1208			`0x08`
1209			`read-only`
1210
1211			`SYSINFO_SOC_BOOTLOADER[0:0]Bootloader implemented`
1212			`SYSINFO_SOC_MEM_EXT[1:1]External bus interface implemented`
1213			`SYSINFO_SOC_MEM_INT_IMEM[2:2]Processor-internal instruction memory implemented`
1214			`SYSINFO_SOC_MEM_INT_DMEM[3:3]Processor-internal data memory implemented`
1215			`SYSINFO_SOC_MEM_EXT_ENDIAN[4:4]External bus interface uses BIG-endian byte-order`
1216			`SYSINFO_SOC_ICACHE[5:5]Processor-internal instruction cache implemented`
1217			`SYSINFO_SOC_IS_SIM[13:13]Set if processor is being simulated`
1218			`SYSINFO_SOC_OCD[14:14]On-chip debugger implemented`
1219			`SYSINFO_SOC_HW_RESET[15:15]Dedicated hardware reset of core registers implemented`
1220			`SYSINFO_SOC_IO_GPIO[16:16]General purpose input/output port unit implemented`
1221			`SYSINFO_SOC_IO_MTIME[17:17]Machine system timer implemented`
1222			`SYSINFO_SOC_IO_UART0[18:18]Primary universal asynchronous receiver/transmitter 0 implemented`
1223			`SYSINFO_SOC_IO_SPI[19:19]Serial peripheral interface implemented`
1224			`SYSINFO_SOC_IO_TWI[20:20]Two-wire interface implemented`
1225			`SYSINFO_SOC_IO_PWM[21:21]Pulse-width modulation unit implemented`
1226			`SYSINFO_SOC_IO_WDT[22:22]Watchdog timer implemented`
1227			`SYSINFO_SOC_IO_CFS[23:23]Custom functions subsystem implemented`
1228			`SYSINFO_SOC_IO_TRNG[24:24]True random number generator implemented`
1229			`SYSINFO_SOC_IO_SLINK[25:25]Stream link interface implemented`
1230			`SYSINFO_SOC_IO_UART1[26:26]Secondary universal asynchronous receiver/transmitter 1 implemented`
1231			`SYSINFO_SOC_IO_NEOLED[27:27]NeoPixel-compatible smart LED interface implemented`
1232			`SYSINFO_SOC_IO_XIRQ[28:28]External interrupt controller implemented`
1233			`SYSINFO_SOC_IO_GPTMR[29:29]General purpose timer implemented`
1234	70	zero_gravi	`SYSINFO_SOC_IO_XIP[30:30]Execute in place module implemented`
1235	69	zero_gravi
1236
1237
1238			`CACHE`
1239			`Cache configuration`
1240			`0x0C`
1241			`read-only`
1242
1243			`SYSINFO_CACHE_IC_BLOCK_SIZE[3:0]i-cache: log2(Block size in bytes)`
1244			`SYSINFO_CACHE_IC_NUM_BLOCKS[7:4]i-cache: log2(Number of cache blocks/pages/lines)`
1245			`SYSINFO_CACHE_IC_ASSOCIATIVITY[11:8]i-cache: log2(associativity)`
1246			`SYSINFO_CACHE_IC_REPLACEMENT[15:12]i-cache: replacement policy (0001 = LRU if associativity > 0)`
1247
1248
1249
1250			`ISPACE_BASE`
1251			`Instruction memory address space base address`
1252			`0x10`
1253			`read-only`
1254
1255
1256			`DSPACE_BASE`
1257			`Data memory address space base address`
1258			`0x14`
1259			`read-only`
1260
1261
1262			`IMEM_SIZE`
1263			`Internal instruction memory (IMEM) size in bytes`
1264			`0x18`
1265			`read-only`
1266
1267
1268			`DMEM_SIZE`
1269			`Internal data memory (DMEM) size in bytes`
1270			`0x1C`
1271			`read-only`
1272
1273
1274
1275
1276
1277