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fpga_is_fu |
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
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-- (email: opencores@vivare-services.com)
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--
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-- This program is free software: you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or any
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-- later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- Created: 24-02-2022 13:24:00
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--
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-----------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY work;
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PACKAGE memory_vhd_v03_pkg IS
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-- /////////////////\\\\\\\\\\\\\\\\\\\
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-- ************************************
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-- *** User Settings ***
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-- ************************************
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-- Wishbone Bus
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CONSTANT WB_DATA_WIDTH : integer := 32; -- Wishbone Data Bus width
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CONSTANT WB_ADDR_WIDTH : integer := 5; -- Wishbone Address Bus width
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CONSTANT VENDOR : string := "generic"; -- (generic, altera, xilinx)
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-- NOT IMPLEMENTED YET
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-- Bus width (DATA_T) of all memories (all are equal)
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-- Chose a value high enough to hold all possible values cumulated in
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-- y_inj_reg,
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-- Memory t,
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-- Memory bias,
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-- Memory w
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CONSTANT DATA_WIDTH : integer := 8;
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-- Address width of s input vector memory (maximum number of components/inputs = 2**MEM_S_ADDR_WIDTH)
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CONSTANT MEM_S_ADDR_WIDTH : integer := 3; -- = 8
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-- Address width of t output vector memory (maximum number of neurons/outputs = 2**MEM_T_ADDR_WIDTH)
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CONSTANT MEM_T_ADDR_WIDTH : integer := 2; -- = 4
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-- /////////////////\\\\\\\\\\\\\\\\\\\
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-- /////////////////\\\\\\\\\\\\\\\\\\\
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-- ************************************
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-- *** System Constants ***
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-- *** DO NOT CHANGE ***
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-- ************************************
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-- Number of maximum usable components/inputs - 1
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CONSTANT I_MAX : integer := ( 2 ** MEM_S_ADDR_WIDTH ) - 1;
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-- Number of maximum usable neurons/outputs - 1
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CONSTANT J_MAX : integer := ( 2 ** MEM_T_ADDR_WIDTH ) - 1;
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-- Width of Memory Latency counter (mem_rd_lat_reg)
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CONSTANT MEM_LAT_CNT_WIDTH : integer := 7; -- At least 3 bits width -> latency 0...2
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-- Value to reach for leaving counting loops
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CONSTANT MEM_LAT_CNT_TRANSITION : integer := ( 2 ** MEM_LAT_CNT_WIDTH ) - 1;
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-- Number of memory write lines (to build up the RD/WR vector
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CONSTANT MEM_WR_LINES : integer := 5;
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CONSTANT MEM_S_BITPOS : integer := MEM_WR_LINES - 5;
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CONSTANT MEM_T_BITPOS : integer := MEM_WR_LINES - 4;
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CONSTANT MEM_W_BITPOS : integer := MEM_WR_LINES - 3;
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CONSTANT MEM_Y_BITPOS : integer := MEM_WR_LINES - 2;
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CONSTANT MEM_BIAS_BITPOS : integer := MEM_WR_LINES - 1;
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-- Status READY FOR COMMANDS bit position
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CONSTANT STAT_RDY : integer := 0;
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-- Status Latency Messurement in progress
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CONSTANT STAT_LAT_RUN : integer := 1;
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-- Status Controller is NOT ready -> RESET (while start of function TRAIN)
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CONSTANT STAT_NOT_RDY : integer := 2;
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-- Status Interrupt Enable
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CONSTANT STAT_INT_EN : integer := 3;
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-- Status Memory Error
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CONSTANT STAT_MEMERR : integer := 4;
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-- Status DATA OUTPUT READY bit position
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CONSTANT STAT_RD_WR_COMPLETE : integer := 5;
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-- Status Interrupt TEST pending
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CONSTANT STAT_INT_TEST : integer := 6;
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-- Status Interrupt TRAIN pending
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CONSTANT STAT_INT_TRAIN : integer := 7;
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-- Calculate all memory address widths and other dependencies
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-- s input memory depth
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CONSTANT MEM_S_DEPTH : integer := ( 2**MEM_S_ADDR_WIDTH ) - 1;
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-- t output memory depth
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CONSTANT MEM_T_DEPTH : integer := ( 2**MEM_T_ADDR_WIDTH ) - 1;
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-- w (weights) memory address width calculation
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CONSTANT MEM_W_ADDR_WIDTH : integer := MEM_S_ADDR_WIDTH + MEM_T_ADDR_WIDTH;
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-- w (weights) memory depths calculation
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CONSTANT MEM_W_DEPTH : integer := ( 2**MEM_W_ADDR_WIDTH ) - 1;
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-- ************************************
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-- Wishbone Address Map
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CONSTANT WB_STAT_A : integer := 0; --
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CONSTANT WB_THRES : integer := 1; --
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CONSTANT WB_BIAS : integer := 2; --
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CONSTANT WB_OFFSET : integer := 3; --
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CONSTANT WB_MAXEPOCH : integer := 4; --
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CONSTANT WB_UNUSED_X05 : integer := 5; -- DO NOT USE, for feature use
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CONSTANT WB_UNUSED_X06 : integer := 6; -- DO NOT USE, for feature use
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CONSTANT WB_STARTI : integer := 7; --
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CONSTANT WB_STOPI : integer := 8; --
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CONSTANT WB_STARTJ : integer := 9; --
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CONSTANT WB_STOPJ : integer := 10; --
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CONSTANT WB_EPOCH : integer := 11; --
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CONSTANT WB_WRLAT : integer := 12; --
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CONSTANT WB_RDLAT : integer := 13; --
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CONSTANT WB_ALLLAT : integer := 14; --
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CONSTANT WB_START3 : integer := 15; --
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CONSTANT WB_START4 : integer := 16; --
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CONSTANT WB_START5_S : integer := 17; --
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CONSTANT WB_START5_T : integer := 18; --
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CONSTANT WB_START5_W : integer := 19; --
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CONSTANT WB_START5_Y : integer := 20; --
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CONSTANT WB_START5_BIAS : integer := 21; --
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CONSTANT WB_START6 : integer := 22; --
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CONSTANT WB_IMAX : integer := 23; --
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CONSTANT WB_JMAX : integer := 24; --
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CONSTANT WB_MEMDATA_WIDTH : integer := 25; --
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-- ************************************
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-- ************************************
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-- *** Type Definitions ***
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-- ************************************
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-- Wishbone data and address types
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SUBTYPE WB_DATA_WIDTH_T IS std_logic_vector ( WB_DATA_WIDTH-1 downto 0 );
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SUBTYPE WB_ADDR_WIDTH_T IS std_logic_vector ( WB_ADDR_WIDTH-1 downto 0 );
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-- Data bus type for all memories
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SUBTYPE DATA_T IS std_logic_vector ( DATA_WIDTH-1 downto 0 );
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SUBTYPE DATA_N IS integer range DATA_WIDTH-1 downto 0;
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-- Memory Latency counter type
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SUBTYPE MEM_LAT_CNT_WIDTH_T IS std_logic_vector ( MEM_LAT_CNT_WIDTH-1 downto 0 );
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-- Vector bus to select memory RD or WR
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SUBTYPE MEM_WR_LINES_T IS std_logic_vector ( MEM_WR_LINES-1 downto 0 );
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-- Declare the types for all memory address busses
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-- s input memory
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SUBTYPE ADDRESS_S_T IS std_logic_vector ( MEM_S_ADDR_WIDTH-1 downto 0 );
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SUBTYPE ADDRESS_S_N IS integer range MEM_S_ADDR_WIDTH-1 downto 0;
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SUBTYPE ADDRESS_S_ZERO_T IS std_logic_vector ( MEM_S_ADDR_WIDTH-1 downto 1 );
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-- t input/output memory
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SUBTYPE ADDRESS_T_T IS std_logic_vector ( MEM_T_ADDR_WIDTH-1 downto 0 );
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SUBTYPE ADDRESS_T_N IS integer range MEM_T_ADDR_WIDTH-1 downto 0;
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SUBTYPE ADDRESS_T_ZERO_T IS std_logic_vector ( MEM_T_ADDR_WIDTH-1 downto 1 );
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-- w (weigths) memory
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SUBTYPE ADDRESS_W_T IS std_logic_vector ( MEM_W_ADDR_WIDTH-1 downto 0 );
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-- Declare the types for all memory arrays
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-- s input memory
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TYPE S_RAM_T IS ARRAY ( MEM_S_DEPTH DOWNTO 0 ) OF std_logic_vector( DATA_WIDTH-1 DOWNTO 0 );
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-- t output memory
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TYPE T_RAM_T IS ARRAY ( MEM_T_DEPTH DOWNTO 0 ) OF std_logic_vector( DATA_WIDTH-1 DOWNTO 0 );
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-- w (weights) memory
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TYPE W_RAM_T IS ARRAY ( MEM_W_DEPTH DOWNTO 0 ) OF std_logic_vector( DATA_WIDTH-1 DOWNTO 0 );
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-- ************************************
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SUBTYPE SIM_STATE_T IS integer;
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CONSTANT ST0 : SIM_STATE_T := 0;
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CONSTANT INIT : SIM_STATE_T := 1;
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CONSTANT WR1 : SIM_STATE_T := 2;
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CONSTANT WR_13_BURST : SIM_STATE_T := 3;
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CONSTANT WR_13_END : SIM_STATE_T := 4;
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CONSTANT WR_7_SINGLE : SIM_STATE_T := 5;
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CONSTANT WR_7_END : SIM_STATE_T := 6;
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CONSTANT ST7 : SIM_STATE_T := 7;
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END memory_vhd_v03_pkg;
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