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fpga_is_fu |
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
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-- (email: opencores@vivare-services.com)
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--
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-- This program is free software: you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or any
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-- later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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--USE ieee.numeric_std.all;
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LIBRARY work;
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USE work.memory_vhd_v03_pkg.ALL;
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ENTITY p0300_m00021_s_v03_wishbone_fsm IS
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PORT(
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clk_i : IN std_logic;
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ctrl_alllat_i : IN MEM_LAT_CNT_WIDTH_T;
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ctrl_complete_i : IN std_logic;
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ctrl_dout_i : IN DATA_T;
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ctrl_dout_valid_i : IN std_logic;
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ctrl_epoch_i : IN WB_DATA_WIDTH_T;
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ctrl_int_test_i : IN std_logic;
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ctrl_int_train_i : IN std_logic;
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ctrl_memerr_i : IN std_logic;
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ctrl_not_rdy6_i : IN std_logic;
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ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T;
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ctrl_rdy1_i : IN std_logic;
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ctrl_rdy2_i : IN std_logic;
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ctrl_rdy3_i : IN std_logic;
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ctrl_rdy4_i : IN std_logic;
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ctrl_rdy5_i : IN std_logic;
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ctrl_rdy6_i : IN std_logic;
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ctrl_run7_i : IN std_logic;
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ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T;
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rst_n_i : IN std_logic;
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wb_adr_i : IN WB_ADDR_WIDTH_T;
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wb_cyc_i : IN std_logic;
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wb_dat_i : IN WB_DATA_WIDTH_T;
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wb_stb_i : IN std_logic;
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wb_we_i : IN std_logic;
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ctrl_bias_o : OUT DATA_T;
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ctrl_clear_epoch_o : OUT std_logic;
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ctrl_din_o : OUT DATA_T;
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ctrl_int_o : OUT std_logic;
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ctrl_maxepoch_o : OUT WB_DATA_WIDTH_T;
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ctrl_offset_o : OUT DATA_T;
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ctrl_rd_vec_o : OUT MEM_WR_LINES_T;
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ctrl_set_starti_o : OUT std_logic;
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ctrl_set_startj_o : OUT std_logic;
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ctrl_start3_o : OUT std_logic;
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ctrl_start4_o : OUT std_logic;
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ctrl_start5_o : OUT std_logic;
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ctrl_start6_o : OUT std_logic;
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ctrl_starti_val_o : OUT ADDRESS_S_T;
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ctrl_startj_val_o : OUT ADDRESS_T_T;
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ctrl_stopi_val_o : OUT ADDRESS_S_T;
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ctrl_stopj_val_o : OUT ADDRESS_T_T;
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ctrl_thres_o : OUT DATA_T;
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ctrl_wr_vec_o : OUT MEM_WR_LINES_T;
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wb_ack_o : OUT std_logic;
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wb_dat_o : OUT WB_DATA_WIDTH_T
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);
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-- Declarations
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END p0300_m00021_s_v03_wishbone_fsm ;
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-- COPYRIGHT (C) 2022 Jens Gutschmidt /
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-- VIVARE GmbH Switzerland
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-- (email: opencores@vivare-services.com)
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--
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-- Versions:
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-- Revision 3.0 2022/07/21
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-- - Delete alpha register and output
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-- - Consolidate # cycles
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-- Revision 2.0 2022/06/18
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-- - Introduce self-resets for status signals
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-- - Remove states introduced for debugging
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-- Revision 1.0 2022/06/11
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-- -- First draft
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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LIBRARY work;
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USE work.memory_vhd_v03_pkg.ALL;
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ARCHITECTURE fsm OF p0300_m00021_s_v03_wishbone_fsm IS
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-- Architecture Declarations
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SIGNAL ctrl_bias_reg : DATA_T;
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SIGNAL ctrl_complete_reg : std_logic;
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SIGNAL ctrl_din_reg : DATA_T;
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SIGNAL ctrl_int_en_reg : std_logic;
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SIGNAL ctrl_int_test_reg : std_logic;
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SIGNAL ctrl_int_train_reg : std_logic;
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SIGNAL ctrl_maxepoch_reg : WB_DATA_WIDTH_T;
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SIGNAL ctrl_offset_reg : DATA_T;
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SIGNAL ctrl_rd_vec_reg : MEM_WR_LINES_T;
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SIGNAL ctrl_rdy_reg : std_logic;
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SIGNAL ctrl_starti_val_reg : ADDRESS_S_T;
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SIGNAL ctrl_startj_val_reg : ADDRESS_T_T;
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SIGNAL ctrl_stat_a_reg : DATA_T;
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SIGNAL ctrl_stopi_val_reg : ADDRESS_S_T;
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SIGNAL ctrl_stopj_val_reg : ADDRESS_T_T;
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SIGNAL ctrl_thres_reg : DATA_T;
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SIGNAL ctrl_wr_vec_reg : MEM_WR_LINES_T;
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SIGNAL wb_adr_reg : WB_ADDR_WIDTH_T;
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SIGNAL wb_cyc_reg : std_logic;
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SIGNAL wb_dat_reg : WB_DATA_WIDTH_T;
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SIGNAL wb_stb_reg : std_logic;
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SIGNAL wb_we_reg : std_logic;
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SIGNAL zero_net_addrs : ADDRESS_S_ZERO_T;
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SIGNAL zero_net_addrt : ADDRESS_T_ZERO_T;
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TYPE STATE_TYPE IS (
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S03,
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S01,
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S04,
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S06,
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S07,
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S08,
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S09,
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S10,
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S11,
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S12,
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S13,
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S17,
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S18,
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S19,
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S20,
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S21,
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S22,
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S23,
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S24,
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S25,
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S26,
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S27,
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S28,
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S29,
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S30,
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S31,
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S32,
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S33,
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S34,
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S35,
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S36,
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S37,
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S38,
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S39,
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S40,
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S41,
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S00,
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S46,
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S47,
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S02,
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S48,
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S14,
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S15,
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S01a
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);
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-- Declare current and next state signals
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SIGNAL current_state : STATE_TYPE;
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SIGNAL next_state : STATE_TYPE;
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BEGIN
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-----------------------------------------------------------------
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clocked_proc : PROCESS (
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clk_i
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)
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-----------------------------------------------------------------
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BEGIN
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IF (clk_i'EVENT AND clk_i = '1') THEN
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IF (rst_n_i = '0') THEN
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current_state <= S00;
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-- Default Reset Values
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ctrl_bias_reg <= (others => '0');
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ctrl_complete_reg <= '0';
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ctrl_din_reg <= (others => '0');
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ctrl_int_en_reg <= '0';
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ctrl_int_test_reg <= '0';
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ctrl_int_train_reg <= '0';
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ctrl_maxepoch_reg <= (others => '0');
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ctrl_offset_reg <= (others => '0');
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ctrl_rd_vec_reg <= (others => '0');
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ctrl_rdy_reg <= '0';
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ctrl_starti_val_reg <= (others => '0');
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ctrl_startj_val_reg <= (others => '0');
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ctrl_stat_a_reg <= (others => '0');
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ctrl_stopi_val_reg <= zero_net_addrs & '1';
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ctrl_stopj_val_reg <= zero_net_addrt & '1';
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ctrl_thres_reg <= (others => '0');
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ctrl_wr_vec_reg <= (others => '0');
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wb_adr_reg <= (others => '0');
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wb_cyc_reg <= '0';
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wb_dat_reg <= (others => '0');
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wb_stb_reg <= '0';
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wb_we_reg <= '0';
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ELSE
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current_state <= next_state;
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-- Default Assignment To Internals
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ctrl_bias_reg <= ctrl_bias_reg;
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ctrl_complete_reg <= ctrl_complete_reg OR ctrl_complete_i;
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ctrl_din_reg <= ctrl_din_reg;
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ctrl_int_en_reg <= ctrl_int_en_reg;
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ctrl_int_test_reg <= ctrl_int_test_reg OR ctrl_int_test_i;
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ctrl_int_train_reg <= ctrl_int_train_reg OR ctrl_int_train_i;
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ctrl_maxepoch_reg <= ctrl_maxepoch_reg;
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ctrl_offset_reg <= ctrl_offset_reg;
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ctrl_rd_vec_reg <= ctrl_rd_vec_reg;
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ctrl_rdy_reg <= ctrl_rdy1_i AND ctrl_rdy2_i AND ctrl_rdy3_i AND ctrl_rdy4_i AND ctrl_rdy5_i AND ctrl_rdy6_i;
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ctrl_starti_val_reg <= ctrl_starti_val_reg;
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ctrl_startj_val_reg <= ctrl_startj_val_reg;
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ctrl_stat_a_reg <= ctrl_stat_a_reg;
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ctrl_stopi_val_reg <= ctrl_stopi_val_reg;
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ctrl_stopj_val_reg <= ctrl_stopj_val_reg;
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ctrl_thres_reg <= ctrl_thres_reg;
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ctrl_wr_vec_reg <= ctrl_wr_vec_reg;
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wb_adr_reg <= wb_adr_i;
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wb_cyc_reg <= wb_cyc_i;
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wb_dat_reg <= wb_dat_i;
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wb_stb_reg <= wb_stb_i;
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wb_we_reg <= wb_we_i;
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-- Combined Actions
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CASE current_state IS
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-- READ Status A
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WHEN S03 =>
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ctrl_complete_reg <= ctrl_complete_i OR ( ctrl_complete_reg AND ( NOT ( ctrl_stat_a_reg (STAT_RD_WR_COMPLETE) ) ) );
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ctrl_int_test_reg <= ctrl_int_test_i OR ( ctrl_int_test_reg AND ( NOT ( ctrl_stat_a_reg (STAT_INT_TEST) ) ) );
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ctrl_int_train_reg <= ctrl_int_train_i OR ( ctrl_int_train_reg AND ( NOT ( ctrl_stat_a_reg (STAT_INT_TRAIN) ) ) );
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-- Wait for
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-- transfer/phase
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WHEN S01 =>
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ctrl_stat_a_reg (STAT_RDY) <= ctrl_rdy_reg;
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ctrl_stat_a_reg (STAT_LAT_RUN) <= ctrl_run7_i;
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ctrl_stat_a_reg (STAT_NOT_RDY) <= ctrl_not_rdy6_i;
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ctrl_stat_a_reg (STAT_INT_EN) <= ctrl_int_en_reg;
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ctrl_stat_a_reg (STAT_MEMERR) <= ctrl_memerr_i;
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ctrl_stat_a_reg (STAT_RD_WR_COMPLETE) <= ctrl_complete_reg AND ctrl_rdy_reg;
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ctrl_stat_a_reg (STAT_INT_TEST) <= ctrl_int_test_reg AND ctrl_rdy_reg;
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ctrl_stat_a_reg (STAT_INT_TRAIN) <= ctrl_int_train_reg AND ctrl_rdy_reg;
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-- WRITE Threshold
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-- register
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WHEN S04 =>
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ctrl_thres_reg <= wb_dat_reg (DATA_N);
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-- WRITE Bias
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-- register
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WHEN S08 =>
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ctrl_bias_reg <= wb_dat_reg (DATA_N);
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-- WRITE Offset
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-- register
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WHEN S10 =>
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ctrl_offset_reg <= wb_dat_reg (DATA_N);
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-- WRITE Maxepochs
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-- register
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WHEN S12 =>
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ctrl_maxepoch_reg <= wb_dat_reg;
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-- WRITE Start i
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-- register
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WHEN S18 =>
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ctrl_starti_val_reg <= wb_dat_reg (ADDRESS_S_N);
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-- WRITE Start j
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-- register
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WHEN S20 =>
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ctrl_startj_val_reg <= wb_dat_reg (ADDRESS_T_N);
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-- WRITE Stop i
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-- register
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WHEN S22 =>
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ctrl_stopi_val_reg <= wb_dat_reg (ADDRESS_S_N);
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-- WRITE Stop j
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-- register
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WHEN S24 =>
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ctrl_stopj_val_reg <= wb_dat_reg (ADDRESS_T_N);
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-- WRITE SMEM
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WHEN S32 =>
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ctrl_rd_vec_reg <= "00001";
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ctrl_wr_vec_reg <= "00001";
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ctrl_din_reg <= wb_dat_reg (DATA_N);
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-- WRITE TMEM
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WHEN S33 =>
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ctrl_rd_vec_reg <= "00010";
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ctrl_wr_vec_reg <= "00010";
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ctrl_din_reg <= wb_dat_reg (DATA_N);
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-- WRITE WMEM
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WHEN S34 =>
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ctrl_rd_vec_reg <= "00100";
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ctrl_wr_vec_reg <= "00100";
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ctrl_din_reg <= wb_dat_reg (DATA_N);
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-- WRITE YMEM
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WHEN S35 =>
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ctrl_rd_vec_reg <= "01000";
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ctrl_wr_vec_reg <= "01000";
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ctrl_din_reg <= wb_dat_reg (DATA_N);
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-- WRITE BIASMEM
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WHEN S36 =>
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ctrl_rd_vec_reg <= "10000";
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ctrl_wr_vec_reg <= "10000";
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ctrl_din_reg <= wb_dat_reg (DATA_N);
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-- READ SMEM
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WHEN S37 =>
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ctrl_rd_vec_reg <= "00001";
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-- READ TMEM
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WHEN S38 =>
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ctrl_rd_vec_reg <= "00010";
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-- READ WMEM
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WHEN S39 =>
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ctrl_rd_vec_reg <= "00100";
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-- READ YMEM
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WHEN S40 =>
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ctrl_rd_vec_reg <= "01000";
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324 |
|
|
-- READ BIASMEM
|
325 |
|
|
WHEN S41 =>
|
326 |
|
|
ctrl_rd_vec_reg <= "10000";
|
327 |
|
|
-- WRITE Status A
|
328 |
|
|
WHEN S02 =>
|
329 |
|
|
ctrl_int_en_reg <= wb_dat_reg (STAT_INT_EN);
|
330 |
|
|
WHEN OTHERS =>
|
331 |
|
|
NULL;
|
332 |
|
|
END CASE;
|
333 |
|
|
END IF;
|
334 |
|
|
END IF;
|
335 |
|
|
END PROCESS clocked_proc;
|
336 |
|
|
|
337 |
|
|
-----------------------------------------------------------------
|
338 |
|
|
nextstate_proc : PROCESS (
|
339 |
|
|
ctrl_rdy3_i,
|
340 |
|
|
ctrl_rdy4_i,
|
341 |
|
|
ctrl_rdy5_i,
|
342 |
|
|
current_state,
|
343 |
|
|
wb_adr_reg,
|
344 |
|
|
wb_cyc_reg,
|
345 |
|
|
wb_stb_reg,
|
346 |
|
|
wb_we_reg
|
347 |
|
|
)
|
348 |
|
|
-----------------------------------------------------------------
|
349 |
|
|
BEGIN
|
350 |
|
|
CASE current_state IS
|
351 |
|
|
-- READ Status A
|
352 |
|
|
WHEN S03 =>
|
353 |
|
|
next_state <= S01a;
|
354 |
|
|
-- Wait for
|
355 |
|
|
-- transfer/phase
|
356 |
|
|
WHEN S01 =>
|
357 |
|
|
IF (unsigned (wb_adr_reg) = WB_STAT_A AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
358 |
|
|
next_state <= S03;
|
359 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_THRES AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
360 |
|
|
next_state <= S06;
|
361 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
362 |
|
|
next_state <= S07;
|
363 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_OFFSET AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
364 |
|
|
next_state <= S09;
|
365 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_MAXEPOCH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
366 |
|
|
next_state <= S11;
|
367 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_IMAX AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
368 |
|
|
next_state <= S13;
|
369 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_STARTI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
370 |
|
|
next_state <= S17;
|
371 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_STOPI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
372 |
|
|
next_state <= S21;
|
373 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_STARTJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
374 |
|
|
next_state <= S19;
|
375 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_STOPJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
376 |
|
|
next_state <= S23;
|
377 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_EPOCH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
378 |
|
|
next_state <= S25;
|
379 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_WRLAT AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
380 |
|
|
next_state <= S26;
|
381 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_RDLAT AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
382 |
|
|
next_state <= S27;
|
383 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_ALLLAT AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
384 |
|
|
next_state <= S28;
|
385 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START5_S AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
386 |
|
|
next_state <= S37;
|
387 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START5_T AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
388 |
|
|
next_state <= S38;
|
389 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START5_W AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
390 |
|
|
next_state <= S39;
|
391 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START5_Y AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
392 |
|
|
next_state <= S40;
|
393 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START5_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
394 |
|
|
next_state <= S41;
|
395 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_THRES AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
396 |
|
|
next_state <= S04;
|
397 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
398 |
|
|
next_state <= S08;
|
399 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_OFFSET AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
400 |
|
|
next_state <= S10;
|
401 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_MAXEPOCH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
402 |
|
|
next_state <= S12;
|
403 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_STARTI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
404 |
|
|
next_state <= S18;
|
405 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_STOPI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
406 |
|
|
next_state <= S22;
|
407 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_STARTJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
408 |
|
|
next_state <= S20;
|
409 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_STOPJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
410 |
|
|
next_state <= S24;
|
411 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START3 AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
412 |
|
|
next_state <= S29;
|
413 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START4 AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
414 |
|
|
next_state <= S30;
|
415 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START5_S AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
416 |
|
|
next_state <= S32;
|
417 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START5_T AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
418 |
|
|
next_state <= S33;
|
419 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START5_W AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
420 |
|
|
next_state <= S34;
|
421 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START5_Y AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
422 |
|
|
next_state <= S35;
|
423 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START5_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
424 |
|
|
next_state <= S36;
|
425 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_START6 AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
426 |
|
|
next_state <= S31;
|
427 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_STAT_A AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
|
428 |
|
|
next_state <= S02;
|
429 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_JMAX AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
430 |
|
|
next_state <= S14;
|
431 |
|
|
ELSIF (unsigned (wb_adr_reg) = WB_MEMDATA_WIDTH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
|
432 |
|
|
next_state <= S15;
|
433 |
|
|
ELSIF (wb_stb_reg = '1' AND wb_cyc_reg = '1') THEN
|
434 |
|
|
next_state <= S48;
|
435 |
|
|
ELSE
|
436 |
|
|
next_state <= S01;
|
437 |
|
|
END IF;
|
438 |
|
|
-- WRITE Threshold
|
439 |
|
|
-- register
|
440 |
|
|
WHEN S04 =>
|
441 |
|
|
next_state <= S01a;
|
442 |
|
|
-- READ Threshold
|
443 |
|
|
-- register
|
444 |
|
|
WHEN S06 =>
|
445 |
|
|
next_state <= S01a;
|
446 |
|
|
-- READ Bias
|
447 |
|
|
-- register
|
448 |
|
|
WHEN S07 =>
|
449 |
|
|
next_state <= S01a;
|
450 |
|
|
-- WRITE Bias
|
451 |
|
|
-- register
|
452 |
|
|
WHEN S08 =>
|
453 |
|
|
next_state <= S01a;
|
454 |
|
|
-- READ Offset
|
455 |
|
|
-- register
|
456 |
|
|
WHEN S09 =>
|
457 |
|
|
next_state <= S01a;
|
458 |
|
|
-- WRITE Offset
|
459 |
|
|
-- register
|
460 |
|
|
WHEN S10 =>
|
461 |
|
|
next_state <= S01a;
|
462 |
|
|
-- READ Maxepochs
|
463 |
|
|
-- register
|
464 |
|
|
WHEN S11 =>
|
465 |
|
|
next_state <= S01a;
|
466 |
|
|
-- WRITE Maxepochs
|
467 |
|
|
-- register
|
468 |
|
|
WHEN S12 =>
|
469 |
|
|
next_state <= S01a;
|
470 |
|
|
-- READ maximum
|
471 |
|
|
-- rows i
|
472 |
|
|
WHEN S13 =>
|
473 |
|
|
next_state <= S01a;
|
474 |
|
|
-- READ Start i
|
475 |
|
|
-- register
|
476 |
|
|
WHEN S17 =>
|
477 |
|
|
next_state <= S01a;
|
478 |
|
|
-- WRITE Start i
|
479 |
|
|
-- register
|
480 |
|
|
WHEN S18 =>
|
481 |
|
|
next_state <= S01a;
|
482 |
|
|
-- READ Start j
|
483 |
|
|
-- register
|
484 |
|
|
WHEN S19 =>
|
485 |
|
|
next_state <= S01a;
|
486 |
|
|
-- WRITE Start j
|
487 |
|
|
-- register
|
488 |
|
|
WHEN S20 =>
|
489 |
|
|
next_state <= S01a;
|
490 |
|
|
-- READ Stop i
|
491 |
|
|
-- register
|
492 |
|
|
WHEN S21 =>
|
493 |
|
|
next_state <= S01a;
|
494 |
|
|
-- WRITE Stop i
|
495 |
|
|
-- register
|
496 |
|
|
WHEN S22 =>
|
497 |
|
|
next_state <= S01a;
|
498 |
|
|
-- READ Stop j
|
499 |
|
|
-- register
|
500 |
|
|
WHEN S23 =>
|
501 |
|
|
next_state <= S01a;
|
502 |
|
|
-- WRITE Stop j
|
503 |
|
|
-- register
|
504 |
|
|
WHEN S24 =>
|
505 |
|
|
next_state <= S01a;
|
506 |
|
|
-- READ Epochs
|
507 |
|
|
-- register
|
508 |
|
|
WHEN S25 =>
|
509 |
|
|
next_state <= S01a;
|
510 |
|
|
-- READ coded
|
511 |
|
|
-- WR Lat
|
512 |
|
|
-- register
|
513 |
|
|
WHEN S26 =>
|
514 |
|
|
next_state <= S01a;
|
515 |
|
|
-- READ coded
|
516 |
|
|
-- RD Lat
|
517 |
|
|
-- register
|
518 |
|
|
WHEN S27 =>
|
519 |
|
|
next_state <= S01a;
|
520 |
|
|
-- READ decimal
|
521 |
|
|
-- Latency register
|
522 |
|
|
WHEN S28 =>
|
523 |
|
|
next_state <= S01a;
|
524 |
|
|
-- Start INIT
|
525 |
|
|
WHEN S29 =>
|
526 |
|
|
IF (ctrl_rdy3_i = '0') THEN
|
527 |
|
|
next_state <= S01a;
|
528 |
|
|
ELSE
|
529 |
|
|
next_state <= S29;
|
530 |
|
|
END IF;
|
531 |
|
|
-- Start TEST
|
532 |
|
|
WHEN S30 =>
|
533 |
|
|
IF (ctrl_rdy4_i = '0') THEN
|
534 |
|
|
next_state <= S01a;
|
535 |
|
|
ELSE
|
536 |
|
|
next_state <= S30;
|
537 |
|
|
END IF;
|
538 |
|
|
-- Start TRAIN
|
539 |
|
|
WHEN S31 =>
|
540 |
|
|
next_state <= S01a;
|
541 |
|
|
-- WRITE SMEM
|
542 |
|
|
WHEN S32 =>
|
543 |
|
|
IF (ctrl_rdy5_i = '0') THEN
|
544 |
|
|
next_state <= S47;
|
545 |
|
|
END IF;
|
546 |
|
|
-- WRITE TMEM
|
547 |
|
|
WHEN S33 =>
|
548 |
|
|
IF (ctrl_rdy5_i = '0') THEN
|
549 |
|
|
next_state <= S47;
|
550 |
|
|
END IF;
|
551 |
|
|
-- WRITE WMEM
|
552 |
|
|
WHEN S34 =>
|
553 |
|
|
IF (ctrl_rdy5_i = '0') THEN
|
554 |
|
|
next_state <= S47;
|
555 |
|
|
END IF;
|
556 |
|
|
-- WRITE YMEM
|
557 |
|
|
WHEN S35 =>
|
558 |
|
|
IF (ctrl_rdy5_i = '0') THEN
|
559 |
|
|
next_state <= S47;
|
560 |
|
|
END IF;
|
561 |
|
|
-- WRITE BIASMEM
|
562 |
|
|
WHEN S36 =>
|
563 |
|
|
IF (ctrl_rdy5_i = '0') THEN
|
564 |
|
|
next_state <= S47;
|
565 |
|
|
END IF;
|
566 |
|
|
-- READ SMEM
|
567 |
|
|
WHEN S37 =>
|
568 |
|
|
IF (ctrl_rdy5_i = '0') THEN
|
569 |
|
|
next_state <= S46;
|
570 |
|
|
END IF;
|
571 |
|
|
-- READ TMEM
|
572 |
|
|
WHEN S38 =>
|
573 |
|
|
IF (ctrl_rdy5_i = '0') THEN
|
574 |
|
|
next_state <= S46;
|
575 |
|
|
END IF;
|
576 |
|
|
-- READ WMEM
|
577 |
|
|
WHEN S39 =>
|
578 |
|
|
IF (ctrl_rdy5_i = '0') THEN
|
579 |
|
|
next_state <= S46;
|
580 |
|
|
END IF;
|
581 |
|
|
-- READ YMEM
|
582 |
|
|
WHEN S40 =>
|
583 |
|
|
IF (ctrl_rdy5_i = '0') THEN
|
584 |
|
|
next_state <= S46;
|
585 |
|
|
END IF;
|
586 |
|
|
-- READ BIASMEM
|
587 |
|
|
WHEN S41 =>
|
588 |
|
|
IF (ctrl_rdy5_i = '0') THEN
|
589 |
|
|
next_state <= S46;
|
590 |
|
|
END IF;
|
591 |
|
|
-- Reset state
|
592 |
|
|
WHEN S00 =>
|
593 |
|
|
next_state <= S01;
|
594 |
|
|
-- READ xMEM
|
595 |
|
|
WHEN S46 =>
|
596 |
|
|
IF (ctrl_rdy5_i = '1') THEN
|
597 |
|
|
next_state <= S01a;
|
598 |
|
|
ELSE
|
599 |
|
|
next_state <= S46;
|
600 |
|
|
END IF;
|
601 |
|
|
-- WRITE xMEM
|
602 |
|
|
WHEN S47 =>
|
603 |
|
|
IF (ctrl_rdy5_i = '1') THEN
|
604 |
|
|
next_state <= S01a;
|
605 |
|
|
ELSE
|
606 |
|
|
next_state <= S47;
|
607 |
|
|
END IF;
|
608 |
|
|
-- WRITE Status A
|
609 |
|
|
WHEN S02 =>
|
610 |
|
|
next_state <= S01a;
|
611 |
|
|
-- Dummy
|
612 |
|
|
-- READ / WRITE
|
613 |
|
|
WHEN S48 =>
|
614 |
|
|
next_state <= S01a;
|
615 |
|
|
-- READ maximum
|
616 |
|
|
-- colums j
|
617 |
|
|
WHEN S14 =>
|
618 |
|
|
next_state <= S01a;
|
619 |
|
|
-- READ memory
|
620 |
|
|
-- data width
|
621 |
|
|
WHEN S15 =>
|
622 |
|
|
next_state <= S01a;
|
623 |
|
|
-- Waite State
|
624 |
|
|
WHEN S01a =>
|
625 |
|
|
next_state <= S01;
|
626 |
|
|
WHEN OTHERS =>
|
627 |
|
|
next_state <= S00;
|
628 |
|
|
END CASE;
|
629 |
|
|
END PROCESS nextstate_proc;
|
630 |
|
|
|
631 |
|
|
-----------------------------------------------------------------
|
632 |
|
|
output_proc : PROCESS (
|
633 |
|
|
ctrl_alllat_i,
|
634 |
|
|
ctrl_bias_reg,
|
635 |
|
|
ctrl_din_reg,
|
636 |
|
|
ctrl_dout_i,
|
637 |
|
|
ctrl_epoch_i,
|
638 |
|
|
ctrl_int_en_reg,
|
639 |
|
|
ctrl_int_test_reg,
|
640 |
|
|
ctrl_int_train_reg,
|
641 |
|
|
ctrl_maxepoch_reg,
|
642 |
|
|
ctrl_offset_reg,
|
643 |
|
|
ctrl_rd_vec_reg,
|
644 |
|
|
ctrl_rdlat_i,
|
645 |
|
|
ctrl_rdy3_i,
|
646 |
|
|
ctrl_rdy4_i,
|
647 |
|
|
ctrl_rdy5_i,
|
648 |
|
|
ctrl_starti_val_reg,
|
649 |
|
|
ctrl_startj_val_reg,
|
650 |
|
|
ctrl_stat_a_reg,
|
651 |
|
|
ctrl_stopi_val_reg,
|
652 |
|
|
ctrl_stopj_val_reg,
|
653 |
|
|
ctrl_thres_reg,
|
654 |
|
|
ctrl_wr_vec_reg,
|
655 |
|
|
ctrl_wrlat_i,
|
656 |
|
|
current_state,
|
657 |
|
|
wb_cyc_i,
|
658 |
|
|
wb_dat_reg,
|
659 |
|
|
wb_stb_i
|
660 |
|
|
)
|
661 |
|
|
-----------------------------------------------------------------
|
662 |
|
|
BEGIN
|
663 |
|
|
-- Default Assignment
|
664 |
|
|
ctrl_bias_o <= ctrl_bias_reg;
|
665 |
|
|
ctrl_clear_epoch_o <= '0';
|
666 |
|
|
ctrl_din_o <= ctrl_din_reg;
|
667 |
|
|
ctrl_int_o <= ctrl_int_en_reg AND (ctrl_int_train_reg OR ctrl_int_test_reg);
|
668 |
|
|
ctrl_maxepoch_o <= ctrl_maxepoch_reg;
|
669 |
|
|
ctrl_offset_o <= ctrl_offset_reg;
|
670 |
|
|
ctrl_rd_vec_o <= ctrl_rd_vec_reg;
|
671 |
|
|
ctrl_set_starti_o <= '0';
|
672 |
|
|
ctrl_set_startj_o <= '0';
|
673 |
|
|
ctrl_start3_o <= '0';
|
674 |
|
|
ctrl_start4_o <= '0';
|
675 |
|
|
ctrl_start5_o <= '0';
|
676 |
|
|
ctrl_start6_o <= '0';
|
677 |
|
|
ctrl_starti_val_o <= ctrl_starti_val_reg;
|
678 |
|
|
ctrl_startj_val_o <= ctrl_startj_val_reg;
|
679 |
|
|
ctrl_stopi_val_o <= ctrl_stopi_val_reg;
|
680 |
|
|
ctrl_stopj_val_o <= ctrl_stopj_val_reg;
|
681 |
|
|
ctrl_thres_o <= ctrl_thres_reg;
|
682 |
|
|
ctrl_wr_vec_o <= ctrl_wr_vec_reg;
|
683 |
|
|
wb_ack_o <= '0';
|
684 |
|
|
wb_dat_o <= (others => '0');
|
685 |
|
|
-- Default Assignment To Internals
|
686 |
|
|
zero_net_addrs <= (others => '0');
|
687 |
|
|
zero_net_addrt <= (others => '0');
|
688 |
|
|
|
689 |
|
|
-- Combined Actions
|
690 |
|
|
CASE current_state IS
|
691 |
|
|
-- READ Status A
|
692 |
|
|
WHEN S03 =>
|
693 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
694 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_stat_a_reg ) )), WB_DATA_WIDTH ) );
|
695 |
|
|
-- WRITE Threshold
|
696 |
|
|
-- register
|
697 |
|
|
WHEN S04 =>
|
698 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
699 |
|
|
-- READ Threshold
|
700 |
|
|
-- register
|
701 |
|
|
WHEN S06 =>
|
702 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
703 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_thres_reg ) )), WB_DATA_WIDTH ) );
|
704 |
|
|
-- READ Bias
|
705 |
|
|
-- register
|
706 |
|
|
WHEN S07 =>
|
707 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
708 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_bias_reg ) )), WB_DATA_WIDTH ) );
|
709 |
|
|
-- WRITE Bias
|
710 |
|
|
-- register
|
711 |
|
|
WHEN S08 =>
|
712 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
713 |
|
|
-- READ Offset
|
714 |
|
|
-- register
|
715 |
|
|
WHEN S09 =>
|
716 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
717 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_offset_reg ) )), WB_DATA_WIDTH ) );
|
718 |
|
|
-- WRITE Offset
|
719 |
|
|
-- register
|
720 |
|
|
WHEN S10 =>
|
721 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
722 |
|
|
-- READ Maxepochs
|
723 |
|
|
-- register
|
724 |
|
|
WHEN S11 =>
|
725 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
726 |
|
|
wb_dat_o <= ctrl_maxepoch_reg;
|
727 |
|
|
-- WRITE Maxepochs
|
728 |
|
|
-- register
|
729 |
|
|
WHEN S12 =>
|
730 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
731 |
|
|
-- READ maximum
|
732 |
|
|
-- rows i
|
733 |
|
|
WHEN S13 =>
|
734 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
735 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( ( I_MAX ) )), WB_DATA_WIDTH ) );
|
736 |
|
|
-- READ Start i
|
737 |
|
|
-- register
|
738 |
|
|
WHEN S17 =>
|
739 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
740 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_starti_val_reg ) )), WB_DATA_WIDTH ) );
|
741 |
|
|
-- WRITE Start i
|
742 |
|
|
-- register
|
743 |
|
|
WHEN S18 =>
|
744 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
745 |
|
|
-- READ Start j
|
746 |
|
|
-- register
|
747 |
|
|
WHEN S19 =>
|
748 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
749 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_startj_val_reg ) )), WB_DATA_WIDTH ) );
|
750 |
|
|
-- WRITE Start j
|
751 |
|
|
-- register
|
752 |
|
|
WHEN S20 =>
|
753 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
754 |
|
|
-- READ Stop i
|
755 |
|
|
-- register
|
756 |
|
|
WHEN S21 =>
|
757 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
758 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_stopi_val_reg ) )), WB_DATA_WIDTH ) );
|
759 |
|
|
-- WRITE Stop i
|
760 |
|
|
-- register
|
761 |
|
|
WHEN S22 =>
|
762 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
763 |
|
|
-- READ Stop j
|
764 |
|
|
-- register
|
765 |
|
|
WHEN S23 =>
|
766 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
767 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_stopj_val_reg ) )), WB_DATA_WIDTH ) );
|
768 |
|
|
-- WRITE Stop j
|
769 |
|
|
-- register
|
770 |
|
|
WHEN S24 =>
|
771 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
772 |
|
|
-- READ Epochs
|
773 |
|
|
-- register
|
774 |
|
|
WHEN S25 =>
|
775 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
776 |
|
|
wb_dat_o <= ctrl_epoch_i;
|
777 |
|
|
-- READ coded
|
778 |
|
|
-- WR Lat
|
779 |
|
|
-- register
|
780 |
|
|
WHEN S26 =>
|
781 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
782 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_wrlat_i ) )), WB_DATA_WIDTH ) );
|
783 |
|
|
-- READ coded
|
784 |
|
|
-- RD Lat
|
785 |
|
|
-- register
|
786 |
|
|
WHEN S27 =>
|
787 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
788 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_rdlat_i ) )), WB_DATA_WIDTH ) );
|
789 |
|
|
-- READ decimal
|
790 |
|
|
-- Latency register
|
791 |
|
|
WHEN S28 =>
|
792 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
793 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_alllat_i ) )), WB_DATA_WIDTH ) );
|
794 |
|
|
-- Start INIT
|
795 |
|
|
WHEN S29 =>
|
796 |
|
|
wb_ack_o <= NOT ctrl_rdy3_i AND wb_stb_i AND wb_cyc_i;
|
797 |
|
|
ctrl_start3_o <= '1';
|
798 |
|
|
-- Start TEST
|
799 |
|
|
WHEN S30 =>
|
800 |
|
|
wb_ack_o <= NOT ctrl_rdy4_i AND wb_stb_i AND wb_cyc_i;
|
801 |
|
|
ctrl_start4_o <= '1';
|
802 |
|
|
-- Start TRAIN
|
803 |
|
|
WHEN S31 =>
|
804 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
805 |
|
|
ctrl_start6_o <= '1';
|
806 |
|
|
ctrl_clear_epoch_o <= wb_dat_reg (0);
|
807 |
|
|
-- WRITE SMEM
|
808 |
|
|
WHEN S32 =>
|
809 |
|
|
ctrl_start5_o <= '1';
|
810 |
|
|
-- WRITE TMEM
|
811 |
|
|
WHEN S33 =>
|
812 |
|
|
ctrl_start5_o <= '1';
|
813 |
|
|
-- WRITE WMEM
|
814 |
|
|
WHEN S34 =>
|
815 |
|
|
ctrl_start5_o <= '1';
|
816 |
|
|
-- WRITE YMEM
|
817 |
|
|
WHEN S35 =>
|
818 |
|
|
ctrl_start5_o <= '1';
|
819 |
|
|
-- WRITE BIASMEM
|
820 |
|
|
WHEN S36 =>
|
821 |
|
|
ctrl_start5_o <= '1';
|
822 |
|
|
-- READ SMEM
|
823 |
|
|
WHEN S37 =>
|
824 |
|
|
ctrl_start5_o <= '1';
|
825 |
|
|
-- READ TMEM
|
826 |
|
|
WHEN S38 =>
|
827 |
|
|
ctrl_start5_o <= '1';
|
828 |
|
|
-- READ WMEM
|
829 |
|
|
WHEN S39 =>
|
830 |
|
|
ctrl_start5_o <= '1';
|
831 |
|
|
-- READ YMEM
|
832 |
|
|
WHEN S40 =>
|
833 |
|
|
ctrl_start5_o <= '1';
|
834 |
|
|
-- READ BIASMEM
|
835 |
|
|
WHEN S41 =>
|
836 |
|
|
ctrl_start5_o <= '1';
|
837 |
|
|
-- READ xMEM
|
838 |
|
|
WHEN S46 =>
|
839 |
|
|
wb_ack_o <= ctrl_rdy5_i AND wb_stb_i AND wb_cyc_i;
|
840 |
|
|
wb_dat_o <= std_logic_vector ( conv_signed ( (conv_integer ( signed ( ctrl_dout_i ) )), WB_DATA_WIDTH ) );
|
841 |
|
|
-- WRITE xMEM
|
842 |
|
|
WHEN S47 =>
|
843 |
|
|
wb_ack_o <= ctrl_rdy5_i AND wb_stb_i AND wb_cyc_i;
|
844 |
|
|
-- WRITE Status A
|
845 |
|
|
WHEN S02 =>
|
846 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
847 |
|
|
-- Dummy
|
848 |
|
|
-- READ / WRITE
|
849 |
|
|
WHEN S48 =>
|
850 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
851 |
|
|
wb_dat_o <= (others => '0');
|
852 |
|
|
-- READ maximum
|
853 |
|
|
-- colums j
|
854 |
|
|
WHEN S14 =>
|
855 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
856 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( ( J_MAX ) )), WB_DATA_WIDTH ) );
|
857 |
|
|
-- READ memory
|
858 |
|
|
-- data width
|
859 |
|
|
WHEN S15 =>
|
860 |
|
|
wb_ack_o <= wb_stb_i AND wb_cyc_i;
|
861 |
|
|
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( ( DATA_WIDTH ) )), WB_DATA_WIDTH ) );
|
862 |
|
|
WHEN OTHERS =>
|
863 |
|
|
NULL;
|
864 |
|
|
END CASE;
|
865 |
|
|
END PROCESS output_proc;
|
866 |
|
|
|
867 |
|
|
END fsm;
|